diff options
| author | Dan Handley <dan.handley@arm.com> | 2015-03-19 19:22:44 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2015-04-28 19:50:56 +0100 |
| commit | f8b0b22a1b2f7c563e0881fc5ee913f469d324a7 (patch) | |
| tree | f5d0c55b51fb3f6d63deaae2060fdc6206ab52ed | |
| parent | 3fc4124c7513554dc14a83a0b94010ce771e7e1c (diff) | |
Migrate Juno port to use common code
Major update to the Juno platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.
Also move the ARM SoC specific security setup (i.e. NIC-400 and PCIe
initialization) from BL1 to `plat_arm_security_setup()` in BL2,
where the other security setup is done.
Change-Id: Ic9fe01bae8ed382bfb04fc5839a4cfff332eb124
26 files changed, 127 insertions, 3519 deletions
diff --git a/plat/juno/aarch64/bl1_plat_helpers.S b/plat/juno/aarch64/bl1_plat_helpers.S deleted file mode 100644 index 9b92979..0000000 --- a/plat/juno/aarch64/bl1_plat_helpers.S +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch.h> -#include <asm_macros.S> -#include "../juno_def.h" - - .globl platform_is_primary_cpu - .globl platform_get_entrypoint - .globl platform_cold_boot_init - .globl plat_secondary_cold_boot_setup - - /* ----------------------------------------------------- - * unsigned int platform_is_primary_cpu (unsigned int mpid); - * - * Given the mpidr say whether this cpu is the primary - * cpu (applicable ony after a cold boot) - * ----------------------------------------------------- - */ -func platform_is_primary_cpu - mov x9, x30 - bl platform_get_core_pos - ldr x1, =SCP_BOOT_CFG_ADDR - ldr x1, [x1] - ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK - cmp x0, x1 - cset x0, eq - ret x9 -endfunc platform_is_primary_cpu - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Juno todo: Implement secondary CPU cold boot setup on Juno */ -cb_panic: - b cb_panic -endfunc plat_secondary_cold_boot_setup - - - /* ----------------------------------------------------- - * void platform_get_entrypoint (unsigned int mpid); - * - * Main job of this routine is to distinguish between - * a cold and warm boot. - * On a cold boot the secondaries first wait for the - * platform to be initialized after which they are - * hotplugged in. The primary proceeds to perform the - * platform initialization. - * On a warm boot, each cpu jumps to the address in its - * mailbox. - * - * TODO: Not a good idea to save lr in a temp reg - * ----------------------------------------------------- - */ -func platform_get_entrypoint - mov x9, x30 // lr - bl platform_get_core_pos - ldr x1, =TRUSTED_MAILBOXES_BASE - lsl x0, x0, #TRUSTED_MAILBOX_SHIFT - ldr x0, [x1, x0] - ret x9 -endfunc platform_get_entrypoint - - - /* ----------------------------------------------------- - * void platform_cold_boot_init (bl1_main function); - * - * Routine called only by the primary cpu after a cold - * boot to perform early platform initialization - * ----------------------------------------------------- - */ -func platform_cold_boot_init - mov x20, x0 - - /* --------------------------------------------- - * Give ourselves a small coherent stack to - * ease the pain of initializing the MMU and - * CCI in assembler - * --------------------------------------------- - */ - mrs x0, mpidr_el1 - bl platform_set_coherent_stack - - /* --------------------------------------------- - * Architectural init. can be generic e.g. - * enabling stack alignment and platform spec- - * ific e.g. MMU & page table setup as per the - * platform memory map. Perform the latter here - * and the former in bl1_main. - * --------------------------------------------- - */ - bl bl1_early_platform_setup - bl bl1_plat_arch_setup - - /* --------------------------------------------- - * Give ourselves a stack allocated in Normal - * -IS-WBWA memory - * --------------------------------------------- - */ - mrs x0, mpidr_el1 - bl platform_set_stack - - /* --------------------------------------------- - * Jump to the main function. Returning from it - * is a terminal error. - * --------------------------------------------- - */ - blr x20 - -cb_init_panic: - b cb_init_panic -endfunc platform_cold_boot_init diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c deleted file mode 100644 index 6b6e185..0000000 --- a/plat/juno/aarch64/juno_common.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch_helpers.h> -#include <arm_gic.h> -#include <assert.h> -#include <bl_common.h> -#include <cci.h> -#include <debug.h> -#include <mmio.h> -#include <platform.h> -#include <platform_def.h> -#include <xlat_tables.h> -#include "../juno_def.h" - -#define MAP_MHU_SECURE MAP_REGION_FLAT(MHU_SECURE_BASE, \ - MHU_SECURE_SIZE, \ - (MHU_PAYLOAD_CACHED ? \ - MT_MEMORY : MT_DEVICE) \ - | MT_RW | MT_SECURE) - -#define MAP_FLASH MAP_REGION_FLAT(FLASH_BASE, \ - FLASH_SIZE, \ - MT_MEMORY | MT_RO | MT_SECURE) - -#define MAP_IOFPGA MAP_REGION_FLAT(IOFPGA_BASE, \ - IOFPGA_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ - DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ - DEVICE1_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \ - DRAM_NS_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ - TSP_SEC_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -/* - * Table of regions for different BL stages to map using the MMU. - * This doesn't include Trusted RAM as the 'mem_layout' argument passed to - * configure_mmu_elx() will give the available subset of that, - */ -#if IMAGE_BL1 -static const mmap_region_t juno_mmap[] = { - MAP_MHU_SECURE, - MAP_FLASH, - MAP_IOFPGA, - MAP_DEVICE0, - MAP_DEVICE1, - {0} -}; -#endif -#if IMAGE_BL2 -static const mmap_region_t juno_mmap[] = { - MAP_MHU_SECURE, - MAP_FLASH, - MAP_IOFPGA, - MAP_DEVICE0, - MAP_DEVICE1, - MAP_NS_DRAM, - MAP_TSP_MEM, - {0} -}; -#endif -#if IMAGE_BL31 -static const mmap_region_t juno_mmap[] = { - MAP_MHU_SECURE, - MAP_IOFPGA, - MAP_DEVICE0, - MAP_DEVICE1, - {0} -}; -#endif -#if IMAGE_BL32 -static const mmap_region_t juno_mmap[] = { - MAP_IOFPGA, - MAP_DEVICE0, - MAP_DEVICE1, - {0} -}; -#endif - -CASSERT(ARRAY_SIZE(juno_mmap) + JUNO_BL_REGIONS \ - <= MAX_MMAP_REGIONS, assert_max_mmap_regions); - -/* Array of secure interrupts to be configured by the gic driver */ -const unsigned int irq_sec_array[] = { - IRQ_MHU, - IRQ_GPU_SMMU_0, - IRQ_GPU_SMMU_1, - IRQ_ETR_SMMU, - IRQ_TZC400, - IRQ_TZ_WDOG, - IRQ_SEC_PHY_TIMER, - IRQ_SEC_SGI_0, - IRQ_SEC_SGI_1, - IRQ_SEC_SGI_2, - IRQ_SEC_SGI_3, - IRQ_SEC_SGI_4, - IRQ_SEC_SGI_5, - IRQ_SEC_SGI_6, - IRQ_SEC_SGI_7 -}; - -static const int cci_map[] = { - CCI400_CLUSTER0_SL_IFACE_IX, - CCI400_CLUSTER1_SL_IFACE_IX -}; - -void plat_cci_init(void) -{ - cci_init(CCI400_BASE, - cci_map, - ARRAY_SIZE(cci_map)); -} - -/******************************************************************************* - * Macro generating the code for the function setting up the pagetables as per - * the platform memory map & initialize the mmu, for the given exception level - ******************************************************************************/ -#if USE_COHERENT_MEM -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void configure_mmu_el##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long ro_start, \ - unsigned long ro_limit, \ - unsigned long coh_start, \ - unsigned long coh_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_MEMORY | MT_RO | MT_SECURE); \ - mmap_add_region(coh_start, coh_start, \ - coh_limit - coh_start, \ - MT_DEVICE | MT_RW | MT_SECURE); \ - mmap_add(juno_mmap); \ - init_xlat_tables(); \ - \ - enable_mmu_el##_el(0); \ - } -#else -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void configure_mmu_el##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long ro_start, \ - unsigned long ro_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_MEMORY | MT_RO | MT_SECURE); \ - mmap_add(juno_mmap); \ - init_xlat_tables(); \ - \ - enable_mmu_el##_el(0); \ - } -#endif -/* Define EL1 and EL3 variants of the function initialising the MMU */ -DEFINE_CONFIGURE_MMU_EL(1) -DEFINE_CONFIGURE_MMU_EL(3) - - -unsigned long plat_get_ns_image_entrypoint(void) -{ - return NS_IMAGE_OFFSET; -} - -uint64_t plat_get_syscnt_freq(void) -{ - uint64_t counter_base_frequency; - - /* Read the frequency from Frequency modes table */ - counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); - - /* The first entry of the frequency modes table must not be 0 */ - if (counter_base_frequency == 0) - panic(); - - return counter_base_frequency; -} - -void plat_gic_init(void) -{ - arm_gic_init(GICC_BASE, - GICD_BASE, - 0, - irq_sec_array, - ARRAY_SIZE(irq_sec_array)); -} diff --git a/plat/juno/aarch64/plat_helpers.S b/plat/juno/aarch64/plat_helpers.S index 6fa66e1..6d31847 100644 --- a/plat/juno/aarch64/plat_helpers.S +++ b/plat/juno/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -32,90 +32,12 @@ #include <asm_macros.S> #include <bl_common.h> #include <cortex_a57.h> -#include <cpu_macros.S> -#include <platform_def.h> +#include <v2m_def.h> #include "../juno_def.h" - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_report_exception - .globl plat_reset_handler - .globl platform_get_core_pos - .globl platform_mem_init - - /* Define a crash console for the plaform */ -#define JUNO_CRASH_CONSOLE_BASE PL011_UART3_BASE - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, JUNO_CRASH_CONSOLE_BASE - mov_imm x1, PL011_UART3_CLK_IN_HZ - mov_imm x2, PL011_BAUDRATE - b console_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(int c) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, JUNO_CRASH_CONSOLE_BASE - b console_core_putc -endfunc plat_crash_console_putc - - /* --------------------------------------------- - * void plat_report_exception(unsigned int type) - * Function to report an unhandled exception - * with platform-specific means. - * On Juno platform, it updates the LEDs - * to indicate where we are - * --------------------------------------------- - */ -func plat_report_exception - mrs x1, CurrentEl - lsr x1, x1, #MODE_EL_SHIFT - lsl x1, x1, #SYS_LED_EL_SHIFT - lsl x0, x0, #SYS_LED_EC_SHIFT - mov x2, #(SECURE << SYS_LED_SS_SHIFT) - orr x0, x0, x2 - orr x0, x0, x1 - mov x1, #VE_SYSREGS_BASE - add x1, x1, #V2M_SYS_LED - str w0, [x1] - ret -endfunc plat_report_exception - - /* - * Return 0 to 3 for the A53s and 4 or 5 for the A57s - */ -func platform_get_core_pos - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap A53/A57 order - add x0, x1, x0, LSR #6 - ret -endfunc platform_get_core_pos + .globl plat_reset_handler - /* ----------------------------------------------------- - * void platform_mem_init(void); - * - * We don't need to carry out any memory initialization - * on Juno. The Secure RAM is accessible straight away. - * ----------------------------------------------------- - */ -func platform_mem_init - ret -endfunc platform_mem_init /* -------------------------------------------------------------------- * void plat_reset_handler(void); @@ -149,10 +71,10 @@ func plat_reset_handler * -------------------------------------------------------------------- */ /* Read the V2M SYS_ID register */ - mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID) + mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) ldr w1, [x0] /* Extract board revision from the SYS_ID */ - ubfx x1, x1, #SYS_ID_REV_SHIFT, #4 + ubfx x1, x1, #V2M_SYS_ID_REV_SHIFT, #4 /* * On Juno R0: x2 := REV_JUNO_R0 - 1 = 0 * On Juno R1: x2 := REV_JUNO_R1 - 1 = 1 @@ -183,7 +105,8 @@ A57: mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES cbnz x2, apply_l2_ram_latencies /* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */ - orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT) + orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << \ + L2CTLR_TAG_RAM_LATENCY_SHIFT) apply_l2_ram_latencies: msr L2CTLR_EL1, x0 diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c deleted file mode 100644 index 3b3471a..0000000 --- a/plat/juno/bl1_plat_setup.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch_helpers.h> -#include <assert.h> -#include <bl_common.h> -#include <cci.h> -#include <console.h> -#include <debug.h> -#include <mmio.h> -#include <platform.h> -#include <platform_def.h> -#include "../../bl1/bl1_private.h" -#include "juno_def.h" -#include "juno_private.h" - -#if USE_COHERENT_MEM -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - ******************************************************************************/ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) -#endif - -/* Data structure which holds the extents of the trusted RAM for BL1 */ -static meminfo_t bl1_tzram_layout; - -meminfo_t *bl1_plat_sec_mem_layout(void) -{ - return &bl1_tzram_layout; -} - -/******************************************************************************* - * Perform any BL1 specific platform actions. - ******************************************************************************/ -void bl1_early_platform_setup(void) -{ - const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; - - /* Initialize the console to provide early debug support */ - console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); - - /* - * Enable CCI-400 for this cluster. No need for locks as no other cpu is - * active at the moment - */ - plat_cci_init(); - cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); - - /* Allow BL1 to see the whole Trusted RAM */ - bl1_tzram_layout.total_base = TZRAM_BASE; - bl1_tzram_layout.total_size = TZRAM_SIZE; - - /* Calculate how much RAM BL1 is using and how much remains free */ - bl1_tzram_layout.free_base = TZRAM_BASE; - bl1_tzram_layout.free_size = TZRAM_SIZE; - reserve_mem(&bl1_tzram_layout.free_base, - &bl1_tzram_layout.free_size, - BL1_RAM_BASE, - bl1_size); - - INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, - bl1_size); -} - - -/* - * Address of slave 'n' security setting in the NIC-400 address region - * control - * TODO: Ideally this macro should be moved in a "nic-400.h" header file but - * it would be the only thing in there so it's not worth it at the moment. - */ -#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) - -static void init_nic400(void) -{ - /* - * NIC-400 Access Control Initialization - * - * Define access privileges by setting each corresponding bit to: - * 0 = Secure access only - * 1 = Non-secure access allowed - */ - - /* - * Allow non-secure access to some SOC regions, excluding UART1, which - * remains secure. - * Note: This is the NIC-400 device on the SOC - */ - mmio_write_32(SOC_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0); - mmio_write_32(SOC_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0); - mmio_write_32(SOC_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0); - mmio_write_32(SOC_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0); - mmio_write_32(SOC_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0); - mmio_write_32(SOC_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE), - ~SOC_NIC400_BOOTSEC_BRIDGE_UART1); - - /* - * Allow non-secure access to some CSS regions. - * Note: This is the NIC-400 device on the CSS - */ - mmio_write_32(CSS_NIC400_BASE + - NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), - ~0); -} - - -#define PCIE_SECURE_REG 0x3000 -#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */ - -static void init_pcie(void) -{ - /* - * PCIE Root Complex Security settings to enable non-secure - * access to config registers. - */ - mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK); -} - - -/******************************************************************************* - * Function which will perform any remaining platform-specific setup that can - * occur after the MMU and data cache have been enabled. - ******************************************************************************/ -void bl1_platform_setup(void) -{ - init_nic400(); - init_pcie(); - - /* Initialise the IO layer and register platform IO devices */ - io_setup(); - - /* Enable and initialize the System level generic timer */ - mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); -} - - -/******************************************************************************* - * Perform the very early platform specific architecture setup here. At the - * moment this only does basic initialization. Later architectural setup - * (bl1_arch_setup()) does not do anything platform specific. - ******************************************************************************/ -void bl1_plat_arch_setup(void) -{ - configure_mmu_el3(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - TZROM_BASE, - TZROM_BASE + TZROM_SIZE -#if USE_COHERENT_MEM - , BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT -#endif - ); -} - -/******************************************************************************* - * Before calling this function BL2 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL2 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - ******************************************************************************/ -void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, - entry_point_info_t *bl2_ep) -{ - SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); - bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); -} diff --git a/plat/juno/bl2_plat_setup.c b/plat/juno/bl2_plat_setup.c deleted file mode 100644 index d7b2f76..0000000 --- a/plat/juno/bl2_plat_setup.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch_helpers.h> -#include <assert.h> -#include <bl_common.h> -#include <console.h> -#include <debug.h> -#include <platform.h> -#include <platform_def.h> -#include <string.h> -#include "juno_def.h" -#include "juno_private.h" -#include "scp_bootloader.h" - -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - ******************************************************************************/ -extern unsigned long __RO_START__; -extern unsigned long __RO_END__; - -#if USE_COHERENT_MEM -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; -#endif - -/* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. - */ -#define BL2_RO_BASE (unsigned long)(&__RO_START__) -#define BL2_RO_LIMIT (unsigned long)(&__RO_END__) - -#if USE_COHERENT_MEM -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) -#endif - -/* Data structure which holds the extents of the trusted RAM for BL2 */ -static meminfo_t bl2_tzram_layout -__attribute__ ((aligned(CACHE_WRITEBACK_GRANULE))); - -/******************************************************************************* - * Structure which holds the arguments which need to be passed to BL3-1 - ******************************************************************************/ -static bl2_to_bl31_params_mem_t bl31_params_mem; - -meminfo_t *bl2_plat_sec_mem_layout(void) -{ - return &bl2_tzram_layout; -} - -/******************************************************************************* - * This function assigns a pointer to the memory that the platform has kept - * aside to pass platform specific and trusted firmware related information - * to BL31. This memory is allocated by allocating memory to - * bl2_to_bl31_params_mem_t structure which is a superset of all the - * structure whose information is passed to BL31 - * NOTE: This function should be called only once and should be done - * before generating params to BL31 - ******************************************************************************/ -bl31_params_t *bl2_plat_get_bl31_params(void) -{ - bl31_params_t *bl2_to_bl31_params; - - /* - * Initialise the memory for all the arguments that needs to - * be passed to BL3-1 - */ - memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); - - /* Assign memory for TF related information */ - bl2_to_bl31_params = &bl31_params_mem.bl31_params; - SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); - - /* Fill BL3-1 related information */ - bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); - - /* Fill BL3-2 related information if it exists */ -#if BL32_BASE - bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, - VERSION_1, 0); - bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); -#endif - - /* Fill BL3-3 related information */ - bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, - PARAM_EP, VERSION_1, 0); - - /* BL3-3 expects to receive the primary CPU MPID (through x0) */ - bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); - - bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); - - return bl2_to_bl31_params; -} - -/******************************************************************************* - * This function returns a pointer to the shared memory that the platform - * has kept to point to entry point information of BL31 to BL2 - ******************************************************************************/ -struct entry_point_info *bl2_plat_get_bl31_ep_info(void) -{ -#if DEBUG - bl31_params_mem.bl31_ep_info.args.arg1 = JUNO_BL31_PLAT_PARAM_VAL; -#endif - - return &bl31_params_mem.bl31_ep_info; -} - -/******************************************************************************* - * BL1 has passed the extents of the trusted RAM that should be visible to BL2 - * in x0. This memory layout is sitting at the base of the free trusted RAM. - * Copy it to a safe loaction before its reclaimed by later BL2 functionality. - ******************************************************************************/ -void bl2_early_platform_setup(meminfo_t *mem_layout) -{ - /* Initialize the console to provide early debug support */ - console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); - - /* Setup the BL2 memory layout */ - bl2_tzram_layout = *mem_layout; - - /* Initialise the IO layer and register platform IO devices */ - io_setup(); -} - -/******************************************************************************* - * Perform platform specific setup, i.e. initialize the IO layer, load BL3-0 - * image and initialise the memory location to use for passing arguments to - * BL3-1. - ******************************************************************************/ -void bl2_platform_setup(void) -{ - /* Initialize the secure environment */ - plat_security_setup(); -} - -/* Flush the TF params and the TF plat params */ -void bl2_plat_flush_bl31_params(void) -{ - flush_dcache_range((unsigned long)&bl31_params_mem, - sizeof(bl2_to_bl31_params_mem_t)); -} - -/******************************************************************************* - * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. - ******************************************************************************/ -void bl2_plat_arch_setup(void) -{ - configure_mmu_el1(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL2_RO_BASE, - BL2_RO_LIMIT -#if USE_COHERENT_MEM - , BL2_COHERENT_RAM_BASE, - BL2_COHERENT_RAM_LIMIT -#endif - ); -} - -/******************************************************************************* - * Populate the extents of memory available for loading BL3-0, i.e. anywhere - * in trusted RAM as long as it doesn't overwrite BL2. - ******************************************************************************/ -void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) -{ - *bl30_meminfo = bl2_tzram_layout; -} - -/******************************************************************************* - * Transfer BL3-0 from Trusted RAM using the SCP Download protocol. - * Return 0 on success, -1 otherwise. - ******************************************************************************/ -int bl2_plat_handle_bl30(image_info_t *bl30_image_info) -{ - int ret; - - ret = scp_bootloader_transfer((void *)bl30_image_info->image_base, - bl30_image_info->image_size); - - if (ret == 0) - INFO("BL2: BL3-0 transferred to SCP\n\r"); - else - ERROR("BL2: BL3-0 transfer failure\n\r"); - - return ret; -} - -/******************************************************************************* - * Before calling this function BL31 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL31 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - ******************************************************************************/ -void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, - entry_point_info_t *bl31_ep_info) -{ - SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); - bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); -} - - -/******************************************************************************* - * Before calling this function BL32 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL32 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - ******************************************************************************/ -void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, - entry_point_info_t *bl32_ep_info) -{ - SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - bl32_ep_info->spsr = 0; -} - -/******************************************************************************* - * Before calling this function BL33 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL33 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - ******************************************************************************/ -void bl2_plat_set_bl33_ep_info(image_info_t *image, - entry_point_info_t *bl33_ep_info) -{ - unsigned long el_status; - unsigned int mode; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - if (el_status) - mode = MODE_EL2; - else - mode = MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); - SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); -} - -/******************************************************************************* - * Populate the extents of memory available for loading BL3-2 - ******************************************************************************/ -void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) -{ - /* - * Populate the extents of memory available for loading BL3-2. - */ - bl32_meminfo->total_base = BL32_BASE; - bl32_meminfo->free_base = BL32_BASE; - bl32_meminfo->total_size = - (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; - bl32_meminfo->free_size = - (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; -} - - -/******************************************************************************* - * Populate the extents of memory available for loading BL3-3 - ******************************************************************************/ -void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) -{ - bl33_meminfo->total_base = DRAM_NS_BASE; - bl33_meminfo->total_size = DRAM_NS_SIZE; - bl33_meminfo->free_base = DRAM_NS_BASE; - bl33_meminfo->free_size = DRAM_NS_SIZE; -} diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c deleted file mode 100644 index 194d620..0000000 --- a/plat/juno/bl31_plat_setup.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch.h> -#include <arm_gic.h> -#include <assert.h> -#include <bl31.h> -#include <bl_common.h> -#include <cci.h> -#include <console.h> -#include <mmio.h> -#include <platform.h> -#include <stddef.h> -#include "juno_def.h" -#include "juno_private.h" -#include "mhu.h" - -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - ******************************************************************************/ -extern unsigned long __RO_START__; -extern unsigned long __RO_END__; -extern unsigned long __BL31_END__; - -#if USE_COHERENT_MEM -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; -#endif - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL3-1 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL31_END (unsigned long)(&__BL31_END__) - -#if USE_COHERENT_MEM -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) -#endif - -/****************************************************************************** - * Placeholder variables for copying the arguments that have been passed to - * BL3-1 from BL2. - ******************************************************************************/ -static entry_point_info_t bl32_ep_info; -static entry_point_info_t bl33_ep_info; - -/******************************************************************************* - * Return a pointer to the 'entry_point_info' structure of the next image for - * the security state specified. BL3-3 corresponds to the non-secure image type - * while BL3-2 corresponds to the secure image type. A NULL pointer is returned - * if the image does not exist. - ******************************************************************************/ -entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) -{ - entry_point_info_t *next_image_info; - - next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; - - /* None of the images on this platform can have 0x0 as the entrypoint */ - if (next_image_info->pc) - return next_image_info; - else - return NULL; -} - -/******************************************************************************* - * Perform any BL3-1 specific platform actions. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they - * are lost (potentially). This needs to be done before the MMU is initialized - * so that the memory layout can be used while creating page tables. Also, BL2 - * has flushed this information to memory, so we are guaranteed to pick up good - * data - ******************************************************************************/ -void bl31_early_platform_setup(bl31_params_t *from_bl2, - void *plat_params_from_bl2) -{ - /* Initialize the console to provide early debug support */ - console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); - - /* - * Initialise the CCI-400 driver for BL31 so that it is accessible after - * a warm boot. BL1 should have already enabled CCI coherency for this - * cluster during cold boot. - */ - plat_cci_init(); - - /* - * Check params passed from BL2 should not be NULL, - */ - assert(from_bl2 != NULL); - assert(from_bl2->h.type == PARAM_BL31); - assert(from_bl2->h.version >= VERSION_1); - /* - * In debug builds, we pass a special value in 'plat_params_from_bl2' - * to verify platform parameters from BL2 to BL3-1. - * In release builds, it's not used. - */ - assert(((unsigned long long)plat_params_from_bl2) == - JUNO_BL31_PLAT_PARAM_VAL); - - /* - * Copy BL3-2 and BL3-3 entry point information. - * They are stored in Secure RAM, in BL2's address space. - */ - bl32_ep_info = *from_bl2->bl32_ep_info; - bl33_ep_info = *from_bl2->bl33_ep_info; -} - -/******************************************************************************* - * Initialize the MHU and the GIC. - ******************************************************************************/ -void bl31_platform_setup(void) -{ - unsigned int reg_val; - - mhu_secure_init(); - - /* Initialize the gic cpu and distributor interfaces */ - plat_gic_init(); - arm_gic_setup(); - - /* Enable and initialize the System level generic timer */ - mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); - - /* Allow access to the System counter timer module */ - reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); - reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); - reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); - mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); - - reg_val = (1 << CNTNSAR_NS_SHIFT(1)); - mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); - - /* Topologies are best known to the platform. */ - plat_setup_topology(); -} - -/******************************************************************************* - * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. - ******************************************************************************/ -void bl31_plat_arch_setup(void) -{ - configure_mmu_el3(BL31_RO_BASE, - (BL31_END - BL31_RO_BASE), - BL31_RO_BASE, - BL31_RO_LIMIT -#if USE_COHERENT_MEM - , - BL31_COHERENT_RAM_BASE, - BL31_COHERENT_RAM_LIMIT -#endif - ); -} diff --git a/plat/juno/include/plat_macros.S b/plat/juno/include/plat_macros.S index 96b672a..db0c1d2 100644 --- a/plat/juno/include/plat_macros.S +++ b/plat/juno/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,85 +30,12 @@ #ifndef __PLAT_MACROS_S__ #define __PLAT_MACROS_S__ -#include <cci.h> -#include <gic_v2.h> -#include "platform_def.h" -#include "../juno_def.h" +#include <css_macros.S> -.section .rodata.gic_reg_name, "aS" -gicc_regs: - .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" -gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" -newline: - .asciz "\n" -spacer: - .asciz ":\t\t0x" - - - /* --------------------------------------------- - * The below macro prints out relevant GIC - * registers whenever an unhandled exception is - * taken in BL3-1. - * Clobbers: x0 - x10, x16, sp - * --------------------------------------------- - */ - .macro plat_print_gic_regs - mov_imm x16, GICD_BASE - mov_imm x17, GICC_BASE - /* Load the gicc reg list to x6 */ - adr x6, gicc_regs - /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ - ldr w8, [x17, #GICC_HPPIR] - ldr w9, [x17, #GICC_AHPPIR] - ldr w10, [x17, #GICC_CTLR] - /* Store to the crash buf and print to console */ - bl str_in_crash_buf_print - - /* Print the GICD_ISPENDR regs */ - add x7, x16, #GICD_ISPENDR - adr x4, gicd_pend_reg - bl asm_print_str -gicd_ispendr_loop: - sub x4, x7, x16 - cmp x4, #0x280 - b.eq exit_print_gic_regs - bl asm_print_hex - - adr x4, spacer - bl asm_print_str - - ldr x4, [x7], #8 - bl asm_print_hex - - adr x4, newline - bl asm_print_str - b gicd_ispendr_loop -exit_print_gic_regs: - .endm - -.section .rodata.cci_reg_name, "aS" -cci_iface_regs: - .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" - - /* ------------------------------------------------ - * The below macro prints out relevant interconnect - * registers whenever an unhandled exception is - * taken in BL3-1. - * Clobbers: x0 - x9, sp - * ------------------------------------------------ - */ - .macro plat_print_interconnect_regs - adr x6, cci_iface_regs - /* Store in x7 the base address of the first interface */ - mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET) - ldr w8, [x7, #SNOOP_CTRL_REG] - /* Store in x7 the base address of the second interface */ - mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET) - ldr w9, [x7, #SNOOP_CTRL_REG] - /* Store to the crash buf and print to console */ - bl str_in_crash_buf_print - .endm +/* + * Required platform porting macros + * (Provided by included headers) + */ #endif /* __PLAT_MACROS_S__ */ diff --git a/plat/juno/include/platform_def.h b/plat/juno/include/platform_def.h index 5c22069..d2122ad 100644 --- a/plat/juno/include/platform_def.h +++ b/plat/juno/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,183 +31,84 @@ #ifndef __PLATFORM_DEF_H__ #define __PLATFORM_DEF_H__ -#include <arch.h> +#include <arm_def.h> +#include <board_arm_def.h> +#include <board_css_def.h> +#include <common_def.h> +#include <css_def.h> +#include <soc_css_def.h> +#include <tzc400.h> +#include <v2m_def.h> #include "../juno_def.h" -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ - -/* Size of cacheable stacks */ -#if TRUSTED_BOARD_BOOT && (IMAGE_BL1 || IMAGE_BL2) -#define PLATFORM_STACK_SIZE 0x1000 -#else -#define PLATFORM_STACK_SIZE 0x800 -#endif - -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" - -/* Trusted Boot Firmware BL2 */ -#define BL2_IMAGE_NAME "bl2.bin" - -/* EL3 Runtime Firmware BL3-1 */ -#define BL31_IMAGE_NAME "bl31.bin" - -/* SCP Firmware BL3-0 */ -#define BL30_IMAGE_NAME "bl30.bin" - -/* Secure Payload BL3-2 (Trusted OS) */ -#define BL32_IMAGE_NAME "bl32.bin" - -/* Non-Trusted Firmware BL3-3 */ -#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ - -/* Firmware Image Package */ -#define FIP_IMAGE_NAME "fip.bin" +/* + * Most platform porting definitions provided by included headers + */ -#if TRUSTED_BOARD_BOOT -/* Certificates */ -# define BL2_CERT_NAME "bl2.crt" -# define TRUSTED_KEY_CERT_NAME "trusted_key.crt" - -# define BL30_KEY_CERT_NAME "bl30_key.crt" -# define BL31_KEY_CERT_NAME "bl31_key.crt" -# define BL32_KEY_CERT_NAME "bl32_key.crt" -# define BL33_KEY_CERT_NAME "bl33_key.crt" - -# define BL30_CERT_NAME "bl30.crt" -# define BL31_CERT_NAME "bl31.crt" -# define BL32_CERT_NAME "bl32.crt" -# define BL33_CERT_NAME "bl33.crt" -#endif /* TRUSTED_BOARD_BOOT */ +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER0_CORE_COUNT 2 +#define PLAT_ARM_CLUSTER1_CORE_COUNT 4 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CORE_COUNT 6 -#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) -#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 -#define MAX_IO_DEVICES 3 -#define MAX_IO_HANDLES 4 - -/******************************************************************************* - * BL1 specific defines. - * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base - * addresses. - ******************************************************************************/ -#define BL1_RO_BASE TZROM_BASE -#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) +/* Use the bypass address */ +#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET /* - * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using - * the current BL1 RW debug size plus a little space for growth. + * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB + * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of + * flash */ #if TRUSTED_BOARD_BOOT -#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x8000) +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 #else -#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000) -#endif -#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE) +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 +#endif /* TRUSTED_BOARD_BOOT */ + + +/* CCI related constants */ +#define PLAT_ARM_CCI_BASE 0x2c090000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 + +/* TZC related constants */ +#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) -/******************************************************************************* - * BL2 specific defines. - ******************************************************************************/ /* - * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug - * size plus a little space for growth. + * Required ARM CSS based platform porting definitions */ -#if TRUSTED_BOARD_BOOT -#define BL2_BASE (BL31_BASE - 0x1D000) -#else -#define BL2_BASE (BL31_BASE - 0xC000) -#endif -#define BL2_LIMIT BL31_BASE - -/******************************************************************************* - * Load address of BL3-0 in the Juno port - * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the - * SCP, it is discarded and BL3-1 is loaded over the top. - ******************************************************************************/ -#define BL30_BASE BL31_BASE - -/******************************************************************************* - * BL3-1 specific defines. - ******************************************************************************/ + +/* GIC related constants (no GICR in GIC-400) */ +#define PLAT_CSS_GICD_BASE 0x2c010000 +#define PLAT_CSS_GICR_BASE 0x0 +#define PLAT_CSS_GICC_BASE 0x2c02f000 +#define PLAT_CSS_GICH_BASE 0x2c04f000 +#define PLAT_CSS_GICV_BASE 0x2c06f000 + +#define PLAT_CSS_IRQ_SEC_LIST CSS_IRQ_MHU, \ + CSS_IRQ_GPU_SMMU_0, \ + CSS_IRQ_GPU_SMMU_1, \ + CSS_IRQ_ETR_SMMU, \ + CSS_IRQ_TZC, \ + CSS_IRQ_TZ_WDOG + /* - * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the - * current BL3-1 debug size plus a little space for growth. + * Required ARM CSS SoC based platform porting definitions */ -#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000) -#define BL31_PROGBITS_LIMIT BL1_RW_BASE -#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) - -/******************************************************************************* - * BL3-2 specific defines. - ******************************************************************************/ -#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID) -# define TSP_SEC_MEM_BASE TZRAM_BASE -# define TSP_SEC_MEM_SIZE TZRAM_SIZE -# define BL32_BASE TZRAM_BASE -# define BL32_LIMIT BL31_BASE -# define BL32_PROGBITS_LIMIT BL2_BASE -#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID) -# define TSP_SEC_MEM_BASE DRAM_SEC_BASE -# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE) -# define BL32_BASE DRAM_SEC_BASE -# define BL32_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE - \ - DRAM_SCP_SIZE) -#else -# error "Unsupported PLAT_TSP_LOCATION_ID value" -#endif - -/******************************************************************************* - * Load address of BL3-3 in the Juno port - ******************************************************************************/ -#define NS_IMAGE_OFFSET 0xE0000000 - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define ADDR_SPACE_SIZE (1ull << 32) - -#if IMAGE_BL1 || IMAGE_BL31 -# define MAX_XLAT_TABLES 2 -#endif - -#if IMAGE_BL2 || IMAGE_BL32 -# define MAX_XLAT_TABLES 3 -#endif - -#define MAX_MMAP_REGIONS (JUNO_MMAP_ENTRIES + JUNO_BL_REGIONS) - -/******************************************************************************* - * ID of the secure physical generic timer interrupt used by the TSP - ******************************************************************************/ -#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#if !USE_COHERENT_MEM -/******************************************************************************* - * Size of the per-cpu data in bytes that should be reserved in the generic - * per-cpu data structure for the Juno port. - ******************************************************************************/ -#define PLAT_PCPU_DATA_SIZE 2 -#endif + +/* CSS SoC NIC-400 Global Programmers View (GPV) */ +#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/juno/include/platform_oid.h b/plat/juno/include/platform_oid.h index 38aca12..1e44cf7 100644 --- a/plat/juno/include/platform_oid.h +++ b/plat/juno/include/platform_oid.h @@ -27,43 +27,9 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ - -#ifndef PLATFORM_OID_H_ -#define PLATFORM_OID_H_ +#include "../../../../../include/plat/arm/board/common/board_arm_oid.h" /* - * This is the list of the different extensions containing relevant information - * to establish the chain of trust. - * - * The OIDs shown here are just an example. Real OIDs should be obtained from - * the ITU-T. + * Required platform OIDs + * (Provided by included header) */ - -/* Non-volatile counter extensions */ -#define TZ_FW_NVCOUNTER_OID "1.2.3.1" -#define NTZ_FW_NVCOUNTER_OID "1.2.3.2" - -/* BL2 extensions */ -#define BL2_HASH_OID "1.2.3.3" - -/* Trusted Key extensions */ -#define TZ_WORLD_PK_OID "1.2.3.4" -#define NTZ_WORLD_PK_OID "1.2.3.5" - -/* BL3-1 extensions */ -#define BL31_CONTENT_CERT_PK_OID "1.2.3.6" -#define BL31_HASH_OID "1.2.3.7" - -/* BL3-0 extensions */ -#define BL30_CONTENT_CERT_PK_OID "1.2.3.8" -#define BL30_HASH_OID "1.2.3.9" - -/* BL3-2 extensions */ -#define BL32_CONTENT_CERT_PK_OID "1.2.3.10" -#define BL32_HASH_OID "1.2.3.11" - -/* BL3-3 extensions */ -#define BL33_CONTENT_CERT_PK_OID "1.2.3.12" -#define BL33_HASH_OID "1.2.3.13" - -#endif /* PLATFORM_OID_H_ */ diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h index 2134ee4..8fe3835 100644 --- a/plat/juno/juno_def.h +++ b/plat/juno/juno_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,263 +31,45 @@ #ifndef __JUNO_DEF_H__ #define __JUNO_DEF_H__ -/* Special value used to verify platform parameters from BL2 to BL3-1 */ -#define JUNO_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL /******************************************************************************* * Juno memory map related constants ******************************************************************************/ -#define FLASH_BASE 0x08000000 -#define FLASH_SIZE 0x04000000 - -/* Bypass offset from start of NOR flash */ -#define BL1_ROM_BYPASS_OFFSET 0x03EC0000 - -#ifndef TZROM_BASE -/* Use the bypass address */ -#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET -#endif -/* Actual ROM size on Juno is 64 KB, but TBB requires at least 80 KB in debug - * mode. We can test TBB on Juno bypassing the ROM and using 128 KB of flash */ -#if TRUSTED_BOARD_BOOT -#define TZROM_SIZE 0x00020000 -#else -#define TZROM_SIZE 0x00010000 -#endif - -#define TZRAM_BASE 0x04001000 -#define TZRAM_SIZE 0x0003F000 - -#define PLAT_TRUSTED_SRAM_ID 0 -#define PLAT_DRAM_ID 1 - -#define MHU_SECURE_BASE 0x04000000 -#define MHU_SECURE_SIZE 0x00001000 - -#define MHU_PAYLOAD_CACHED 0 - -#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE -#define TRUSTED_MAILBOX_SHIFT 4 - -#define EMMC_BASE 0x0c000000 -#define EMMC_SIZE 0x04000000 - -#define PSRAM_BASE 0x14000000 -#define PSRAM_SIZE 0x02000000 - -#define IOFPGA_BASE 0x1c000000 -#define IOFPGA_SIZE 0x03000000 - -#define NSROM_BASE 0x1f000000 -#define NSROM_SIZE 0x00001000 - -/* Following covers Columbus Peripherals excluding NSROM and NSRAM */ -#define DEVICE0_BASE 0x20000000 -#define DEVICE0_SIZE 0x0e000000 -#define MHU_BASE 0x2b1f0000 - -#define NSRAM_BASE 0x2e000000 -#define NSRAM_SIZE 0x00008000 - -/* Following covers Juno Peripherals and PCIe expansion area */ -#define DEVICE1_BASE 0x40000000 -#define DEVICE1_SIZE 0x40000000 -#define PCIE_CONTROL_BASE 0x7ff20000 - -#define DRAM_BASE 0x80000000 -#define DRAM_SIZE 0x80000000 - -/* - * DRAM at 0x8000_0000 is divided in two regions: - * - Secure DRAM (default is the top 16MB except for the last 2MB, which are - * used by the SCP for DDR retraining) - * - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE) - */ - -#define DRAM_SCP_SIZE 0x00200000 -#define DRAM_SCP_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SCP_SIZE) - -#define DRAM_SEC_SIZE 0x00E00000 -#define DRAM_SEC_BASE (DRAM_SCP_BASE - DRAM_SEC_SIZE) - -#define DRAM_NS_BASE DRAM_BASE -#define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SCP_SIZE - DRAM_SEC_SIZE) - -/* Second region of DRAM */ -#define DRAM2_BASE 0x880000000 -#define DRAM2_SIZE 0x180000000 - -/* Memory mapped Generic timer interfaces */ -#define SYS_CNTCTL_BASE 0x2a430000 -#define SYS_CNTREAD_BASE 0x2a800000 -#define SYS_TIMCTL_BASE 0x2a810000 - -/* - * Base memory address of the V2M-Juno motherboard APB system registers in the - * IOFPGA - */ -#define VE_SYSREGS_BASE 0x1c010000 -/* APB system registers in address offset order from the base memory address */ -#define V2M_SYS_ID 0x0 -#define V2M_SYS_LED 0x8 - -/* V2M SYS_ID register bits */ -#define SYS_ID_REV_SHIFT 28 -#define SYS_ID_REV_MASK 0xf /* Board revisions */ -#define REV_JUNO_R0 0x1 /* Rev B */ -#define REV_JUNO_R1 0x2 /* Rev C */ - -/* - * V2M sysled bit definitions. The values written to this - * register are defined in arch.h & runtime_svc.h. Only - * used by the primary cpu to diagnose any cold boot issues. - * - * SYS_LED[0] - Security state (S=0/NS=1) - * SYS_LED[2:1] - Exception Level (EL3-EL0) - * SYS_LED[7:3] - Exception Class (Sync/Async & origin) - * - */ -#define SYS_LED_SS_SHIFT 0x0 -#define SYS_LED_EL_SHIFT 0x1 -#define SYS_LED_EC_SHIFT 0x3 +#define REV_JUNO_R0 0x1 /* Rev B */ +#define REV_JUNO_R1 0x2 /* Rev C */ -/* - * The number of regions like RO(code), coherent and data required by - * different BL stages which need to be mapped in the MMU. - */ -#if USE_COHERENT_MEM -#define JUNO_BL_REGIONS 3 -#else -#define JUNO_BL_REGIONS 2 -#endif - -/* - * The JUNO_MAX_MMAP_REGIONS depend on the number of entries in juno_mmap[] - * defined for each BL stage in juno_common.c. - */ -#if IMAGE_BL1 -#define JUNO_MMAP_ENTRIES 6 -#endif -#if IMAGE_BL2 -#define JUNO_MMAP_ENTRIES 8 -#endif -#if IMAGE_BL31 -#define JUNO_MMAP_ENTRIES 5 -#endif -#if IMAGE_BL32 -#define JUNO_MMAP_ENTRIES 4 -#endif - -/******************************************************************************* - * GIC-400 & interrupt handling related constants - ******************************************************************************/ -#define GICD_BASE 0x2c010000 -#define GICC_BASE 0x2c02f000 -#define GICH_BASE 0x2c04f000 -#define GICV_BASE 0x2c06f000 - -#define IRQ_MHU 69 -#define IRQ_GPU_SMMU_0 71 -#define IRQ_GPU_SMMU_1 73 -#define IRQ_ETR_SMMU 75 -#define IRQ_TZC400 80 -#define IRQ_TZ_WDOG 86 - -#define IRQ_SEC_PHY_TIMER 29 -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 - -/******************************************************************************* - * PL011 related constants - ******************************************************************************/ -/* FPGA UART0 */ -#define PL011_UART0_BASE 0x1c090000 -/* FPGA UART1 */ -#define PL011_UART1_BASE 0x1c0a0000 -/* SoC UART0 */ -#define PL011_UART2_BASE 0x7ff80000 -/* SoC UART1 */ -#define PL011_UART3_BASE 0x7ff70000 - -#define PL011_BAUDRATE 115200 - -#define PL011_UART0_CLK_IN_HZ 24000000 -#define PL011_UART1_CLK_IN_HZ 24000000 -#define PL011_UART2_CLK_IN_HZ 7273800 -#define PL011_UART3_CLK_IN_HZ 7273800 - -/******************************************************************************* - * NIC-400 related constants - ******************************************************************************/ - -/* CSS NIC-400 Global Programmers View (GPV) */ -#define CSS_NIC400_BASE 0x2a000000 +/* Bypass offset from start of NOR flash */ +#define BL1_ROM_BYPASS_OFFSET 0x03EC0000 -/* The slave_bootsecure controls access to GPU, DMC and CS. */ -#define CSS_NIC400_SLAVE_BOOTSECURE 8 +#define EMMC_BASE 0x0c000000 +#define EMMC_SIZE 0x04000000 -/* SoC NIC-400 Global Programmers View (GPV) */ -#define SOC_NIC400_BASE 0x7fd00000 +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x02000000 -#define SOC_NIC400_USB_EHCI 0 -#define SOC_NIC400_TLX_MASTER 1 -#define SOC_NIC400_USB_OHCI 2 -#define SOC_NIC400_PL354_SMC 3 -/* - * The apb4_bridge controls access to: - * - the PCIe configuration registers - * - the MMU units for USB, HDLCD and DMA - */ -#define SOC_NIC400_APB4_BRIDGE 4 -/* - * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. - */ -#define SOC_NIC400_BOOTSEC_BRIDGE 5 -#define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) /******************************************************************************* * TZC-400 related constants ******************************************************************************/ -#define TZC400_BASE 0x2a4a0000 - -#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ -#define TZC400_NSAID_PCIE 1 -#define TZC400_NSAID_HDLCD0 2 -#define TZC400_NSAID_HDLCD1 3 -#define TZC400_NSAID_USB 4 -#define TZC400_NSAID_DMA330 5 -#define TZC400_NSAID_THINLINKS 6 -#define TZC400_NSAID_AP 9 -#define TZC400_NSAID_GPU 10 -#define TZC400_NSAID_SCP 11 -#define TZC400_NSAID_CORESIGHT 12 - -/******************************************************************************* - * CCI-400 related constants - ******************************************************************************/ -#define CCI400_BASE 0x2c090000 -#define CCI400_CLUSTER0_SL_IFACE_IX 4 -#define CCI400_CLUSTER1_SL_IFACE_IX 3 - -/******************************************************************************* - * SCP <=> AP boot configuration - ******************************************************************************/ -#define SCP_BOOT_CFG_ADDR 0x04000080 -#define PRIMARY_CPU_SHIFT 8 -#define PRIMARY_CPU_MASK 0xf +#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ +#define TZC400_NSAID_PCIE 1 +#define TZC400_NSAID_HDLCD0 2 +#define TZC400_NSAID_HDLCD1 3 +#define TZC400_NSAID_USB 4 +#define TZC400_NSAID_DMA330 5 +#define TZC400_NSAID_THINLINKS 6 +#define TZC400_NSAID_AP 9 +#define TZC400_NSAID_GPU 10 +#define TZC400_NSAID_SCP 11 +#define TZC400_NSAID_CORESIGHT 12 /******************************************************************************* * MMU-401 related constants ******************************************************************************/ -#define MMU401_SSD_OFFSET 0x4000 -#define MMU401_DMA330_BASE 0x7fb00000 +#define MMU401_SSD_OFFSET 0x4000 +#define MMU401_DMA330_BASE 0x7fb00000 + #endif /* __JUNO_DEF_H__ */ diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h deleted file mode 100644 index afb1bfc..0000000 --- a/plat/juno/juno_private.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __JUNO_PRIVATE_H__ -#define __JUNO_PRIVATE_H__ - -#include <bakery_lock.h> -#include <bl_common.h> -#include <cpu_data.h> -#include <platform_def.h> -#include <stdint.h> - -/******************************************************************************* - * Forward declarations - ******************************************************************************/ -struct plat_pm_ops; -struct meminfo; -struct bl31_params; -struct image_info; -struct entry_point_info; - -/******************************************************************************* - * This structure represents the superset of information that is passed to - * BL3-1 e.g. while passing control to it from BL2 which is bl31_params - * and other platform specific params - ******************************************************************************/ -typedef struct bl2_to_bl31_params_mem { - struct bl31_params bl31_params; - struct image_info bl31_image_info; - struct image_info bl32_image_info; - struct image_info bl33_image_info; - struct entry_point_info bl33_ep_info; - struct entry_point_info bl32_ep_info; - struct entry_point_info bl31_ep_info; -} bl2_to_bl31_params_mem_t; - -#if IMAGE_BL31 -#if USE_COHERENT_MEM -/* - * These are wrapper macros to the Coherent Memory Bakery Lock API. - */ -#define juno_lock_init(_lock_arg) bakery_lock_init(_lock_arg) -#define juno_lock_get(_lock_arg) bakery_lock_get(_lock_arg) -#define juno_lock_release(_lock_arg) bakery_lock_release(_lock_arg) - -#else - -/******************************************************************************* - * Constants that specify how many bakeries this platform implements and bakery - * ids. - ******************************************************************************/ -#define JUNO_MAX_BAKERIES 1 -#define JUNO_MHU_BAKERY_ID 0 - -/******************************************************************************* - * Definition of structure which holds platform specific per-cpu data. Currently - * it holds only the bakery lock information for each cpu. Constants to specify - * how many bakeries this platform implements and bakery ids are specified in - * juno_def.h - ******************************************************************************/ -typedef struct juno_cpu_data { - bakery_info_t pcpu_bakery_info[JUNO_MAX_BAKERIES]; -} juno_cpu_data_t; - -/* Macro to define the offset of bakery_info_t in juno_cpu_data_t */ -#define JUNO_CPU_DATA_LOCK_OFFSET __builtin_offsetof\ - (juno_cpu_data_t, pcpu_bakery_info) - -/******************************************************************************* - * Helper macros for bakery lock api when using the above juno_cpu_data_t for - * bakery lock data structures. It assumes that the bakery_info is at the - * beginning of the platform specific per-cpu data. - ******************************************************************************/ -#define juno_lock_init(_lock_arg) /* No init required */ -#define juno_lock_get(_lock_arg) bakery_lock_get(_lock_arg, \ - CPU_DATA_PLAT_PCPU_OFFSET + \ - JUNO_CPU_DATA_LOCK_OFFSET) -#define juno_lock_release(_lock_arg) bakery_lock_release(_lock_arg, \ - CPU_DATA_PLAT_PCPU_OFFSET + \ - JUNO_CPU_DATA_LOCK_OFFSET) - -/* - * Ensure that the size of the Juno specific per-cpu data structure and the size - * of the memory allocated in generic per-cpu data for the platform are the same. - */ -CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(juno_cpu_data_t), \ - juno_pcpu_data_size_mismatch); -#endif /* __USE_COHERENT_MEM__ */ -#else -/* - * Dummy wrapper macros for all other BL stages other than BL3-1 - */ -#define juno_lock_init(_lock_arg) -#define juno_lock_get(_lock_arg) -#define juno_lock_release(_lock_arg) - -#endif /* __IMAGE_BL31__ */ - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void bl1_plat_arch_setup(void); -void bl2_plat_arch_setup(void); -void bl31_plat_arch_setup(void); -int platform_setup_pm(const struct plat_pm_ops **plat_ops); -unsigned int platform_get_core_pos(unsigned long mpidr); -void configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit -#if USE_COHERENT_MEM - , unsigned long coh_start, - unsigned long coh_limit -#endif - ); -void configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit -#if USE_COHERENT_MEM - , unsigned long coh_start, - unsigned long coh_limit -#endif - ); -void plat_report_exception(unsigned long type); -unsigned long plat_get_ns_image_entrypoint(void); -unsigned long platform_get_stack(unsigned long mpidr); -uint64_t plat_get_syscnt_freq(void); -void plat_gic_init(void); -void plat_cci_init(void); - -/* Declarations for plat_topology.c */ -int plat_setup_topology(void); -unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr); -unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr); - -/* Declarations for plat_io_storage.c */ -void io_setup(void); -int plat_get_image_source(const char *image_name, - uintptr_t *dev_handle, - uintptr_t *image_spec); - -/* Declarations for security.c */ -void plat_security_setup(void); - -/* - * Before calling this function BL2 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL2 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - */ -void bl1_plat_set_bl2_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL3-1 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL3-1 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl31_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL3-2 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL3-2 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl32_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL3-3 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL3-3 and set SPSR and security state. - * On Juno we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl33_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* Gets the memory layout for BL3-2 */ -void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); - -/* Gets the memory layout for BL3-3 */ -void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); - -#endif /* __JUNO_PRIVATE_H__ */ diff --git a/plat/juno/juno_trusted_boot.c b/plat/juno/juno_trusted_boot.c deleted file mode 100644 index e63d4b2..0000000 --- a/plat/juno/juno_trusted_boot.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <assert.h> -#include <debug.h> -#include "juno_def.h" -#include "juno_private.h" - -/* - * Check the validity of the key - * - * 0 = success, Otherwise = error - */ -int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len) -{ - /* TODO: check against the ROT key stored in the platform */ - return 0; -} diff --git a/plat/juno/mhu.c b/plat/juno/mhu.c deleted file mode 100644 index c1c414c..0000000 --- a/plat/juno/mhu.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch_helpers.h> -#include <bakery_lock.h> -#include <mmio.h> -#include "juno_def.h" -#include "juno_private.h" -#include "mhu.h" - -/* SCP MHU secure channel registers */ -#define SCP_INTR_S_STAT 0x200 -#define SCP_INTR_S_SET 0x208 -#define SCP_INTR_S_CLEAR 0x210 - -/* CPU MHU secure channel registers */ -#define CPU_INTR_S_STAT 0x300 -#define CPU_INTR_S_SET 0x308 -#define CPU_INTR_S_CLEAR 0x310 - -#if IMAGE_BL31 -#if USE_COHERENT_MEM -static bakery_lock_t mhu_secure_lock __attribute__ ((section("tzfw_coherent_mem"))); -#define LOCK_ARG &mhu_secure_lock -#else -#define LOCK_ARG JUNO_MHU_BAKERY_ID -#endif /*__USE_COHERENT_MEM__ */ -#else -#define LOCK_ARG /* Locks required only for BL3-1 images */ -#endif /* __IMAGE_BL31__ */ - -void mhu_secure_message_start(void) -{ - juno_lock_get(LOCK_ARG); - - /* Make sure any previous command has finished */ - while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0) - ; -} - -void mhu_secure_message_send(uint32_t command) -{ - /* Send command to SCP and wait for it to pick it up */ - mmio_write_32(MHU_BASE + CPU_INTR_S_SET, command); - while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0) - ; -} - -uint32_t mhu_secure_message_wait(void) -{ - /* Wait for response from SCP */ - uint32_t response; - while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT))) - ; - - return response; -} - -void mhu_secure_message_end(void) -{ - /* Clear any response we got by writing all ones to the CLEAR register */ - mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 0xffffffffu); - - juno_lock_release(LOCK_ARG); -} - -void mhu_secure_init(void) -{ - juno_lock_init(LOCK_ARG); - - /* - * Clear the CPU's INTR register to make sure we don't see a stale - * or garbage value and think it's a message we've already sent. - */ - mmio_write_32(MHU_BASE + CPU_INTR_S_CLEAR, 0xffffffffu); -} diff --git a/plat/juno/mhu.h b/plat/juno/mhu.h deleted file mode 100644 index 5149c82..0000000 --- a/plat/juno/mhu.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MHU_H__ -#define __MHU_H__ - -#include <stdint.h> - -extern void mhu_secure_message_start(void); -extern void mhu_secure_message_send(uint32_t command); -extern uint32_t mhu_secure_message_wait(void); -extern void mhu_secure_message_end(void); - -extern void mhu_secure_init(void); - -#endif /* __MHU_H__ */ diff --git a/plat/juno/plat-tsp.ld.S b/plat/juno/plat-tsp.ld.S deleted file mode 100644 index 16d6c17..0000000 --- a/plat/juno/plat-tsp.ld.S +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - - ASSERT(__BL32_END__ <= BL2_BASE, "BL3-2 image overlaps BL2 image.") diff --git a/plat/juno/plat_io_storage.c b/plat/juno/plat_io_storage.c deleted file mode 100644 index b31865e..0000000 --- a/plat/juno/plat_io_storage.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <assert.h> -#include <debug.h> -#include <io_driver.h> -#include <io_fip.h> -#include <io_memmap.h> -#include <io_storage.h> -#include <platform_def.h> -#include <semihosting.h> /* For FOPEN_MODE_... */ -#include <string.h> - -/* IO devices */ -static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_spec; -static uintptr_t fip_dev_handle; -static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_spec; -static uintptr_t memmap_init_params; -static uintptr_t memmap_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = FLASH_BASE, - .length = FLASH_SIZE -}; - -static const io_file_spec_t bl2_file_spec = { - .path = BL2_IMAGE_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl30_file_spec = { - .path = BL30_IMAGE_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl31_file_spec = { - .path = BL31_IMAGE_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl32_file_spec = { - .path = BL32_IMAGE_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl33_file_spec = { - .path = BL33_IMAGE_NAME, - .mode = FOPEN_MODE_RB -}; - -#if TRUSTED_BOARD_BOOT -static const io_file_spec_t bl2_cert_file_spec = { - .path = BL2_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t trusted_key_cert_file_spec = { - .path = TRUSTED_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl30_key_cert_file_spec = { - .path = BL30_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl31_key_cert_file_spec = { - .path = BL31_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl32_key_cert_file_spec = { - .path = BL32_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl33_key_cert_file_spec = { - .path = BL33_KEY_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl30_cert_file_spec = { - .path = BL30_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl31_cert_file_spec = { - .path = BL31_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl32_cert_file_spec = { - .path = BL32_CERT_NAME, - .mode = FOPEN_MODE_RB -}; - -static const io_file_spec_t bl33_cert_file_spec = { - .path = BL33_CERT_NAME, - .mode = FOPEN_MODE_RB -}; -#endif /* TRUSTED_BOARD_BOOT */ - -static int open_fip(const uintptr_t spec); -static int open_memmap(const uintptr_t spec); - -struct plat_io_policy { - const char *image_name; - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -static const struct plat_io_policy policies[] = { - { - FIP_IMAGE_NAME, - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, { - BL2_IMAGE_NAME, - &fip_dev_handle, - (uintptr_t)&bl2_file_spec, - open_fip - }, { - BL30_IMAGE_NAME, - &fip_dev_handle, - (uintptr_t)&bl30_file_spec, - open_fip - }, { - BL31_IMAGE_NAME, - &fip_dev_handle, - (uintptr_t)&bl31_file_spec, - open_fip - }, { - BL32_IMAGE_NAME, - &fip_dev_handle, - (uintptr_t)&bl32_file_spec, - open_fip - }, { - BL33_IMAGE_NAME, - &fip_dev_handle, - (uintptr_t)&bl33_file_spec, - open_fip - }, { -#if TRUSTED_BOARD_BOOT - BL2_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl2_cert_file_spec, - open_fip - }, { - TRUSTED_KEY_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_file_spec, - open_fip - }, { - BL30_KEY_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl30_key_cert_file_spec, - open_fip - }, { - BL31_KEY_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl31_key_cert_file_spec, - open_fip - }, { - BL32_KEY_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl32_key_cert_file_spec, - open_fip - }, { - BL33_KEY_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl33_key_cert_file_spec, - open_fip - }, { - BL30_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl30_cert_file_spec, - open_fip - }, { - BL31_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl31_cert_file_spec, - open_fip - }, { - BL32_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl32_cert_file_spec, - open_fip - }, { - BL33_CERT_NAME, - &fip_dev_handle, - (uintptr_t)&bl33_cert_file_spec, - open_fip - }, { -#endif /* TRUSTED_BOARD_BOOT */ - 0, 0, 0 - } -}; - - -static int open_fip(const uintptr_t spec) -{ - int result = IO_FAIL; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME); - if (result == IO_SUCCESS) { - INFO("Using FIP\n"); - /*TODO: Check image defined in spec is present in FIP. */ - } - return result; -} - - -static int open_memmap(const uintptr_t spec) -{ - int result = IO_FAIL; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, memmap_init_params); - if (result == IO_SUCCESS) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == IO_SUCCESS) { - /* INFO("Using Memmap IO\n"); */ - io_close(local_image_handle); - } - } - return result; -} - -void io_setup(void) -{ - int io_result = IO_FAIL; - - /* Register the IO devices on this platform */ - io_result = register_io_dev_fip(&fip_dev_con); - assert(io_result == IO_SUCCESS); - - io_result = register_io_dev_memmap(&memmap_dev_con); - assert(io_result == IO_SUCCESS); - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle); - assert(io_result == IO_SUCCESS); - - io_result = io_dev_open(memmap_dev_con, memmap_dev_spec, - &memmap_dev_handle); - assert(io_result == IO_SUCCESS); - - /* Ignore improbable errors in release builds */ - (void)io_result; -} - - -/* Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy */ -int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result = IO_FAIL; - const struct plat_io_policy *policy; - - if ((image_name != NULL) && (dev_handle != NULL) && - (image_spec != NULL)) { - policy = policies; - while (policy->image_name != NULL) { - if (strcmp(policy->image_name, image_name) == 0) { - result = policy->check(policy->image_spec); - if (result == IO_SUCCESS) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - break; - } - } - policy++; - } - } else { - result = IO_FAIL; - } - return result; -} diff --git a/plat/juno/plat_pm.c b/plat/juno/plat_pm.c deleted file mode 100644 index 953e5f7..0000000 --- a/plat/juno/plat_pm.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <assert.h> -#include <arch_helpers.h> -#include <arm_gic.h> -#include <cci.h> -#include <debug.h> -#include <errno.h> -#include <platform.h> -#include <platform_def.h> -#include <psci.h> -#include "juno_def.h" -#include "juno_private.h" -#include "scpi.h" - -/******************************************************************************* - * Private Juno function to program the mailbox for a cpu before it is released - * from reset. - ******************************************************************************/ -static void juno_program_mailbox(uint64_t mpidr, uint64_t address) -{ - uint64_t linear_id; - uint64_t mbox; - - linear_id = platform_get_core_pos(mpidr); - mbox = TRUSTED_MAILBOXES_BASE + (linear_id << TRUSTED_MAILBOX_SHIFT); - *((uint64_t *) mbox) = address; - flush_dcache_range(mbox, sizeof(mbox)); -} - -/******************************************************************************* - * Private Juno function which is used to determine if any platform actions - * should be performed for the specified affinity instance given its - * state. Nothing needs to be done if the 'state' is not off or if this is not - * the highest affinity level which will enter the 'state'. - ******************************************************************************/ -static int32_t juno_do_plat_actions(uint32_t afflvl, uint32_t state) -{ - uint32_t max_phys_off_afflvl; - - assert(afflvl <= MPIDR_AFFLVL1); - - if (state != PSCI_STATE_OFF) - return -EAGAIN; - - /* - * Find the highest affinity level which will be suspended and postpone - * all the platform specific actions until that level is hit. - */ - max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); - assert(max_phys_off_afflvl != PSCI_INVALID_DATA); - assert(psci_get_suspend_afflvl() >= max_phys_off_afflvl); - if (afflvl != max_phys_off_afflvl) - return -EAGAIN; - - return 0; -} - -/******************************************************************************* - * Juno handler called to check the validity of the power state parameter. - ******************************************************************************/ -int32_t juno_validate_power_state(unsigned int power_state) -{ - /* Sanity check the requested state */ - if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { - /* - * It's possible to enter standby only on affinity level 0 i.e. - * a cpu on the Juno. Ignore any other affinity level. - */ - if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) - return PSCI_E_INVALID_PARAMS; - } - - /* - * We expect the 'state id' to be zero. - */ - if (psci_get_pstate_id(power_state)) - return PSCI_E_INVALID_PARAMS; - - return PSCI_E_SUCCESS; -} - - -/******************************************************************************* - * Juno handler called when an affinity instance is about to be turned on. The - * level and mpidr determine the affinity instance. - ******************************************************************************/ -int32_t juno_affinst_on(uint64_t mpidr, - uint64_t sec_entrypoint, - uint32_t afflvl, - uint32_t state) -{ - /* - * SCP takes care of powering up higher affinity levels so we - * only need to care about level 0 - */ - if (afflvl != MPIDR_AFFLVL0) - return PSCI_E_SUCCESS; - - /* - * Setup mailbox with address for CPU entrypoint when it next powers up - */ - juno_program_mailbox(mpidr, sec_entrypoint); - - scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on, - scpi_power_on); - - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * Juno handler called when an affinity instance has just been powered on after - * being turned off earlier. The level and mpidr determine the affinity - * instance. The 'state' arg. allows the platform to decide whether the cluster - * was turned off prior to wakeup and do what's necessary to setup it up - * correctly. - ******************************************************************************/ -void juno_affinst_on_finish(uint32_t afflvl, uint32_t state) -{ - unsigned long mpidr; - - /* Determine if any platform actions need to be executed. */ - if (juno_do_plat_actions(afflvl, state) == -EAGAIN) - return; - - /* Get the mpidr for this cpu */ - mpidr = read_mpidr_el1(); - - /* - * Perform the common cluster specific operations i.e enable coherency - * if this cluster was off. - */ - if (afflvl != MPIDR_AFFLVL0) - cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); - - /* Enable the gic cpu interface */ - arm_gic_cpuif_setup(); - - /* Juno todo: Is this setup only needed after a cold boot? */ - arm_gic_pcpu_distif_setup(); - - /* Clear the mailbox for this cpu. */ - juno_program_mailbox(mpidr, 0); -} - -/******************************************************************************* - * Common function called while turning a cpu off or suspending it. It is called - * from juno_off() or juno_suspend() when these functions in turn are called for - * the highest affinity level which will be powered down. It performs the - * actions common to the OFF and SUSPEND calls. - ******************************************************************************/ -static void juno_power_down_common(uint32_t afflvl) -{ - uint32_t cluster_state = scpi_power_on; - - /* Prevent interrupts from spuriously waking up this cpu */ - arm_gic_cpuif_deactivate(); - - /* Cluster is to be turned off, so disable coherency */ - if (afflvl > MPIDR_AFFLVL0) { - cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); - cluster_state = scpi_power_off; - } - - /* - * Ask the SCP to power down the appropriate components depending upon - * their state. - */ - scpi_set_css_power_state(read_mpidr_el1(), - scpi_power_off, - cluster_state, - scpi_power_on); -} - -/******************************************************************************* - * Handler called when an affinity instance is about to be turned off. The - * level and mpidr determine the affinity instance. The 'state' arg. allows the - * platform to decide whether the cluster is being turned off and take - * appropriate actions. - * - * CAUTION: There is no guarantee that caches will remain turned on across calls - * to this function as each affinity level is dealt with. So do not write & read - * global variables across calls. It will be wise to do flush a write to the - * global to prevent unpredictable results. - ******************************************************************************/ -static void juno_affinst_off(uint32_t afflvl, uint32_t state) -{ - /* Determine if any platform actions need to be executed */ - if (juno_do_plat_actions(afflvl, state) == -EAGAIN) - return; - - juno_power_down_common(afflvl); -} - -/******************************************************************************* - * Handler called when an affinity instance is about to be suspended. The - * level and mpidr determine the affinity instance. The 'state' arg. allows the - * platform to decide whether the cluster is being turned off and take apt - * actions. The 'sec_entrypoint' determines the address in BL3-1 from where - * execution should resume. - * - * CAUTION: There is no guarantee that caches will remain turned on across calls - * to this function as each affinity level is dealt with. So do not write & read - * global variables across calls. It will be wise to do flush a write to the - * global to prevent unpredictable results. - ******************************************************************************/ -static void juno_affinst_suspend(uint64_t sec_entrypoint, - uint32_t afflvl, - uint32_t state) -{ - /* Determine if any platform actions need to be executed */ - if (juno_do_plat_actions(afflvl, state) == -EAGAIN) - return; - - /* - * Setup mailbox with address for CPU entrypoint when it next powers up. - */ - juno_program_mailbox(read_mpidr_el1(), sec_entrypoint); - - juno_power_down_common(afflvl); -} - -/******************************************************************************* - * Juno handler called when an affinity instance has just been powered on after - * having been suspended earlier. The level and mpidr determine the affinity - * instance. - * TODO: At the moment we reuse the on finisher and reinitialize the secure - * context. Need to implement a separate suspend finisher. - ******************************************************************************/ -static void juno_affinst_suspend_finish(uint32_t afflvl, - uint32_t state) -{ - juno_affinst_on_finish(afflvl, state); -} - -/******************************************************************************* - * Juno handlers to shutdown/reboot the system - ******************************************************************************/ -static void __dead2 juno_system_off(void) -{ - uint32_t response; - - /* Send the power down request to the SCP */ - response = scpi_sys_power_state(scpi_system_shutdown); - - if (response != SCP_OK) { - ERROR("Juno System Off: SCP error %u.\n", response); - panic(); - } - wfi(); - ERROR("Juno System Off: operation not handled.\n"); - panic(); -} - -static void __dead2 juno_system_reset(void) -{ - uint32_t response; - - /* Send the system reset request to the SCP */ - response = scpi_sys_power_state(scpi_system_reboot); - - if (response != SCP_OK) { - ERROR("Juno System Reset: SCP error %u.\n", response); - panic(); - } - wfi(); - ERROR("Juno System Reset: operation not handled.\n"); - panic(); -} - -/******************************************************************************* - * Handler called when an affinity instance is about to enter standby. - ******************************************************************************/ -void juno_affinst_standby(unsigned int power_state) -{ - unsigned int scr; - - scr = read_scr_el3(); - /* Enable PhysicalIRQ bit for NS world to wake the CPU */ - write_scr_el3(scr | SCR_IRQ_BIT); - isb(); - dsb(); - wfi(); - - /* - * Restore SCR to the original value, synchronisation of scr_el3 is - * done by eret while el3_exit to save some execution cycles. - */ - write_scr_el3(scr); -} - -/******************************************************************************* - * Export the platform handlers to enable psci to invoke them - ******************************************************************************/ -static const plat_pm_ops_t juno_ops = { - .affinst_on = juno_affinst_on, - .affinst_on_finish = juno_affinst_on_finish, - .affinst_off = juno_affinst_off, - .affinst_standby = juno_affinst_standby, - .affinst_suspend = juno_affinst_suspend, - .affinst_suspend_finish = juno_affinst_suspend_finish, - .system_off = juno_system_off, - .system_reset = juno_system_reset, - .validate_power_state = juno_validate_power_state -}; - -/******************************************************************************* - * Export the platform specific power ops. - ******************************************************************************/ -int32_t platform_setup_pm(const plat_pm_ops_t **plat_ops) -{ - *plat_ops = &juno_ops; - return 0; -} diff --git a/plat/juno/plat_security.c b/plat/juno/plat_security.c index 254357d..1de38c3 100644 --- a/plat/juno/plat_security.c +++ b/plat/juno/plat_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -28,71 +28,11 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include <debug.h> #include <mmio.h> -#include <tzc400.h> +#include <plat_arm.h> +#include <soc_css.h> #include "juno_def.h" -/******************************************************************************* - * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access - * and allow Non-Secure masters full access - ******************************************************************************/ -static void init_tzc400(void) -{ - tzc_init(TZC400_BASE); - - /* Disable filters. */ - tzc_disable_filters(); - - /* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the - * same configuration to all filters in the TZC. */ - tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 1, - DRAM_NS_BASE, DRAM_NS_BASE + DRAM_NS_SIZE - 1, - TZC_REGION_S_NONE, - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)); - - /* Region 2 set to cover Secure DRAM */ - tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 2, - DRAM_SEC_BASE, DRAM_SEC_BASE + DRAM_SEC_SIZE - 1, - TZC_REGION_S_RDWR, - 0); - - /* Region 3 set to cover DRAM used by SCP for DDR retraining */ - tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 3, - DRAM_SCP_BASE, DRAM_SCP_BASE + DRAM_SCP_SIZE - 1, - TZC_REGION_S_NONE, - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP)); - - /* Region 4 set to cover Non-Secure DRAM at 0x8_8000_0000 */ - tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 4, - DRAM2_BASE, DRAM2_BASE + DRAM2_SIZE - 1, - TZC_REGION_S_NONE, - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)); - - /* Raise an exception if a NS device tries to access secure memory */ - tzc_set_action(TZC_ACTION_ERR); - - /* Enable filters. */ - tzc_enable_filters(); -} /******************************************************************************* * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs @@ -108,13 +48,14 @@ static void init_mmu401(void) } /******************************************************************************* - * Initialize the secure environment. At this moment only the TrustZone - * Controller is initialized. + * Initialize the secure environment. ******************************************************************************/ -void plat_security_setup(void) +void plat_arm_security_setup(void) { /* Initialize the TrustZone Controller */ - init_tzc400(); + arm_tzc_setup(); + /* Do ARM CSS SoC security setup */ + soc_css_security_setup(); /* Initialize the SMMU SSD tables*/ init_mmu401(); } diff --git a/plat/juno/plat_topology.c b/plat/juno/plat_topology.c deleted file mode 100644 index 24be767..0000000 --- a/plat/juno/plat_topology.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <platform_def.h> -#include <psci.h> - -unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) -{ - /* Report 1 (absent) instance at levels higher that the cluster level */ - if (aff_lvl > MPIDR_AFFLVL1) - return 1; - - if (aff_lvl == MPIDR_AFFLVL1) - return 2; /* We have two clusters */ - - return mpidr & 0x100 ? 4 : 2; /* 4 cpus in cluster 1, 2 in cluster 0 */ -} - -unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) -{ - return aff_lvl <= MPIDR_AFFLVL1 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; -} - -int plat_setup_topology(void) -{ - /* Juno todo: Make topology configurable via SCC */ - return 0; -} diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk index 6877814..8399c0a 100644 --- a/plat/juno/platform.mk +++ b/plat/juno/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -28,79 +28,18 @@ # POSSIBILITY OF SUCH DAMAGE. # -# On Juno, the Secure Payload can be loaded either in Trusted SRAM (default) or -# Secure DRAM allocated by the TrustZone Controller. +PLAT_INCLUDES := -Iplat/juno/include -PLAT_TSP_LOCATION := tsram +PLAT_BL_COMMON_SOURCES := plat/juno/aarch64/plat_helpers.S -ifeq (${PLAT_TSP_LOCATION}, tsram) - PLAT_TSP_LOCATION_ID := PLAT_TRUSTED_SRAM_ID -else ifeq (${PLAT_TSP_LOCATION}, dram) - PLAT_TSP_LOCATION_ID := PLAT_DRAM_ID -else - $(error "Unsupported PLAT_TSP_LOCATION value") -endif +BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S -# Process flags -$(eval $(call add_define,PLAT_TSP_LOCATION_ID)) +BL2_SOURCES += plat/juno/plat_security.c \ +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S -PLAT_INCLUDES := -Iplat/juno/include/ - -PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ - drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - drivers/io/io_storage.c \ - lib/aarch64/xlat_tables.c \ - plat/common/aarch64/plat_common.c \ - plat/common/plat_gic.c \ - plat/juno/plat_io_storage.c - -BL1_SOURCES += drivers/arm/cci/cci.c \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S \ - plat/common/aarch64/platform_up_stack.S \ - plat/juno/bl1_plat_setup.c \ - plat/juno/aarch64/bl1_plat_helpers.S \ - plat/juno/aarch64/plat_helpers.S \ - plat/juno/aarch64/juno_common.c - -BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ - plat/common/aarch64/platform_up_stack.S \ - plat/juno/bl2_plat_setup.c \ - plat/juno/mhu.c \ - plat/juno/plat_security.c \ - plat/juno/aarch64/plat_helpers.S \ - plat/juno/aarch64/juno_common.c \ - plat/juno/scp_bootloader.c \ - plat/juno/scpi.c - -BL31_SOURCES += drivers/arm/cci/cci.c \ - drivers/arm/gic/arm_gic.c \ - drivers/arm/gic/gic_v2.c \ - drivers/arm/gic/gic_v3.c \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S \ - plat/common/aarch64/platform_mp_stack.S \ - plat/juno/bl31_plat_setup.c \ - plat/juno/mhu.c \ - plat/juno/aarch64/plat_helpers.S \ - plat/juno/aarch64/juno_common.c \ - plat/juno/plat_pm.c \ - plat/juno/plat_topology.c \ - plat/juno/scpi.c - -ifneq (${TRUSTED_BOARD_BOOT},0) - BL1_SOURCES += plat/juno/juno_trusted_boot.c - BL2_SOURCES += plat/juno/juno_trusted_boot.c -endif - -ifneq (${RESET_TO_BL31},0) - $(error "Using BL3-1 as the reset vector is not supported on Juno. \ - Please set RESET_TO_BL31 to 0.") -endif - -NEED_BL30 := yes # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_806969 := 0 @@ -109,3 +48,8 @@ ERRATA_A57_813420 := 1 # Enable option to skip L1 data cache flush during the Cortex-A57 cluster # power down sequence SKIP_A57_L1_FLUSH_PWR_DWN := 1 + +include plat/arm/board/common/board_css.mk +include plat/arm/common/arm_common.mk +include plat/arm/soc/common/soc_css.mk +include plat/arm/css/common/css_common.mk diff --git a/plat/juno/scp_bootloader.c b/plat/juno/scp_bootloader.c deleted file mode 100644 index a6d25d4..0000000 --- a/plat/juno/scp_bootloader.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch_helpers.h> -#include <platform.h> -#include "juno_def.h" -#include "mhu.h" -#include "scp_bootloader.h" -#include "scpi.h" - -/* Boot commands sent from AP -> SCP */ -#define BOOT_CMD_START 0x01 -#define BOOT_CMD_DATA 0x02 - -typedef struct { - uint32_t image_size; -} cmd_start_payload; - -typedef struct { - uint32_t sequence_num; - uint32_t offset; - uint32_t size; -} cmd_data_payload; - -#define BOOT_DATA_MAX_SIZE 0x1000 - -/* Boot commands sent from SCP -> AP */ -#define BOOT_CMD_ACK 0x03 -#define BOOT_CMD_NACK 0x04 - -typedef struct { - uint32_t sequence_num; -} cmd_ack_payload; - -/* - * Unlike the runtime protocol, the boot protocol uses the same memory region - * for both AP -> SCP and SCP -> AP transfers; define the address of this... - */ -static void * const cmd_payload = (void *)(MHU_SECURE_BASE + 0x0080); - -static void *scp_boot_message_start(void) -{ - mhu_secure_message_start(); - - return cmd_payload; -} - -static void scp_boot_message_send(unsigned command, size_t size) -{ - /* Make sure payload can be seen by SCP */ - if (MHU_PAYLOAD_CACHED) - flush_dcache_range((unsigned long)cmd_payload, size); - - /* Send command to SCP */ - mhu_secure_message_send(command | (size << 8)); -} - -static uint32_t scp_boot_message_wait(size_t size) -{ - uint32_t response = mhu_secure_message_wait(); - - /* Make sure we see the reply from the SCP and not any stale data */ - if (MHU_PAYLOAD_CACHED) - inv_dcache_range((unsigned long)cmd_payload, size); - - return response & 0xff; -} - -static void scp_boot_message_end(void) -{ - mhu_secure_message_end(); -} - -static int transfer_block(uint32_t sequence_num, uint32_t offset, uint32_t size) -{ - cmd_data_payload *cmd_data = scp_boot_message_start(); - cmd_data->sequence_num = sequence_num; - cmd_data->offset = offset; - cmd_data->size = size; - - scp_boot_message_send(BOOT_CMD_DATA, sizeof(*cmd_data)); - - cmd_ack_payload *cmd_ack = cmd_payload; - int ok = scp_boot_message_wait(sizeof(*cmd_ack)) == BOOT_CMD_ACK - && cmd_ack->sequence_num == sequence_num; - - scp_boot_message_end(); - - return ok; -} - -int scp_bootloader_transfer(void *image, unsigned int image_size) -{ - uintptr_t offset = (uintptr_t)image - MHU_SECURE_BASE; - uintptr_t end = offset + image_size; - uint32_t response; - - mhu_secure_init(); - - /* Initiate communications with SCP */ - do { - cmd_start_payload *cmd_start = scp_boot_message_start(); - cmd_start->image_size = image_size; - - scp_boot_message_send(BOOT_CMD_START, sizeof(*cmd_start)); - - response = scp_boot_message_wait(0); - - scp_boot_message_end(); - } while (response != BOOT_CMD_ACK); - - /* Transfer image to SCP a block at a time */ - uint32_t sequence_num = 1; - size_t size; - while ((size = end - offset) != 0) { - if (size > BOOT_DATA_MAX_SIZE) - size = BOOT_DATA_MAX_SIZE; - while (!transfer_block(sequence_num, offset, size)) - ; /* Retry forever */ - offset += size; - sequence_num++; - } - - /* Wait for SCP to signal it's ready */ - return scpi_wait_ready(); -} diff --git a/plat/juno/scp_bootloader.h b/plat/juno/scp_bootloader.h deleted file mode 100644 index e872513..0000000 --- a/plat/juno/scp_bootloader.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __SCP_BOOTLOADER_H__ -#define __SCP_BOOTLOADER_H__ - -int scp_bootloader_transfer(void *image, unsigned int image_size); - -#endif diff --git a/plat/juno/scpi.c b/plat/juno/scpi.c deleted file mode 100644 index 950c00b..0000000 --- a/plat/juno/scpi.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch_helpers.h> -#include <platform.h> -#include "juno_def.h" -#include "mhu.h" -#include "scpi.h" - -#define MHU_SECURE_SCP_TO_AP_PAYLOAD (MHU_SECURE_BASE+0x0080) -#define MHU_SECURE_AP_TO_SCP_PAYLOAD (MHU_SECURE_BASE+0x0280) - -#define SIZE_SHIFT 20 /* Bit position for size value in MHU header */ -#define SIZE_MASK 0x1ff /* Mask to extract size value in MHU header*/ - - -void *scpi_secure_message_start(void) -{ - mhu_secure_message_start(); - - /* Return address of payload area. */ - return (void *)MHU_SECURE_AP_TO_SCP_PAYLOAD; -} - -void scpi_secure_message_send(unsigned command, size_t size) -{ - /* Make sure payload can be seen by SCP */ - if (MHU_PAYLOAD_CACHED) - flush_dcache_range(MHU_SECURE_AP_TO_SCP_PAYLOAD, size); - - mhu_secure_message_send(command | (size << SIZE_SHIFT)); -} - -unsigned scpi_secure_message_receive(void **message_out, size_t *size_out) -{ - uint32_t response = mhu_secure_message_wait(); - - /* Get size of payload */ - size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; - - /* Clear size from response */ - response &= ~(SIZE_MASK << SIZE_SHIFT); - - /* Make sure we don't read stale data */ - if (MHU_PAYLOAD_CACHED) - inv_dcache_range(MHU_SECURE_SCP_TO_AP_PAYLOAD, size); - - if (size_out) - *size_out = size; - - if (message_out) - *message_out = (void *)MHU_SECURE_SCP_TO_AP_PAYLOAD; - - return response; -} - -void scpi_secure_message_end(void) -{ - mhu_secure_message_end(); -} - -static void scpi_secure_send32(unsigned command, uint32_t message) -{ - *(__typeof__(message) *)scpi_secure_message_start() = message; - scpi_secure_message_send(command, sizeof(message)); - scpi_secure_message_end(); -} - -int scpi_wait_ready(void) -{ - /* Get a message from the SCP */ - scpi_secure_message_start(); - size_t size; - unsigned command = scpi_secure_message_receive(NULL, &size); - scpi_secure_message_end(); - - /* We are expecting 'SCP Ready', produce correct error if it's not */ - scpi_status_t response = SCP_OK; - if (command != SCPI_CMD_SCP_READY) - response = SCP_E_SUPPORT; - else if (size != 0) - response = SCP_E_SIZE; - - /* Send our response back to SCP */ - scpi_secure_send32(command, response); - - return response == SCP_OK ? 0 : -1; -} - -void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state, - scpi_power_state_t cluster_state, scpi_power_state_t css_state) -{ - uint32_t state = mpidr & 0x0f; /* CPU ID */ - state |= (mpidr & 0xf00) >> 4; /* Cluster ID */ - state |= cpu_state << 8; - state |= cluster_state << 12; - state |= css_state << 16; - scpi_secure_send32(SCPI_CMD_SET_CSS_POWER_STATE, state); -} - -uint32_t scpi_sys_power_state(scpi_system_state_t system_state) -{ - uint32_t *response; - size_t size; - uint8_t state = system_state & 0xff; - - /* Send the command */ - *(__typeof__(state) *)scpi_secure_message_start() = state; - scpi_secure_message_send(SCPI_CMD_SYS_POWER_STATE, sizeof(state)); - scpi_secure_message_receive((void *)&response, &size); - scpi_secure_message_end(); - return *response; -} diff --git a/plat/juno/scpi.h b/plat/juno/scpi.h deleted file mode 100644 index 8a5ef65..0000000 --- a/plat/juno/scpi.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __SCPI_H__ -#define __SCPI_H__ - -#include <stddef.h> -#include <stdint.h> - -extern void *scpi_secure_message_start(void); -extern void scpi_secure_message_send(unsigned command, size_t size); -extern unsigned scpi_secure_message_receive(void **message_out, size_t *size_out); -extern void scpi_secure_message_end(void); - - -enum { - SCP_OK = 0, /* Success */ - SCP_E_PARAM, /* Invalid parameter(s) */ - SCP_E_ALIGN, /* Invalid alignment */ - SCP_E_SIZE, /* Invalid size */ - SCP_E_HANDLER, /* Invalid handler or callback */ - SCP_E_ACCESS, /* Invalid access or permission denied */ - SCP_E_RANGE, /* Value out of range */ - SCP_E_TIMEOUT, /* Time out has ocurred */ - SCP_E_NOMEM, /* Invalid memory area or pointer */ - SCP_E_PWRSTATE, /* Invalid power state */ - SCP_E_SUPPORT, /* Feature not supported or disabled */ -}; - -typedef uint32_t scpi_status_t; - -typedef enum { - SCPI_CMD_SCP_READY = 0x01, - SCPI_CMD_SET_CSS_POWER_STATE = 0x04, - SCPI_CMD_SYS_POWER_STATE = 0x08 -} scpi_command_t; - -typedef enum { - scpi_power_on = 0, - scpi_power_retention = 1, - scpi_power_off = 3, -} scpi_power_state_t; - -typedef enum { - scpi_system_shutdown = 0, - scpi_system_reboot = 1, - scpi_system_reset = 2 -} scpi_system_state_t; - -extern int scpi_wait_ready(void); -extern void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state, - scpi_power_state_t cluster_state, scpi_power_state_t css_state); -uint32_t scpi_sys_power_state(scpi_system_state_t system_state); - -#endif /* __SCPI_H__ */ diff --git a/plat/juno/tsp/tsp-juno.mk b/plat/juno/tsp/tsp-juno.mk index 4d56ea2..55b031a 100644 --- a/plat/juno/tsp/tsp-juno.mk +++ b/plat/juno/tsp/tsp-juno.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -28,10 +28,4 @@ # POSSIBILITY OF SUCH DAMAGE. # -# TSP source files specific to Juno platform -BL32_SOURCES += drivers/arm/gic/arm_gic.c \ - drivers/arm/gic/gic_v2.c \ - plat/common/aarch64/platform_mp_stack.S \ - plat/juno/aarch64/juno_common.c \ - plat/juno/aarch64/plat_helpers.S \ - plat/juno/tsp/tsp_plat_setup.c +include plat/arm/common/tsp/arm_tsp.mk diff --git a/plat/juno/tsp/tsp_plat_setup.c b/plat/juno/tsp/tsp_plat_setup.c deleted file mode 100644 index 8293a13..0000000 --- a/plat/juno/tsp/tsp_plat_setup.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <bl_common.h> -#include <console.h> -#include <platform_tsp.h> -#include "../juno_def.h" -#include "../juno_private.h" - -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -extern unsigned long __RO_START__; -extern unsigned long __RO_END__; -extern unsigned long __BL32_END__; - -#if USE_COHERENT_MEM -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; -#endif - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL3-2 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL32_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL32_RO_BASE (unsigned long)(&__RO_START__) -#define BL32_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL32_END (unsigned long)(&__BL32_END__) - -#if USE_COHERENT_MEM -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) -#endif - -/******************************************************************************* - * Initialize the UART - ******************************************************************************/ -void tsp_early_platform_setup(void) -{ - /* - * Initialize a different console than already in use to display - * messages from TSP - */ - console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); -} - -/******************************************************************************* - * Perform platform specific setup placeholder - ******************************************************************************/ -void tsp_platform_setup(void) -{ - plat_gic_init(); -} - -/******************************************************************************* - * Perform the very early platform specific architectural setup here. At the - * moment this only intializes the MMU - ******************************************************************************/ -void tsp_plat_arch_setup(void) -{ - configure_mmu_el1(BL32_RO_BASE, - (BL32_END - BL32_RO_BASE), - BL32_RO_BASE, - BL32_RO_LIMIT -#if USE_COHERENT_MEM - , BL32_COHERENT_RAM_BASE, - BL32_COHERENT_RAM_LIMIT -#endif - ); -} |