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Diffstat (limited to 'big-little/secure_world/flat_pagetable.s')
| -rw-r--r-- | big-little/secure_world/flat_pagetable.s | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/big-little/secure_world/flat_pagetable.s b/big-little/secure_world/flat_pagetable.s new file mode 100644 index 0000000..8a4317c --- /dev/null +++ b/big-little/secure_world/flat_pagetable.s @@ -0,0 +1,111 @@ + ;; $Copyright: + ;; ---------------------------------------------------------------- + ;; This confidential and proprietary software may be used only as + ;; authorised by a licensing agreement from ARM Limited + ;; (C) COPYRIGHT 2008-2011 ARM Limited + ;; ALL RIGHTS RESERVED + ;; The entire notice above must be reproduced on all authorised + ;; copies and copies may only be made to the extent permitted + ;; by a licensing agreement from ARM Limited. + ;; ---------------------------------------------------------------- + ;; File: flat_pagetable.s + ;; ---------------------------------------------------------------- + ;; $ + + PRESERVE8 + AREA PageTable, DATA, READONLY, ALIGN=14 + EXPORT flat_pagetables + GBLL CONFIG_SMP_CPU3_AMP +CONFIG_SMP_CPU3_AMP SETL {FALSE} + +; Definitions for section descriptors +NGLOBAL EQU (1<<17) +SHARED EQU (1<<16) +APX EQU (1<<15) +TEX1 EQU (1<<12) +TEX2 EQU (1<<13) +TEX3 EQU (1<<14) +AP0 EQU (1<<10) +AP1 EQU (1<<11) +PARITY EQU (1<<9) +XN EQU (1<<4) +CACHE EQU (1<<3) +BUFFER EQU (1<<2) +SECTION EQU 2 +SECURITY EQU 0 + +; Select WBWA for both Inner and Outer cache +MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1 :OR: SECURITY) +S_RO_MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1 :OR: APX) +S_RW_MEMORY EQU (TEX1 :OR: CACHE :OR: BUFFER :OR: SECTION :OR: AP0 :OR: AP1) +; Select WBWA Inner cache, WBnWA Outer cache +;MEMORY EQU (TEX3 | TEX2 | TEX1 | BUFFER | SECTION | AP0 | AP1 | SECURITY) + +NC_MEMORY EQU (TEX1 :OR: SECTION :OR: AP0 :OR: AP1 :OR: SECURITY) +SO_MEMORY EQU (SHARED :OR: SECTION :OR: AP0 :OR: AP1 :OR: SECURITY) + +; *Don't* mark device accesses as nonsecure, or things like secure-side GIC config won't work... +DEVICE EQU (BUFFER :OR: SHARED :OR: SECTION :OR: AP0 :OR: AP1 :OR: XN ) + +NO_MEMORY EQU (SECTION) +SHARED_MEMORY EQU (MEMORY :OR: SHARED) +SHARED_S_RO_MEMORY EQU (S_RO_MEMORY :OR: SHARED) +SHARED_S_RW_MEMORY EQU (S_RW_MEMORY :OR: SHARED) +SHARED_NC_MEMORY EQU (NC_MEMORY :OR: SHARED) +SHARED_SO_MEMORY EQU (SO_MEMORY :OR: SHARED) +SHARED_DEVICE EQU (DEVICE :OR: SHARED) + +; first-level descriptors - all of them are 1MB sections + +flat_pagetables + GBLA count16 + GBLA ramstart + +count16 SETA 0 +ramstart SETA 0 + +; NOT FOR RELEASE + WHILE count16 < ramstart+0x40 + ; 0-64MB Secure ROM/NOR Flash + DCD (count16<<20) :OR: SHARED_S_RO_MEMORY +count16 SETA count16 + 1 + WEND + + WHILE count16 < ramstart+0x80 + ; 64-128MB Secure RAM + DCD (count16<<20) :OR: SHARED_S_RW_MEMORY +count16 SETA count16 + 1 + WEND + + WHILE count16 < ramstart+0x800 + ; 128-2048MB Peripheral space + DCD (count16<<20) :OR: SHARED_DEVICE +count16 SETA count16 + 1 + WEND + + WHILE count16 < ramstart+0x810 + ; 0-16MB Shared Memory + DCD (count16<<20) :OR: SHARED_MEMORY +count16 SETA count16 + 1 + WEND + + WHILE count16 < ramstart+0x81f + ; 16-31MB Strongly Ordered + DCD (count16<<20) :OR: SHARED_SO_MEMORY +count16 SETA count16 + 1 + WEND + + WHILE count16 < ramstart+0x820 + ; 31-32MB Shared Noncached Normal Memory + DCD (count16<<20) :OR: SHARED_NC_MEMORY +count16 SETA count16 + 1 + WEND + + WHILE count16 < ramstart+0x1000 + ; rest of memory is RAM + DCD (count16<<20) :OR: SHARED_MEMORY +count16 SETA count16 + 1 + WEND + + END + |