diff options
| author | Andrey Konovalov <andrey.konovalov@linaro.org> | 2013-04-18 20:25:57 +0400 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2013-04-18 20:25:57 +0400 |
| commit | 9e96e8e0059f3100690af85e64736ca87d6ecaaf (patch) | |
| tree | 5b71215042d0fd380dce6373700ad47f4da17275 | |
| parent | 3a58649068df52162ef63dd0f1c98d231f667b05 (diff) | |
| parent | 50fc7f8001eaf06f459f7ea07bfcdb3f875ab372 (diff) | |
Merge branch 'tracking-samslt-all' into merge-linux-linaro
67 files changed, 4079 insertions, 80 deletions
diff --git a/Documentation/devicetree/bindings/fb/samsung-fb.txt b/Documentation/devicetree/bindings/fb/samsung-fb.txt new file mode 100644 index 000000000000..612bd9f83277 --- /dev/null +++ b/Documentation/devicetree/bindings/fb/samsung-fb.txt @@ -0,0 +1,148 @@ +* Samsung Display Controller Framebuffer Controller + +The display controller is used to transfer image data from memory to a +external display device such as an RGB interface LCD panel. It supports +various color formats such as rgb and yuv. It also supports multiple window +overlays. + +Required properties: + + - compatible: should be one of the following + - samsung,exynos4210-fimd: for fimd compatible with Exynos4210 fimd + - samsung,s5pv210-fimd: for fimd compatible with s5pv210 fimd + + - reg: physical base address of the controller and length of memory + mapped region. + + - interrupts: Three interrupts should be specified. The format of the + interrupt specifier depends on the interrupt controller. The interrupts + should be specified in the following order. + - VSYNC (Video Frame) interrupt + - Video FIFO level interrupt + - FIMD System Interrupt + + - gpios: The gpios used to interface with the external LCD panel. For a + panel with rgb interface, the gpio interface consists of video data + lines, HSYNC, VSYNC, Pixel Clock and Data Enable. The gpio's used for + these interface lines can be listed under this property in any order. + + - samsung,fimd-display: The fimd controller is interfaced with the a + display device such as a lcd panel. This property should specify the + phandle of the display device node. For a display device node that + represents a RGB type display interface, it is expected to specify the + video interface timing using the following properties. + + - lcd-htiming: Specifies the horizontal timing for the overlay. The + horizontal timing includes four parameters in the following order. + + - horizontal back porch (in number of lcd clocks) + - horizontal front porch (in number of lcd clocks) + - hsync pulse width (in number of lcd clocks) + - Display panels X resolution. + + - lcd-vtiming: Specifies the vertical timing for the overlay. The + vertical timing includes four parameters in the following order. + + - vertical back porch (in number of lcd lines) + - vertical front porch (in number of lcd lines) + - vsync pulse width (in number of lcd clocks) + - Y resolution. + + - Overlay/Windows: Multiple overlays/windows can be specified as child + nodes. Each window should have the following properties (optional + window properties are marked as 'optional'). + + - samsung,fimd-win-id: Specifies the window number of the fimd controller. + + - samsung,fimd-win-bpp: Specifies the bits per pixel. Two values should + be specified in the following order. + - default-bpp: bpp supported by the overlay. + - max-bpp: maximum required bpp for the overlay. + + - samsung,fimd-win-res: (OPTIONAL) Specifies the window resolution in + pixels. The resolution contains the X and Y pixel values with X being + specified first. If this property is not specified, the window + resolution is set to be equal to the display panel resolution. + + - samsung,fimd-win-virtres: (OPTIONAL) Specifies the resolution of the + virtual frame buffer for the window. The resolution contains the X + and Y resolution in pixels with value of X being the specified first. + +Optional properties: + + - samsung,fimd-vidout-rgb: Video output format is RGB. + - samsung,fimd-inv-hsync: invert hsync pulse polarity. + - samsung,fimd-inv-vsync: invert vsync pulse polarity. + - samsung,fimd-inv-vclk: invert video clock polarity. + - samsung,fimd-inv-vden: invert video enable signal polarity. + - samsung,fimd-frame-rate: Number of video frames per second. + +Example: + + The following is an example for the fimd framebuffer controller is split + into two portions. The SoC specific portion can be specified in the SoC + specific dts file. The board specific portion can be specified in the + board specific dts file. + + - SoC Specific portion + + fimd@11C00000 { + compatible = "samsung,exynos4210-fimd"; + interrupt-parent = <&combiner>; + reg = <0x11C00000 0x8000>; + interrupts = <11 1>, <11 0>, <11 2>; + }; + + - Board Specific portion + + fimd@11C00000 { + samsung,fimd-display = <&lcd_fimd0>; + samsung,fimd-vidout-rgb; + samsung,fimd-inv-hsync; + samsung,fimd-inv-vsync; + samsung,fimd-inv-vclk; + samsung,fimd-frame-rate = <60>; + + gpios = <&gpf0 0 2 0 0>, + <&gpf0 1 2 0 0>, + <&gpf0 2 2 0 0>, + <&gpf0 3 2 0 0>, + <&gpf0 4 2 0 0>, + <&gpf0 5 2 0 0>, + <&gpf0 6 2 0 0>, + <&gpf0 7 2 0 0>, + <&gpf1 0 2 0 0>, + <&gpf1 1 2 0 0>, + <&gpf1 2 2 0 0>, + <&gpf1 3 2 0 0>, + <&gpf1 4 2 0 0>, + <&gpf1 5 2 0 0>, + <&gpf1 6 2 0 0>, + <&gpf1 7 2 0 0>, + <&gpf2 0 2 0 0>, + <&gpf2 1 2 0 0>, + <&gpf2 2 2 0 0>, + <&gpf2 3 2 0 0>, + <&gpf2 4 2 0 0>, + <&gpf2 5 2 0 0>, + <&gpf2 6 2 0 0>, + <&gpf2 7 2 0 0>, + <&gpf3 0 2 0 0>, + <&gpf3 1 2 0 0>, + <&gpf3 2 2 0 0>, + <&gpf3 3 2 0 0>; + + window0 { + samsung,fimd-win-id = <0>; + samsung,fimd-win-bpp = <32 24>; + samsung,fimd-win-res = <512 300>; + samsung,fimd-win-vres = <1024 600>; + }; + + window1 { + samsung,fimd-win-id = <1>; + samsung,fimd-win-bpp = <32 24>; + samsung,fimd-win-res = <1024 200>; + samsung,fimd-win-vres = <1024 600>; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt new file mode 100644 index 000000000000..45dadca510fb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -0,0 +1,41 @@ +Samsung Exynos SoC USB controller + +The device node for USB controller for Samsung SOC have +following properties + +OHCI +Required properties: + - compatible: should be "samsung,exynos-ohci" for USB 2.0 + OHCI companion controller in host mode. + - reg: physical base address of the controller and length + of memory mapped. + - interrupts: interrupt number to the cpu. + +ohci { + compatible = "samsung,exynos-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; +}; + +EHCI +Required properties: + - compatible: should be "samsung,exynos-ehci" for USB 2.0 + EHCI controller in host mode. + - reg: physical base address of the controller and length + of memory mapped. + - interrupts: interrupt number to the cpu. + +Optional properties: + - samsung,vbus-gpio: if present, specifies the GPIO + that needs to be pulled up for the bus to be powered. + +ehci { + compatible = "samsung,exynos-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; +}; + +ehci { + samsung,vbus-gpio = <&gpx2 6 1 3 3>; +}; + diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 32d3c0da4c87..6237f74eefa9 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1480,6 +1480,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. ltpc= [NET] Format: <io>,<irq>,<dma> + mac= [NET] + Used ASIX drivers. + Example: mac=12:34:56:78:ab:cd + machvec= [IA-64] Force the use of a particular machine-vector (machvec) in a generic kernel. Example: machvec=hpzx1_swiotlb @@ -796,7 +796,6 @@ include/config/kernel.release: include/config/auto.conf FORCE $(Q)rm -f $@ $(Q)echo "$(KERNELVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" > $@ - # Things we need to do before we recursively start building the kernel # or the modules are listed in "prepare". # A multi level approach is used. prepareN is processed before prepareN-1. @@ -846,7 +845,9 @@ define filechk_utsrelease.h echo '"$(KERNELRELEASE)" exceeds $(uts_len) characters' >&2; \ exit 1; \ fi; \ - (echo \#define UTS_RELEASE \"$(KERNELRELEASE)\";) + (echo \#define UTS_RELEASE \"$(KERNELRELEASE)\"; \ + echo \#define KERNEL_GIT_ID \"$(shell \ + git rev-parse --verify --short HEAD 2>/dev/null)\";) endef define filechk_version.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 59b0c2d14f76..38e7acdf20ab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1930,7 +1930,7 @@ config FORCE_MAX_ZONEORDER range 11 64 if ARCH_SHMOBILE default "12" if SOC_AM33XX default "9" if SA1111 - default "11" + default "14" if ARCH_EXYNOS5 help The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2fc92bf10cc4..f4dffac1979d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4412-smdk4412.dtb \ + exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ exynos5440-ssdk5440.dtb diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2feffc70814c..005376b334ad 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -47,6 +47,12 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; + pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts new file mode 100644 index 000000000000..5aa567c695e4 --- /dev/null +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -0,0 +1,544 @@ +/* + * Samsung's Exynos5250 based Arndale board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos5250.dtsi" + +/ { + model = "Insignal Arndale evaluation board based on EXYNOS5250"; + compatible = "insignal,arndale", "samsung,exynos5250"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + chosen { + bootargs = "console=ttySAC2,115200"; + }; + + codec@11000000 { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + }; + + i2c@12C60000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + samsung,i2c-slave-addr = <0x66>; + gpios = <&gpb3 0 2 3 0>, + <&gpb3 1 2 3 0>; + + s5m8767_pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + s5m8767,pmic-buck2-dvs-voltage = <1300000>; + s5m8767,pmic-buck3-dvs-voltage = <1100000>; + s5m8767,pmic-buck4-dvs-voltage = <1200000>; + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 1 0 0>, + <&gpd1 1 1 0 0>, + <&gpd1 2 1 0 0>; + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 1 0 0>, + <&gpx2 4 1 0 0>, + <&gpx2 5 1 0 0>; + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_28IO_DP_1.35V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_COMMON1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_IOPERI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_XPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_COMMON2_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_33ON_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD_COMMON3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_ABB2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_COMMON4_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDQ_MMC2_3_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_33ON_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo22_reg: LDO22 { + regulator-name = "EXT_33_OFF"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo23_reg: LDO23 { + regulator-name = "EXT_28_OFF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo25_reg: LDO25 { + regulator-name = "PVDD_LDO25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + }; + + ldo26_reg: LDO26 { + regulator-name = "EXT_18_OFF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + op_mode = <1>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1.35V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1355000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck9_reg: BUCK9 { + regulator-name = "VDD_33_OFF_EXT1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; + }; + }; + }; + + i2c@12C70000 { + status = "disabled"; + }; + + i2c@12C80000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa0 6 3 3 0>, + <&gpa0 7 3 3 0>; + + hdmiddc@50 { + compatible = "samsung,exynos5-hdmiddc"; + reg = <0x50>; + }; + }; + + i2c@12C90000 { + status = "disabled"; + }; + + i2c@12CA0000 { + status = "disabled"; + }; + + i2c@12CB0000 { + status = "disabled"; + }; + + i2c@12CC0000 { + status = "disabled"; + }; + + i2c@12CD0000 { + status = "disabled"; + }; + + i2c@12CE0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiphy@38 { + compatible = "samsung,exynos5-hdmiphy"; + reg = <0x38>; + }; + }; + + i2c@121D0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; + + sata-phy { + compatible = "samsung,sata-phy"; + reg = <0x38>; + }; + }; + + sata@122F0000 { + samsung,sata-freq = <66>; + }; + + dwmmc_0: dwmmc0@12200000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + + slot@0 { + reg = <0>; + bus-width = <8>; + gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, + <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, + <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>, + <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, + <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>; + }; + }; + + dwmmc_1: dwmmc1@12210000 { + status = "disabled"; + }; + + dwmmc_2: dwmmc2@12220000 { + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; + gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>, + <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>, + <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>; + }; + }; + + dwmmc_3: dwmmc3@12230000 { + status = "disabled"; + }; + + spi_0: spi@12d20000 { + status = "disabled"; + }; + + spi_1: spi@12d30000 { + status = "disabled"; + }; + + spi_2: spi@12d40000 { + status = "disabled"; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + clock-frequency = <50000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <64>; + hback-porch = <16>; + hsync-len = <48>; + vback-porch = <64>; + vfront-porch = <16>; + vsync-len = <3>; + }; + }; + + lcd_fimd0: lcd_panel0 { + compatible = "lcd-powercontrol"; + lcd-reset-gpio = <&gph1 4 1 0 0>; + lcd-htiming = <64 16 48 1024>; + lcd-vtiming = <64 16 3 600>; + }; + + fimd: fimd@14400000 { + samsung,fimd-display = <&lcd_fimd0>; + samsung,fimd-vidout-rgb; + samsung,fimd-inv-hsync; + samsung,fimd-inv-vsync; + samsung,fimd-inv-vclk; + samsung,fimd-frame-rate = <60>; + + gpios = <&gph1 0 2 0 0>, + <&gph1 1 2 0 0>; + + window0 { + samsung,fimd-win-id = <0>; + samsung,fimd-win-bpp = <32 24>; + samsung,fimd-win-res = <1024 600>; + samsung,fimd-win-vres = <1024 600>; + }; + + window1 { + samsung,fimd-win-id = <1>; + samsung,fimd-win-bpp = <32 24>; + samsung,fimd-win-res = <1024 600>; + samsung,fimd-win-vres = <1024 600>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + menu { + label = "SW-TACT2"; + gpios = <&gpx1 4 0 0x10000 2>; + linux,code = <139>; + gpio-key,wakeup; + }; + + home { + label = "SW-TACT3"; + gpios = <&gpx1 5 0 0x10000 2>; + linux,code = <102>; + gpio-key,wakeup; + }; + + up { + label = "SW-TACT4"; + gpios = <&gpx1 6 0 0x10000 2>; + linux,code = <103>; + gpio-key,wakeup; + }; + + down { + label = "SW-TACT5"; + gpios = <&gpx1 7 0 0x10000 2>; + linux,code = <108>; + gpio-key,wakeup; + }; + + back { + label = "SW-TACT6"; + gpios = <&gpx2 0 0 0x10000 2>; + linux,code = <158>; + gpio-key,wakeup; + }; + + wakeup { + label = "SW-TACT7"; + gpios = <&gpx2 1 0 0x10000 2>; + linux,code = <143>; + gpio-key,wakeup; + }; + }; + + hdmi { + hpd-gpio = <&gpx3 7 0xf 1 3>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; + }; + + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDD_33ON_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 0 0 2>; + enable-active-high; + }; + + reg_hdmi_en: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-en"; + }; + + ehci { + samsung,hub-reset = <&gpx3 5 1 0 3>; + samsung,hub-connect = <&gpd1 7 1 0 3>; + }; +}; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 1b8d4106d338..980c03cdfec1 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -23,6 +23,14 @@ reg = <0x40000000 0x80000000>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + chosen { bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; @@ -231,4 +239,8 @@ samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&wm8994>; }; + + ehci { + samsung,vbus-gpio = <&gpx2 6 1 3 3>; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b1ac73e21c80..2d702f9819b7 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -47,10 +47,15 @@ }; gic:interrupt-controller@10481000 { - compatible = "arm,cortex-a9-gic"; + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; + #address-cells = <0>; interrupt-controller; - reg = <0x10481000 0x1000>, <0x10482000 0x2000>; + reg = <0x10481000 0x1000>, + <0x10482000 0x2000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; }; combiner:interrupt-controller@10440000 { @@ -69,6 +74,12 @@ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, <22 4>; + }; + watchdog { compatible = "samsung,s3c2410-wdt"; reg = <0x101D0000 0x100>; @@ -81,6 +92,37 @@ interrupts = <0 96 0>; }; + usbphy { + #address-cells = <1>; + #size-cells = <1>; + compatible = "samsung,exynos5250-usbphy"; + reg = <0x12130000 0x100>, <0x12100000 0x100>; + ranges; + + usbphy-sys { + /* USB device and host PHY_CONTROL registers */ + reg = <0x10040704 0x8>; + }; + }; + + usb@12000000 { + compatible = "samsung,exynos-dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + }; + + ohci { + compatible = "samsung,exynos-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; + }; + + ehci { + compatible = "samsung,exynos-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; + }; + rtc { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; @@ -200,11 +242,11 @@ #size-cells = <0>; }; - i2c@121D0000 { - compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121D0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; + i2c_sataphy: i2c@121D0000 { + compatible = "samsung,exynos5-sata-phy-i2c"; + reg = <0x121D0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; }; spi_0: spi@12d20000 { @@ -616,6 +658,13 @@ interrupts = <0 88 0>; }; + fimd: fimd@14400000 { + compatible = "samsung,exynos4210-fimd"; + interrupt-parent = <&combiner>; + reg = <0x14400000 0x40000>; + interrupts = <18 5>, <18 4>, <18 6>; + }; + hdmi { compatible = "samsung,exynos5-hdmi"; reg = <0x14530000 0x70000>; diff --git a/arch/arm/configs/android_origen_quad_defconfig b/arch/arm/configs/android_origen_quad_defconfig new file mode 100644 index 000000000000..81e604a88518 --- /dev/null +++ b/arch/arm/configs/android_origen_quad_defconfig @@ -0,0 +1,190 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_GCOV_KERNEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_MACH_SMDKC210=y +CONFIG_MACH_ARMLEX4210=y +CONFIG_MACH_UNIVERSAL_C210=y +CONFIG_MACH_NURI=y +CONFIG_MACH_SMDK4412=y +CONFIG_MACH_ORIGEN_QUAD=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=4 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_CMDLINE="root=/dev/mmcblk0p1 rw rootwait console=ttySAC2,115200 init=/linuxrc mem=256M" +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_ACCT=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_CFG80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_SAMSUNG=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_UNIDISPLAY_TS=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_S3C2410=y +# CONFIG_HWMON is not set +CONFIG_MFD_SEC_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_USB_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_FIMC=y +CONFIG_VIDEO_S5P_FIMC=y +CONFIG_VIDEO_SAMSUNG_S5P_TV=y +CONFIG_VIDEO_SAMSUNG_S5P_HDMI=y +CONFIG_VIDEO_SAMSUNG_S5P_MIXER=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_MFC=y +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_DRM=y +CONFIG_ION=y +CONFIG_MALI400MP=y +CONFIG_USING_PMM=y +CONFIG_UMP=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SAMSUNG_ORIGEN_QUAD_RT5631=y +CONFIG_USB_SUPPORT=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_NETDEVICES=y +CONFIG_USB_USBNET=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_PERSISTENT_TRACER=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_SWITCH=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_PSTORE=y +CONFIG_PSTORE_RAM=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_INFO=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_S3C_UART2=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/arndale_android_defconfig b/arch/arm/configs/arndale_android_defconfig new file mode 100644 index 000000000000..b01bb6e70902 --- /dev/null +++ b/arch/arm/configs/arndale_android_defconfig @@ -0,0 +1,144 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +# CONFIG_ARCH_EXYNOS4 is not set +CONFIG_ARCH_EXYNOS5=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=2 +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init= mem=256M" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_IPV6_SIT=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_EXYNOS=y +CONFIG_NETDEVICES=y +CONFIG_AX88796=y +CONFIG_AX88796_93CX6=y +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +CONFIG_USB_USBNET=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C_GPIO=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_EXYNOS_THERMAL=y +CONFIG_MFD_SEC_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +CONFIG_HID_LOGITECH_DJ=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DWC3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_STORAGE=y +CONFIG_SAMSUNG_USBPHY=y +CONFIG_USB_GADGET=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_PERSISTENT_TRACER=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_SWITCH=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT2_FS_XIP=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_DEBUG=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_S3C_UART2=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/arndale_ubuntu_defconfig b/arch/arm/configs/arndale_ubuntu_defconfig new file mode 100644 index 000000000000..295ff6216ca1 --- /dev/null +++ b/arch/arm/configs/arndale_ubuntu_defconfig @@ -0,0 +1,190 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +# CONFIG_ARCH_EXYNOS4 is not set +CONFIG_ARCH_EXYNOS5=y +CONFIG_ARM_LPAE=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_VMSPLIT_2G=y +CONFIG_NR_CPUS=2 +CONFIG_THUMB2_KERNEL=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_SECCOMP=y +CONFIG_CC_STACKPROTECTOR=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init= mem=256M" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EXTRA_FIRMWARE="edid-1920x1080.fw" +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_OOPS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_NAND=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_EXYNOS=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_AX88796=y +CONFIG_AX88796_93CX6=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_DM9601=y +CONFIG_USB_NET_MCS7830=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_EXYNOS_THERMAL=y +CONFIG_MFD_SEC_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_DRM=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_EXYNOS=y +CONFIG_DRM_EXYNOS_DMABUF=y +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DWC3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_STORAGE=y +CONFIG_SAMSUNG_USBPHY=y +CONFIG_USB_GADGET=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_BTRFS_FS=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_AUTOFS4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_INFO=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_FUNCTION_TRACER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_S3C_UART2=y +CONFIG_EARLY_PRINTK=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 70f94c87479d..b05388538756 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -398,6 +398,39 @@ config MACH_SMDK4412 select SOC_EXYNOS4412 help Machine support for Samsung SMDK4412 + +config MACH_ORIGEN_QUAD + bool "ORIGEN_QUAD" + select SOC_EXYNOS4412 + select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_I2C3 + select S3C_DEV_I2C4 + select S3C_DEV_RTC + select S3C_DEV_WDT + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 + select S5P_DEV_MFC + select S5P_DEV_TV + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_PWM + select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_I2C2 + select EXYNOS4_SETUP_I2C3 + select EXYNOS4_SETUP_I2C4 + select EXYNOS4_SETUP_SDHCI + select S5P_DEV_I2C_HDMIPHY + select S3C24XX_PWM + help + Machine support for ORIGEN based on Samsung EXYNOS4412 + endif comment "Flattened Device Tree based board for EXYNOS SoCs" @@ -423,6 +456,8 @@ config MACH_EXYNOS5_DT depends on ARCH_EXYNOS5 select ARM_AMBA select USE_OF + select USB_ARCH_HAS_XHCI + select S5P_DEV_FIMD0 help Machine support for Samsung EXYNOS5 machine with device tree enabled. Select this if a fdt blob is available for the EXYNOS5 SoC based board. diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 435757e57bb4..3ee9fc89b357 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o +obj-$(CONFIG_MACH_ORIGEN_QUAD) += mach-origen_quad.o obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index b0ea31fc9fb8..87c022bf3f2c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -746,6 +746,11 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_fsys_ctrl , .ctrlbit = (1 << 18), }, { + .name = "usbdrd30", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 19), + }, { .name = "usbotg", .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), @@ -1015,6 +1020,16 @@ static struct clksrc_sources exynos5_clkset_group = { .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list), }; +struct clk *exynos5_clkset_usbdrd30_list[] = { + [0] = &exynos5_clk_mout_mpll.clk, + [1] = &exynos5_clk_mout_cpll.clk, +}; + +struct clksrc_sources exynos5_clkset_usbdrd30 = { + .sources = exynos5_clkset_usbdrd30_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list), +}; + /* Possible clock sources for aclk_266_gscl_sub Mux */ static struct clk *clk_src_gscl_266_list[] = { [0] = &clk_ext_xtal_mux, @@ -1309,7 +1324,17 @@ static struct clksrc_clk exynos5_clksrcs[] = { .parent = &exynos5_clk_mout_cpll.clk, }, .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 }, - }, + }, { + + .clk = { + .name = "sclk_usbdrd30", + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 28), + }, + .sources = &exynos5_clkset_usbdrd30, + .reg_src = {.reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1}, + .reg_div = {.reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4}, + } }; /* Clock initialization code */ diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 7bc0f9aa8b33..25da8abd7c92 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -38,6 +38,7 @@ #include <mach/regs-irq.h> #include <mach/regs-pmu.h> #include <mach/regs-gpio.h> +#include <mach/irqs.h> #include <plat/cpu.h> #include <plat/clock.h> @@ -464,6 +465,8 @@ void __init exynos4_init_irq(void) * uses GIC instead of VIC. */ s5p_init_irq(NULL, 0); + + gic_arch_extn.irq_set_wake = s3c_irq_wake; } void __init exynos5_init_irq(void) @@ -876,3 +879,30 @@ static int __init exynos_init_irq_eint(void) return 0; } arch_initcall(exynos_init_irq_eint); + +static struct resource exynos4_pmu_resource[] = { + DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU), + DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1), +#if defined(CONFIG_SOC_EXYNOS4412) + DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2), + DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3), +#endif +}; + +static struct platform_device exynos4_device_pmu = { + .name = "arm-pmu", + .num_resources = ARRAY_SIZE(exynos4_pmu_resource), + .resource = exynos4_pmu_resource, +}; + +static int __init exynos_armpmu_init(void) +{ + if (!of_have_populated_dt()) { + if (soc_is_exynos4210() || soc_is_exynos4212()) + exynos4_device_pmu.num_resources = 2; + platform_device_register(&exynos4_device_pmu); + } + + return 0; +} +arch_initcall(exynos_armpmu_init); diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index c3f825b27947..d9712fed163f 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -99,13 +99,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) if (cpu == 1) __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION); - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); + wfi(); if (pen_release == cpu_logical_map(cpu)) { /* diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 1f4dc35cd4b9..0bef0d24b5cb 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -128,7 +128,7 @@ #define EXYNOS4_IRQ_ADC1 IRQ_SPI(107) #define EXYNOS4_IRQ_PEN1 IRQ_SPI(108) #define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109) -#define EXYNOS4_IRQ_PMU IRQ_SPI(110) +#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110) #define EXYNOS4_IRQ_GPS IRQ_SPI(111) #define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) #define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113) @@ -139,6 +139,11 @@ #define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4) #define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4) +#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2) +#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2) +#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2) +#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2) + #define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) #define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) #define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) @@ -168,7 +173,10 @@ #define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) #define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) -#define EXYNOS4_MAX_COMBINER_NR 16 +#define EXYNOS4210_MAX_COMBINER_NR 16 +#define EXYNOS4212_MAX_COMBINER_NR 18 +#define EXYNOS4412_MAX_COMBINER_NR 20 +#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR #define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 @@ -233,7 +241,6 @@ #define IRQ_TC EXYNOS4_IRQ_PEN0 #define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD -#define IRQ_PMU EXYNOS4_IRQ_PMU #define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO #define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC @@ -465,6 +472,9 @@ #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) #define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) +/* optional GPIO interrupts */ +#define IRQ_BOARD_START IRQ_GPIO_END + /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 1df6abbf53b8..6297df8223d3 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -178,6 +178,7 @@ #define EXYNOS4_PA_MIPI_CSIS1 0x11890000 #define EXYNOS4_PA_FIMD0 0x11C00000 +#define EXYNOS5_PA_FIMD1 0x14400000 #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) #define EXYNOS4_PA_DWMCI 0x12550000 @@ -192,6 +193,9 @@ #define EXYNOS4_PA_SATA 0x12560000 #define EXYNOS4_PA_SATAPHY 0x125D0000 #define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 +#define EXYNOS5_PA_SATA_PHY_CTRL 0x12170000 +#define EXYNOS5_PA_SATA_PHY_I2C 0x121D0000 +#define EXYNOS5_PA_SATA_BASE 0x122F0000 #define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS5_PA_SROMC 0x12250000 diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 3f30aa1ae354..3e0f9375e4d1 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -369,4 +369,7 @@ #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) +/* Only for EXYNOS5250 */ +#define EXYNOS5_SATA_PHY_CONTROL S5P_PMUREG(0x0724) + #endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-sata.h b/arch/arm/mach-exynos/include/mach/regs-sata.h new file mode 100644 index 000000000000..80dd564eb324 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/regs-sata.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SATA PHY controller definition + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define EXYNOS5_SATA_RESET 0x4 +#define RESET_CMN_RST_N (1 << 1) +#define LINK_RESET 0xF0000 + +#define EXYNOS5_SATA_MODE0 0x10 + +#define EXYNOS5_SATA_CTRL0 0x14 +#define CTRL0_P0_PHY_CALIBRATED_SEL (1 << 9) +#define CTRL0_P0_PHY_CALIBRATED (1 << 8) + +#define EXYNOS5_SATA_PHSATA_CTRLM 0xE0 +#define PHCTRLM_REF_RATE (1 << 1) +#define PHCTRLM_HIGH_SPEED (1 << 0) + +#define EXYNOS5_SATA_PHSATA_STATM 0xF0 +#define PHSTATM_PLL_LOCKED (1 << 0) + +#define SATA_PHY_CON_RESET 0xF003F diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index acaeb14db54b..c8e741930776 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -14,6 +14,7 @@ #include <linux/serial_core.h> #include <linux/memblock.h> #include <linux/io.h> +#include <linux/fb.h> #include <asm/mach/arch.h> #include <mach/map.h> @@ -79,11 +80,11 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos4210-spi.1", NULL), OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, "exynos4210-spi.2", NULL), - OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000, + OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", EXYNOS5_PA_SATA_BASE, "exynos5-sata", NULL), - OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000, + OF_DEV_AUXDATA("samsung,exynos5-sata-phy", EXYNOS5_PA_SATA_PHY_CTRL, "exynos5-sata-phy", NULL), - OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000, + OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", EXYNOS5_PA_SATA_PHY_I2C, "exynos5-sata-phy-i2c", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), @@ -139,9 +140,27 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000, "exynos-sysmmu.14", NULL), /* G2D */ + OF_DEV_AUXDATA("samsung,exynos-dwc3", 0x12000000, + "exynos-dwc3", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-usbphy", 0x12130000, + "s3c-usbphy", NULL), + OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000, + "exynos-ohci", NULL), + OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000, + "s5p-ehci", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-fimd", EXYNOS5_PA_FIMD1, + "exynos5-fb.1", NULL), {}, }; +static void __init exynos5_setup_fimd(void) +{ + unsigned int reg; + reg = __raw_readl(S3C_VA_SYS + 0x0214); + reg |= (1 << 15); + __raw_writel(reg, S3C_VA_SYS + 0x0214); +} + static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0, "exynos4210-uart.0", NULL), @@ -158,6 +177,11 @@ static void __init exynos5_dt_map_io(void) s3c24xx_init_clocks(24000000); } +static void exynos5_i2c_setup(void) +{ /* Setup the low-speed i2c controller interrupts */ + writel(0x0, EXYNOS5_SYS_I2C_CFG); +} + static void __init exynos5_dt_machine_init(void) { struct device_node *i2c_np; @@ -182,12 +206,15 @@ static void __init exynos5_dt_machine_init(void) } } + exynos5_i2c_setup(); + if (of_machine_is_compatible("samsung,exynos5250")) of_platform_populate(NULL, of_default_bus_match_table, exynos5250_auxdata_lookup, NULL); else if (of_machine_is_compatible("samsung,exynos5440")) of_platform_populate(NULL, of_default_bus_match_table, exynos5440_auxdata_lookup, NULL); + exynos5_setup_fimd(); } static char const *exynos5_dt_compat[] __initdata = { diff --git a/arch/arm/mach-exynos/mach-origen_quad.c b/arch/arm/mach-exynos/mach-origen_quad.c new file mode 100644 index 000000000000..78ffe82f5343 --- /dev/null +++ b/arch/arm/mach-exynos/mach-origen_quad.c @@ -0,0 +1,773 @@ +/* linux/arch/arm/mach-exynos/mach-origen_quad.c + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/serial_core.h> +#include <linux/gpio.h> +#include <linux/mmc/host.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/input.h> + +#include <linux/i2c.h> +#include <linux/lcd.h> +#include <linux/mfd/samsung/s5m8767.h> +#include <linux/mfd/samsung/core.h> +#include <linux/pwm.h> +#include <linux/pwm_backlight.h> +#include <linux/regulator/machine.h> + +#include <video/platform_lcd.h> +#include <video/samsung_fimd.h> +#include <drm/exynos_drm.h> + +#include <asm/mach/arch.h> +#include <asm/hardware/gic.h> +#include <asm/mach-types.h> + +#include <plat/backlight.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> +#include <plat/mfc.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <plat/regs-serial.h> +#include <plat/sdhci.h> + +#include <mach/map.h> +#include "common.h" + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define ORIGEN_QUAD_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define ORIGEN_QUAD_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define ORIGEN_QUAD_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + + +static struct s3c2410_uartcfg origen_quad_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = ORIGEN_QUAD_UCON_DEFAULT, + .ulcon = ORIGEN_QUAD_ULCON_DEFAULT, + .ufcon = ORIGEN_QUAD_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = ORIGEN_QUAD_UCON_DEFAULT, + .ulcon = ORIGEN_QUAD_ULCON_DEFAULT, + .ufcon = ORIGEN_QUAD_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = ORIGEN_QUAD_UCON_DEFAULT, + .ulcon = ORIGEN_QUAD_ULCON_DEFAULT, + .ufcon = ORIGEN_QUAD_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = ORIGEN_QUAD_UCON_DEFAULT, + .ulcon = ORIGEN_QUAD_ULCON_DEFAULT, + .ufcon = ORIGEN_QUAD_UFCON_DEFAULT, + }, +}; + + +static struct s3c_sdhci_platdata origen_quad_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, +}; + +/* S5M8767 Regulator */ +static int s5m_cfg_irq(void) +{ + /* AP_PMIC_IRQ: EINT22 */ + s3c_gpio_cfgpin(EXYNOS4_GPX2(6), S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(EXYNOS4_GPX2(6), S3C_GPIO_PULL_UP); + return 0; +} + +static struct regulator_consumer_supply s5m8767_ldo1_supply[] = { + REGULATOR_SUPPLY("vdd_alive", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo2_supply[] = { + REGULATOR_SUPPLY("vddq_m12", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo3_supply[] = { + REGULATOR_SUPPLY("vddioap_18", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo4_supply[] = { + REGULATOR_SUPPLY("vddq_pre", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo5_supply[] = { + REGULATOR_SUPPLY("vdd18_2m", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo6_supply[] = { + REGULATOR_SUPPLY("vdd10_mpll", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo7_supply[] = { + REGULATOR_SUPPLY("vdd10_xpll", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo8_supply[] = { + REGULATOR_SUPPLY("vdd10_mipi", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo9_supply[] = { + REGULATOR_SUPPLY("vdd33_lcd", "platform-lcd"), +}; + +static struct regulator_consumer_supply s5m8767_ldo10_supply[] = { + REGULATOR_SUPPLY("vdd18_mipi", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo11_supply[] = { + REGULATOR_SUPPLY("vdd18_abb1", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo12_supply[] = { + REGULATOR_SUPPLY("vdd33_uotg", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo13_supply[] = { + REGULATOR_SUPPLY("vddioperi_18", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo14_supply[] = { + REGULATOR_SUPPLY("vdd18_abb02", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo15_supply[] = { + REGULATOR_SUPPLY("vdd10_ush", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo16_supply[] = { + REGULATOR_SUPPLY("vdd18_hsic", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo17_supply[] = { + REGULATOR_SUPPLY("vddioap_mmc012_28", NULL), +}; +static struct regulator_consumer_supply s5m8767_ldo18_supply[] = { + REGULATOR_SUPPLY("vddioperi_28", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo19_supply[] = { + REGULATOR_SUPPLY("dvdd25", NULL), +}; + + +static struct regulator_consumer_supply s5m8767_ldo20_supply[] = { + REGULATOR_SUPPLY("vdd28_cam", NULL), +}; +static struct regulator_consumer_supply s5m8767_ldo21_supply[] = { + REGULATOR_SUPPLY("vdd28_af", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo22_supply[] = { + REGULATOR_SUPPLY("vdda28_2m", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo23_supply[] = { + REGULATOR_SUPPLY("vdd_tf", NULL), +}; + + +static struct regulator_consumer_supply s5m8767_ldo24_supply[] = { + REGULATOR_SUPPLY("vdd33_a31", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo25_supply[] = { + REGULATOR_SUPPLY("vdd18_cam", NULL), +}; + +static struct regulator_consumer_supply s5m8767_ldo26_supply[] = { + REGULATOR_SUPPLY("vdd18_a31", NULL), +}; +static struct regulator_consumer_supply s5m8767_ldo27_supply[] = { + REGULATOR_SUPPLY("gps_1v8", NULL), +}; +static struct regulator_consumer_supply s5m8767_ldo28_supply[] = { + REGULATOR_SUPPLY("dvdd12", NULL), +}; + + +static struct regulator_consumer_supply s5m8767_buck1_consumer = + REGULATOR_SUPPLY("vdd_mif", NULL); + +static struct regulator_consumer_supply s5m8767_buck2_consumer = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply s5m8767_buck3_consumer = + REGULATOR_SUPPLY("vdd_int", NULL); + +static struct regulator_consumer_supply s5m8767_buck4_consumer = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_consumer_supply s5m8767_buck5_consumer = + REGULATOR_SUPPLY("vdd_m12", NULL); +static struct regulator_consumer_supply s5m8767_buck6_consumer = + REGULATOR_SUPPLY("vdd12_5m", NULL); + +static struct regulator_consumer_supply s5m8767_buck9_consumer = + REGULATOR_SUPPLY("vddf28_emmc", NULL); + + + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask,\ + _disabled) \ + static struct regulator_init_data s5m8767_##_ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(s5m8767_##_ldo##_supply), \ + .consumer_supplies = &s5m8767_##_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo1, "VDD_ALIVE", 1100000, 1100000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo2, "VDDQ_M12", 1200000, 1200000, 1, + REGULATOR_CHANGE_STATUS, 1);//sleep controlled by pwren +REGULATOR_INIT(ldo3, "VDDIOAP_18", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo4, "VDDQ_PRE", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); //sleep controlled by pwren + +REGULATOR_INIT(ldo5, "VDD18_2M", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo6, "VDD10_MPLL", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 1);//sleep controlled by pwren +REGULATOR_INIT(ldo7, "VDD10_XPLL", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 1);//sleep controlled by pwren +REGULATOR_INIT(ldo8, "VDD10_MIPI", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo9, "VDD33_LCD", 3300000, 3300000, 1, //LCD + REGULATOR_CHANGE_STATUS, 1); + + +REGULATOR_INIT(ldo10, "VDD18_MIPI", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo11, "VDD18_ABB1", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); //??? +REGULATOR_INIT(ldo12, "VDD33_UOTG", 3300000, 3300000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo13, "VDDIOPERI_18", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0);//??? +REGULATOR_INIT(ldo14, "VDD18_ABB02", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); //??? +REGULATOR_INIT(ldo15, "VDD10_USH", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 1); + +//liang, VDD18_HSIC must be 1.8V, otherwise USB HUB 3503A can't be recognized +REGULATOR_INIT(ldo16, "VDD18_HSIC", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo17, "VDDIOAP_MMC012_28", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 0); //??? +REGULATOR_INIT(ldo18, "VDDIOPERI_28", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 0);//??? +REGULATOR_INIT(ldo19, "DVDD25", 2500000, 2500000, 1, + REGULATOR_CHANGE_STATUS, 1); //?? +REGULATOR_INIT(ldo20, "VDD28_CAM", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(ldo21, "VDD28_AF", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo22, "VDDA28_2M", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo23, "VDD28_TF", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 1);//sleep controlled by pwren +REGULATOR_INIT(ldo24, "VDD33_A31", 3300000, 3300000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo25, "VDD18_CAM", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo26, "VDD18_A31", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo27, "GPS_1V8", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo28, "DVDD12", 1200000, 1200000, 1, + REGULATOR_CHANGE_STATUS, 1); + + +static struct regulator_init_data s5m8767_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 950000, + .max_uV = 1100000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck1_consumer, +}; + +static struct regulator_init_data s5m8767_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 925000, + .max_uV = 1300000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck2_consumer, +}; + +static struct regulator_init_data s5m8767_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 900000, + .max_uV = 1200000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1100000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck3_consumer, +}; + +static struct regulator_init_data s5m8767_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 750000, + .max_uV = 1500000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck4_consumer, +}; + +static struct regulator_init_data s5m8767_buck5_data = { + .constraints = { + .name = "vdd_m12 range", + .min_uV = 750000, + .max_uV = 1500000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck5_consumer, +}; +static struct regulator_init_data s5m8767_buck6_data = { + .constraints = { + .name = "vdd12_5m range", + .min_uV = 750000, + .max_uV = 1500000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck6_consumer, +}; + +static struct regulator_init_data s5m8767_buck9_data = { + .constraints = { + .name = "vddf28_emmc range", + .min_uV = 750000, + .max_uV = 3000000, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck9_consumer, +}; + +static struct sec_regulator_data origen_quad_regulators[] = { + { S5M8767_BUCK1, &s5m8767_buck1_data }, + { S5M8767_BUCK2, &s5m8767_buck2_data }, + { S5M8767_BUCK3, &s5m8767_buck3_data }, + { S5M8767_BUCK4, &s5m8767_buck4_data }, + { S5M8767_BUCK5, &s5m8767_buck5_data }, + { S5M8767_BUCK6, &s5m8767_buck6_data }, + { S5M8767_BUCK9, &s5m8767_buck9_data }, + + { S5M8767_LDO1, &s5m8767_ldo1_init_data }, + { S5M8767_LDO2, &s5m8767_ldo2_init_data }, + { S5M8767_LDO3, &s5m8767_ldo3_init_data }, + { S5M8767_LDO4, &s5m8767_ldo4_init_data }, + { S5M8767_LDO5, &s5m8767_ldo5_init_data }, + { S5M8767_LDO6, &s5m8767_ldo6_init_data }, + { S5M8767_LDO7, &s5m8767_ldo7_init_data }, + { S5M8767_LDO8, &s5m8767_ldo8_init_data }, + { S5M8767_LDO9, &s5m8767_ldo9_init_data }, + { S5M8767_LDO10, &s5m8767_ldo10_init_data }, + + { S5M8767_LDO11, &s5m8767_ldo11_init_data }, + { S5M8767_LDO12, &s5m8767_ldo12_init_data }, + { S5M8767_LDO13, &s5m8767_ldo13_init_data }, + { S5M8767_LDO14, &s5m8767_ldo14_init_data }, + { S5M8767_LDO15, &s5m8767_ldo15_init_data }, + { S5M8767_LDO16, &s5m8767_ldo16_init_data }, + { S5M8767_LDO17, &s5m8767_ldo17_init_data }, + { S5M8767_LDO18, &s5m8767_ldo18_init_data }, + { S5M8767_LDO19, &s5m8767_ldo19_init_data }, + { S5M8767_LDO20, &s5m8767_ldo20_init_data }, + + { S5M8767_LDO21, &s5m8767_ldo21_init_data }, + { S5M8767_LDO22, &s5m8767_ldo22_init_data }, + { S5M8767_LDO23, &s5m8767_ldo23_init_data }, + { S5M8767_LDO24, &s5m8767_ldo24_init_data }, + { S5M8767_LDO25, &s5m8767_ldo25_init_data }, + { S5M8767_LDO26, &s5m8767_ldo26_init_data }, + { S5M8767_LDO27, &s5m8767_ldo27_init_data }, + { S5M8767_LDO28, &s5m8767_ldo28_init_data }, +}; + +struct sec_opmode_data s5m_opmode_data[S5M8767_REG_MAX] = { + [S5M8767_BUCK1] = { S5M8767_BUCK1, SEC_OPMODE_ON}, + [S5M8767_BUCK2] = { S5M8767_BUCK2, SEC_OPMODE_ON}, + [S5M8767_BUCK3] = { S5M8767_BUCK3, SEC_OPMODE_ON}, + [S5M8767_BUCK4] = { S5M8767_BUCK4, SEC_OPMODE_ON}, + [S5M8767_BUCK5] = { S5M8767_BUCK5, SEC_OPMODE_ON}, + [S5M8767_BUCK6] = { S5M8767_BUCK6, SEC_OPMODE_ON}, + [S5M8767_BUCK9] = { S5M8767_BUCK9, SEC_OPMODE_ON}, + + [S5M8767_LDO1] = {S5M8767_LDO1, SEC_OPMODE_ON}, + [S5M8767_LDO2] = {S5M8767_LDO2, SEC_OPMODE_ON}, + [S5M8767_LDO3] = {S5M8767_LDO3, SEC_OPMODE_ON}, + [S5M8767_LDO4] = {S5M8767_LDO4, SEC_OPMODE_ON}, + [S5M8767_LDO5] = {S5M8767_LDO5, SEC_OPMODE_ON}, + [S5M8767_LDO6] = {S5M8767_LDO6, SEC_OPMODE_ON}, + [S5M8767_LDO7] = {S5M8767_LDO7, SEC_OPMODE_ON}, + [S5M8767_LDO8] = {S5M8767_LDO8, SEC_OPMODE_ON}, + [S5M8767_LDO9] = {S5M8767_LDO9, SEC_OPMODE_ON}, + [S5M8767_LDO10] = {S5M8767_LDO10, SEC_OPMODE_ON}, + + [S5M8767_LDO11] = {S5M8767_LDO11, SEC_OPMODE_ON}, + [S5M8767_LDO12] = {S5M8767_LDO12, SEC_OPMODE_ON}, + [S5M8767_LDO13] = {S5M8767_LDO13, SEC_OPMODE_ON}, + [S5M8767_LDO14] = {S5M8767_LDO14, SEC_OPMODE_ON}, + [S5M8767_LDO15] = {S5M8767_LDO15, SEC_OPMODE_ON}, + [S5M8767_LDO16] = {S5M8767_LDO16, SEC_OPMODE_ON}, + [S5M8767_LDO17] = {S5M8767_LDO17, SEC_OPMODE_ON}, + [S5M8767_LDO18] = {S5M8767_LDO18, SEC_OPMODE_ON}, + [S5M8767_LDO19] = {S5M8767_LDO19, SEC_OPMODE_ON}, + [S5M8767_LDO20] = {S5M8767_LDO20, SEC_OPMODE_ON}, + + [S5M8767_LDO21] = {S5M8767_LDO21, SEC_OPMODE_ON}, + [S5M8767_LDO22] = {S5M8767_LDO22, SEC_OPMODE_ON}, + [S5M8767_LDO23] = {S5M8767_LDO23, SEC_OPMODE_ON}, + [S5M8767_LDO24] = {S5M8767_LDO24, SEC_OPMODE_ON}, + [S5M8767_LDO25] = {S5M8767_LDO25, SEC_OPMODE_ON}, + [S5M8767_LDO26] = {S5M8767_LDO26, SEC_OPMODE_ON}, + [S5M8767_LDO27] = {S5M8767_LDO27, SEC_OPMODE_ON}, + [S5M8767_LDO28] = {S5M8767_LDO28, SEC_OPMODE_ON}, +}; + +static struct sec_platform_data origen_quad_s5m8767_pdata = { + .device_type = S5M8767X, + .num_regulators = ARRAY_SIZE(origen_quad_regulators), + .regulators = origen_quad_regulators, + .cfg_pmic_irq = s5m_cfg_irq, + .opmode = s5m_opmode_data, + + .buck2_gpiodvs = false, + .buck3_gpiodvs = false, + .buck4_gpiodvs = false, + + .buck2_voltage[0] = 1250000, + .buck2_voltage[1] = 1200000, + .buck2_voltage[2] = 1200000, + .buck2_voltage[3] = 1200000, + .buck2_voltage[4] = 1200000, + .buck2_voltage[5] = 1200000, + .buck2_voltage[6] = 1200000, + .buck2_voltage[7] = 1200000, + + .buck3_voltage[0] = 1100000, + .buck3_voltage[1] = 1100000, + .buck3_voltage[2] = 1100000, + .buck3_voltage[3] = 1100000, + .buck3_voltage[4] = 1100000, + .buck3_voltage[5] = 1100000, + .buck3_voltage[6] = 1100000, + .buck3_voltage[7] = 1100000, + + .buck4_voltage[0] = 1200000, + .buck4_voltage[1] = 1200000, + .buck4_voltage[2] = 1200000, + .buck4_voltage[3] = 1200000, + .buck4_voltage[4] = 1200000, + .buck4_voltage[5] = 1200000, + .buck4_voltage[6] = 1200000, + .buck4_voltage[7] = 1200000, + + .buck_default_idx = 3, + .buck_gpios[0] = EXYNOS4_GPX2(3), + .buck_gpios[1] = EXYNOS4_GPX2(4), + .buck_gpios[2] = EXYNOS4_GPX2(5), + + .buck_ds[0] = EXYNOS4_GPM3(5), + .buck_ds[1] = EXYNOS4_GPM3(6), + .buck_ds[2] = EXYNOS4_GPM3(7), + + .buck_ramp_delay = 50, + .buck2_ramp_enable = true, + .buck3_ramp_enable = true, + .buck4_ramp_enable = true, +}; +/* End of S5M8767 */ + +static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) +{ + int ret; + + if (power) + ret = gpio_request_one(EXYNOS4_GPX0(6), + GPIOF_OUT_INIT_HIGH, "GPX0_6"); + else + ret = gpio_request_one(EXYNOS4_GPX0(6), + GPIOF_OUT_INIT_LOW, "GPX0_6"); + + gpio_free(EXYNOS4_GPX0(6)); + + if (ret) + pr_err("failed to request gpio for LCD power: %d\n", ret); +} + +static struct plat_lcd_data origen_quad_lcd_hv070wsa_data = { + .set_power = lcd_hv070wsa_set_power, +}; + +static struct platform_device origen_quad_lcd_hv070wsa = { + .name = "platform-lcd", + .dev.parent = &s5p_device_fimd0.dev, + .dev.platform_data = &origen_quad_lcd_hv070wsa_data, +}; + +static struct pwm_lookup origen_quad_pwm_lookup[] = { + PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL), +}; + +#ifdef CONFIG_DRM_EXYNOS +static struct exynos_drm_fimd_pdata drm_fimd_pdata = { + .panel = { + .timing = { + .left_margin = 64, + .right_margin = 16, + .upper_margin = 64, + .lower_margin = 16, + .hsync_len = 48, + .vsync_len = 3, + .xres = 1024, + .yres = 600, + }, + }, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VCLK, + .default_win = 0, + .bpp = 32, +}; +#else +static struct s3c_fb_pd_win origen_quad_fb_win0 = { + .xres = 1024, + .yres = 600, + .max_bpp = 32, + .default_bpp = 24, + .virtual_x = 1024, + .virtual_y = 2 * 600, +}; + +static struct s3c_fb_pd_win origen_quad_fb_win1 = { + .xres = 1024, + .yres = 600, + .max_bpp = 32, + .default_bpp = 24, + .virtual_x = 1024, + .virtual_y = 2 * 600, +}; + +static struct s3c_fb_pd_win origen_quad_fb_win2 = { + .xres = 1024, + .yres = 600, + .max_bpp = 32, + .default_bpp = 24, + .virtual_x = 1024, + .virtual_y = 2 * 600, +}; + +static struct fb_videomode origen_quad_lcd_timing = { + .left_margin = 64, + .right_margin = 16, + .upper_margin = 64, + .lower_margin = 16, + .hsync_len = 48, + .vsync_len = 3, + .xres = 1024, + .yres = 600, +}; + +static struct s3c_fb_platdata origen_quad_lcd_pdata __initdata = { + .win[0] = &origen_quad_fb_win0, + .win[1] = &origen_quad_fb_win1, + .win[2] = &origen_quad_fb_win2, + .vtiming = &origen_quad_lcd_timing, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VCLK, + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, +}; +#endif + +static struct platform_device *origen_quad_devices[] __initdata = { + &s3c_device_wdt, + &s3c_device_rtc, + &s3c_device_hsmmc2, + &s3c_device_i2c0, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc3, + &s5p_device_fimc_md, + &s5p_device_fimd0, + &s5p_device_mfc, + &s5p_device_mfc_l, + &s5p_device_mfc_r, +#ifdef CONFIG_DRM_EXYNOS + &exynos_device_drm, +#endif + &origen_quad_lcd_hv070wsa, +}; + +/* LCD Backlight data */ +static struct samsung_bl_gpio_info origen_quad_bl_gpio_info = { + .no = EXYNOS4_GPD0(1), + .func = S3C_GPIO_SFN(2), +}; + +static struct platform_pwm_backlight_data origen_quad_bl_data = { + .pwm_id = 0, + .pwm_period_ns = 1000, +}; + +static void __init origen_quad_map_io(void) +{ + exynos_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); + s3c24xx_init_uarts(origen_quad_uartcfgs, ARRAY_SIZE(origen_quad_uartcfgs)); +} + +static void __init origen_quad_power_init(void) +{ + gpio_request(EXYNOS4_GPX2(6), "PMIC_IRQ"); + s3c_gpio_cfgpin(EXYNOS4_GPX2(6), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(EXYNOS4_GPX2(6), S3C_GPIO_PULL_UP); +} + +static struct i2c_board_info i2c0_devs[] __initdata = { + { + I2C_BOARD_INFO("sec_pmic", 0xCC >> 1), + .platform_data = &origen_quad_s5m8767_pdata, + .irq = IRQ_EINT(22), + }, +}; + +static void __init origen_quad_reserve(void) +{ + s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); +} + +static void __init origen_quad_machine_init(void) +{ + origen_quad_power_init(); + + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); + + s3c_sdhci2_set_platdata(&origen_quad_hsmmc2_pdata); + +#ifdef CONFIG_DRM_EXYNOS + s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; + exynos4_fimd0_gpio_setup_24bpp(); +#else + s5p_fimd0_set_platdata(&origen_quad_lcd_pdata); +#endif + pwm_add_table(origen_quad_pwm_lookup, ARRAY_SIZE(origen_quad_pwm_lookup)); + samsung_bl_set(&origen_quad_bl_gpio_info, &origen_quad_bl_data); + + platform_add_devices(origen_quad_devices, ARRAY_SIZE(origen_quad_devices)); +} + +MACHINE_START(ORIGEN_QUAD, "ORIGEN_QUAD") + .atag_offset = 0x100, + .init_irq = exynos4_init_irq, + .map_io = origen_quad_map_io, + .handle_irq = gic_handle_irq, + .init_machine = origen_quad_machine_init, + .init_late = exynos_init_late, + .timer = &exynos4_timer, + .reserve = &origen_quad_reserve, + .restart = exynos4_restart, + +MACHINE_END diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index c9d6650f9b5d..60c511f7e471 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -23,6 +23,7 @@ #include <asm/arch_timer.h> #include <asm/localtimer.h> +#include <asm/arch_timer.h> #include <plat/cpu.h> @@ -159,6 +160,10 @@ static void __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(0, 0); + if (soc_is_exynos5250()) { + mct_frc.rating = 399; + } + if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); } @@ -482,4 +487,7 @@ void __init exynos4_timer_init(void) exynos4_timer_resources(); exynos4_clocksource_init(); exynos4_clockevent_init(); + + if (arch_timer_of_register() != 0) + pr_err("Error registering architected timers\n"); } diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 51afedda9ab6..e1124d9fd2b0 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -1113,7 +1113,7 @@ struct platform_device s5p_device_onenand = { /* PMU */ -#ifdef CONFIG_PLAT_S5P +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS) static struct resource s5p_pmu_resource[] = { DEFINE_RES_IRQ(IRQ_PMU) }; diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 831e1fdfdb2f..3ff349fcd83a 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1204,3 +1204,4 @@ baileys MACH_BAILEYS BAILEYS 4169 familybox MACH_FAMILYBOX FAMILYBOX 4170 ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 +origen_quad MACH_ORIGEN_QUAD ORIGEN_QUAD 4200 diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index a5a3ebcbdd2c..7db71c5692c3 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -97,6 +97,28 @@ config SATA_AHCI_PLATFORM If unsure, say N. +config SATA_PHY + bool "SATA PHY Framework" + default n + help + This option enables the SATA PHY utility framework APIs. + The framework acts as an interface between the SATA device + and the PHY device. The SATA PHY device registers itself + with the framework through the APIs provided and the SATA + device finds and requests for an appropriate PHY device. + +config SATA_EXYNOS + bool "Exynos SATA AHCI support" + select I2C + select HAVE_S3C2410_I2C + select I2C_S3C2410 + select SATA_PHY + help + This option enables support for Exynos AHCI Serial ATA + controllers. + + If unsure, say N. + config SATA_FSL tristate "Freescale 3.0Gbps SATA support" depends on FSL_SOC diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index c04d0fd038a3..32d49edfade3 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -10,6 +10,8 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o obj-$(CONFIG_SATA_SIL24) += sata_sil24.o obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o +obj-$(CONFIG_SATA_PHY) += sata_phy.o +obj-$(CONFIG_SATA_EXYNOS) += sata_exynos.o sata_exynos_phy.o libahci.o # SFF w/ custom DMA obj-$(CONFIG_PDC_ADMA) += pdc_adma.o diff --git a/drivers/ata/sata_exynos.c b/drivers/ata/sata_exynos.c new file mode 100644 index 000000000000..01ec82e1b3c0 --- /dev/null +++ b/drivers/ata/sata_exynos.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SATA controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gfp.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/libata.h> +#include <linux/ahci_platform.h> +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/of.h> + +#include "ahci.h" +#include "sata_phy.h" + +#define MHZ (1000 * 1000) + +static const struct ata_port_info ahci_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, +}; + +static struct scsi_host_template ahci_platform_sht = { + AHCI_SHT("ahci_platform"), +}; + +struct exynos_sata { + struct clk *sclk; + struct clk *clk; + struct sata_phy *phy; + int irq; + unsigned int freq; +}; + +static void exynos_sata_parse_dt(struct device_node *np, + struct exynos_sata *sata) +{ + if (!np) + return; + + of_property_read_u32(np, "samsung,sata-freq", &sata->freq); +} + +static int exynos_sata_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_port_info pi = ahci_port_info; + const struct ata_port_info *ppi[] = { &pi, NULL }; + struct ahci_host_priv *hpriv; + struct exynos_sata *sata; + struct ata_host *host; + struct resource *mem; + int n_ports, i, ret; + + sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL); + if (!sata) { + dev_err(dev, "can't alloc sata\n"); + return -EINVAL; + } + + hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); + if (!hpriv) { + dev_err(dev, "can't alloc ahci_host_priv\n"); + ret = -ENOMEM; + goto err1; + } + + hpriv->flags |= (unsigned long)pi.private_data; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "no mmio space\n"); + ret = -EINVAL; + goto err2; + } + + sata->irq = platform_get_irq(pdev, 0); + if (sata->irq <= 0) { + dev_err(dev, "no irq\n"); + ret = -EINVAL; + goto err2; + } + + hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); + if (!hpriv->mmio) { + dev_err(dev, "can't map %pR\n", mem); + ret = -ENOMEM; + goto err2; + } + + exynos_sata_parse_dt(dev->of_node, sata); + + sata->sclk = devm_clk_get(dev, "sclk_sata"); + if (IS_ERR(sata->sclk)) { + dev_err(dev, "failed to get sclk_sata\n"); + ret = PTR_ERR(sata->sclk); + goto err3; + } + clk_enable(sata->sclk); + + clk_set_rate(sata->sclk, sata->freq * MHZ); + + sata->clk = devm_clk_get(dev, "sata"); + if (IS_ERR(sata->clk)) { + dev_err(dev, "failed to get sata clock\n"); + ret = PTR_ERR(sata->clk); + goto err4; + } + clk_enable(sata->clk); + + /* Get a gen 3 PHY controller */ + + sata->phy = sata_get_phy(SATA_PHY_GENERATION3); + if (!sata->phy) { + dev_err(dev, "failed to get sata phy\n"); + ret = -EPROBE_DEFER; + goto err5; + } + + /* Initialize the controller */ + + ret = sata_init_phy(sata->phy); + if (ret < 0) { + dev_err(dev, "failed to initialize sata phy\n"); + goto err6; + } + + ahci_save_initial_config(dev, hpriv, 0, 0); + + /* prepare host */ + if (hpriv->cap & HOST_CAP_NCQ) + pi.flags |= ATA_FLAG_NCQ; + + if (hpriv->cap & HOST_CAP_PMP) + pi.flags |= ATA_FLAG_PMP; + + ahci_set_em_messages(hpriv, &pi); + + /* CAP.NP sometimes indicate the index of the last enabled + * port, at other times, that of the last possible port, so + * determining the maximum port number requires looking at + * both CAP.NP and port_map. + */ + n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); + + host = ata_host_alloc_pinfo(dev, ppi, n_ports); + if (!host) { + ret = -ENOMEM; + goto err7; + } + + host->private_data = hpriv; + + if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) + host->flags |= ATA_HOST_PARALLEL_SCAN; + else + pr_info(KERN_INFO + "ahci: SSS flag set, parallel bus scan disabled\n"); + + if (pi.flags & ATA_FLAG_EM) + ahci_reset_em(host); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + + ata_port_desc(ap, "mmio %pR", mem); + ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); + + /* set enclosure management message type */ + if (ap->flags & ATA_FLAG_EM) + ap->em_message_type = hpriv->em_msg_type; + + /* disabled/not-implemented port */ + if (!(hpriv->port_map & (1 << i))) + ap->ops = &ata_dummy_port_ops; + } + + ret = ahci_reset_controller(host); + if (ret) + goto err7; + + ahci_init_controller(host); + ahci_print_info(host, "platform"); + + ret = ata_host_activate(host, sata->irq, ahci_interrupt, IRQF_SHARED, + &ahci_platform_sht); + if (ret) + goto err7; + + platform_set_drvdata(pdev, sata); + + return 0; + + err7: + sata_shutdown_phy(sata->phy); + + err6: + sata_put_phy(sata->phy); + + err5: + clk_disable(sata->clk); + devm_clk_put(dev, sata->clk); + + err4: + clk_disable(sata->sclk); + devm_clk_put(dev, sata->sclk); + + err3: + devm_iounmap(dev, hpriv->mmio); + + err2: + devm_kfree(dev, hpriv); + + err1: + devm_kfree(dev, sata); + + return ret; +} + +static int exynos_sata_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_host *host = dev_get_drvdata(dev); + struct exynos_sata *sata = platform_get_drvdata(pdev); + + ata_host_detach(host); + + sata_shutdown_phy(sata->phy); + sata_put_phy(sata->phy); + + return 0; +} + +static const struct of_device_id ahci_of_match[] = { + { .compatible = "samsung,exynos5-sata-ahci", }, +}; + +MODULE_DEVICE_TABLE(of, ahci_of_match); + +static struct platform_driver exynos_sata_driver = { + .probe = exynos_sata_probe, + .remove = exynos_sata_remove, + .driver = { + .name = "ahci-sata", + .owner = THIS_MODULE, + .of_match_table = ahci_of_match, + }, +}; + +module_platform_driver(exynos_sata_driver); + +MODULE_DESCRIPTION("EXYNOS SATA DRIVER"); +MODULE_AUTHOR("Vasanth Ananthan, <vasanth.a@samsung.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/ata/sata_exynos_phy.c b/drivers/ata/sata_exynos_phy.c new file mode 100644 index 000000000000..f001262255e6 --- /dev/null +++ b/drivers/ata/sata_exynos_phy.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SATA PHY controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/ahci_platform.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/list.h> +#include <linux/io.h> + +#include <plat/cpu.h> + +#include <mach/irqs.h> +#include <mach/map.h> +#include <mach/regs-pmu.h> +#include <mach/regs-sata.h> + +#include "sata_phy.h" + +#define SATA_TIME_LIMIT 1000 + +static struct i2c_client *i2c_client; + +static struct i2c_driver sataphy_i2c_driver; + +struct exynos_sata_phy { + void __iomem *mmio; + struct resource *mem; + struct clk *clk; +}; + +static bool sata_is_reg(void __iomem *base, u32 reg, u32 checkbit, u32 status) +{ + if ((readl(base + reg) & checkbit) == status) + return true; + else + return false; +} + +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit, + u32 status) +{ + u16 time_limit_cnt = 0; + while (!sata_is_reg(base, reg, checkbit, status)) { + if (time_limit_cnt == SATA_TIME_LIMIT) + return false; + udelay(1000); + time_limit_cnt++; + } + return true; +} + +static int sataphy_init(struct sata_phy *phy) +{ + int ret; + u32 val; + + /* Values to be written to enable 40 bits interface */ + u8 buf[] = { 0x3A, 0x0B }; + + struct exynos_sata_phy *sata_phy; + + if (!i2c_client) + return -EPROBE_DEFER; + + sata_phy = (struct exynos_sata_phy *)phy->priv_data; + + clk_enable(sata_phy->clk); + + if (sata_is_reg(sata_phy->mmio , EXYNOS5_SATA_CTRL0, + CTRL0_P0_PHY_CALIBRATED, CTRL0_P0_PHY_CALIBRATED)) + return 0; + + writel(S5P_PMU_SATA_PHY_CONTROL_EN, EXYNOS5_SATA_PHY_CONTROL); + + val = 0; + writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET); + + val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET); + val |= 0xFF; + writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET); + + val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET); + val |= LINK_RESET; + writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET); + + val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET); + val |= RESET_CMN_RST_N; + writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET); + + val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM); + val &= ~PHCTRLM_REF_RATE; + writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM); + + /* High speed enable for Gen3 */ + val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM); + val |= PHCTRLM_HIGH_SPEED; + writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM); + + val = readl(sata_phy->mmio + EXYNOS5_SATA_CTRL0); + val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED; + writel(val, sata_phy->mmio + EXYNOS5_SATA_CTRL0); + + writel(SATA_PHY_GENERATION3, sata_phy->mmio + EXYNOS5_SATA_MODE0); + + ret = i2c_master_send(i2c_client, buf, sizeof(buf)); + if (ret < 0) + return -EINVAL; + + /* release cmu reset */ + val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET); + val &= ~RESET_CMN_RST_N; + writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET); + + val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET); + val |= RESET_CMN_RST_N; + writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET); + + if (wait_for_reg_status(sata_phy->mmio, EXYNOS5_SATA_PHSATA_STATM, + PHSTATM_PLL_LOCKED, 1)) { + return 0; + } + return -EINVAL; +} + +static int sataphy_shutdown(struct sata_phy *phy) +{ + + struct exynos_sata_phy *sata_phy; + + sata_phy = (struct exynos_sata_phy *)phy->priv_data; + + clk_disable(sata_phy->clk); + + return 0; +} + +static int sata_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *i2c_id) +{ + i2c_client = client; + return 0; +} + +static int sata_phy_probe(struct platform_device *pdev) +{ + struct exynos_sata_phy *sataphy; + struct sata_phy *phy; + struct resource *res; + struct device *dev = &pdev->dev; + int ret = 0; + + phy = kzalloc(sizeof(struct sata_phy), GFP_KERNEL); + if (!phy) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + ret = -ENOMEM; + goto out; + } + + sataphy = kzalloc(sizeof(struct exynos_sata_phy), GFP_KERNEL); + if (!sataphy) { + dev_err(dev, "failed to allocate memory\n"); + ret = -ENOMEM; + goto err0; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Could not find IO resource\n"); + ret = -EINVAL; + goto err1; + } + + sataphy->mem = devm_request_mem_region(dev, res->start, + resource_size(res), pdev->name); + if (!sataphy->mem) { + dev_err(dev, "Could not request IO resource\n"); + ret = -EINVAL; + goto err1; + } + + sataphy->mmio = + devm_ioremap(dev, res->start, resource_size(res)); + if (!sataphy->mmio) { + dev_err(dev, "failed to remap IO\n"); + ret = -ENOMEM; + goto err2; + } + + sataphy->clk = devm_clk_get(dev, "sata-phy"); + if (IS_ERR(sataphy->clk)) { + dev_err(dev, "failed to get clk for PHY\n"); + ret = PTR_ERR(sataphy->clk); + goto err3; + } + + phy->init = sataphy_init; + phy->shutdown = sataphy_shutdown; + phy->priv_data = (void *)sataphy; + phy->dev = dev; + + ret = sata_add_phy(phy, SATA_PHY_GENERATION3); + if (ret < 0) + goto err4; + + ret = i2c_add_driver(&sataphy_i2c_driver); + if (ret < 0) + goto err5; + + platform_set_drvdata(pdev, phy); + + return ret; + + err5: + sata_remove_phy(phy); + + err4: + clk_disable(sataphy->clk); + devm_clk_put(dev, sataphy->clk); + + err3: + devm_iounmap(dev, sataphy->mmio); + + err2: + devm_release_mem_region(dev, res->start, resource_size(res)); + + err1: + kfree(sataphy); + + err0: + kfree(phy); + + out: + return ret; +} + +static int sata_phy_remove(struct platform_device *pdev) +{ + struct sata_phy *phy; + struct exynos_sata_phy *sataphy; + + phy = platform_get_drvdata(pdev); + + sataphy = (struct exynos_sata_phy *)phy->priv_data; + sata_remove_phy(phy); + + kfree(sataphy); + kfree(phy); + + return 0; +} + +static const struct of_device_id sata_phy_of_match[] = { + { .compatible = "samsung,exynos5-sata-phy", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, sata_phy_of_match); + +static const struct i2c_device_id phy_i2c_device_match[] = { + { "sata-phy", 0 }, +}; + +MODULE_DEVICE_TABLE(of, phy_i2c_device_match); + +static struct platform_driver sata_phy_driver = { + .probe = sata_phy_probe, + .remove = sata_phy_remove, + .driver = { + .name = "sata-phy", + .owner = THIS_MODULE, + .of_match_table = sata_phy_of_match, + }, +}; + +static struct i2c_driver sataphy_i2c_driver = { + .driver = { + .name = "sata-phy-i2c", + .owner = THIS_MODULE, + .of_match_table = phy_i2c_device_match, + }, + .probe = sata_i2c_probe, + .id_table = phy_i2c_device_match, +}; + +module_platform_driver(sata_phy_driver); + +MODULE_DESCRIPTION("EXYNOS SATA PHY DRIVER"); +MODULE_AUTHOR("Vasanth Ananthan, <vasanth.a@samsung.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/ata/sata_phy.c b/drivers/ata/sata_phy.c new file mode 100644 index 000000000000..e5631a97951f --- /dev/null +++ b/drivers/ata/sata_phy.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SATA utility framework. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/export.h> +#include <linux/err.h> +#include <linux/device.h> +#include <linux/slab.h> +#include <linux/list.h> +#include "sata_phy.h" + +static LIST_HEAD(phy_list); +static DEFINE_SPINLOCK(phy_lock); + +struct sata_phy *sata_get_phy(enum sata_phy_type type) +{ + struct sata_phy *x = NULL; + unsigned long flag; + + if (list_empty(&phy_list)) + return x; + + spin_lock_irqsave(&phy_lock, flag); + + list_for_each_entry(x, &phy_list, head) { + if (x->type == type) { + get_device(x->dev); + break; + } + } + + spin_unlock_irqrestore(&phy_lock, flag); + return x; +} +EXPORT_SYMBOL(sata_get_phy); + +int sata_add_phy(struct sata_phy *phy, enum sata_phy_type type) +{ + unsigned long flag; + unsigned int ret = -EINVAL; + struct sata_phy *x; + + spin_lock_irqsave(&phy_lock, flag); + + if (!phy) + return ret; + + list_for_each_entry(x, &phy_list, head) { + if (x->type == type) { + dev_err(phy->dev, "transceiver type already exists\n"); + goto out; + } + } + phy->type = type; + list_add_tail(&phy->head, &phy_list); + ret = 0; + + out: + spin_unlock_irqrestore(&phy_lock, flag); + return ret; +} +EXPORT_SYMBOL(sata_add_phy); + +void sata_remove_phy(struct sata_phy *phy) +{ + unsigned long flag; + struct sata_phy *x; + + spin_lock_irqsave(&phy_lock, flag); + + if (!phy) + return; + + list_for_each_entry(x, &phy_list, head) { + if (x->type == phy->type) + list_del(&phy->head); + } + + spin_unlock_irqrestore(&phy_lock, flag); +} +EXPORT_SYMBOL(sata_remove_phy); + +void sata_put_phy(struct sata_phy *phy) +{ + unsigned long flag; + + spin_lock_irqsave(&phy_lock, flag); + + if (!phy) + return; + + put_device(phy->dev); + spin_unlock_irqrestore(&phy_lock, flag); + +} +EXPORT_SYMBOL(sata_put_phy); diff --git a/drivers/ata/sata_phy.h b/drivers/ata/sata_phy.h new file mode 100644 index 000000000000..dc38683052e3 --- /dev/null +++ b/drivers/ata/sata_phy.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SATA utility framework definitions. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +enum sata_phy_type { + SATA_PHY_GENERATION1, + SATA_PHY_GENERATION2, + SATA_PHY_GENERATION3, +}; + +struct sata_phy { + int (*init) (struct sata_phy *); + int (*shutdown) (struct sata_phy *); + struct device *dev; + void *priv_data; + enum sata_phy_type type; + struct list_head head; +}; + +static inline int sata_init_phy(struct sata_phy *x) +{ + if (x && x->init) + return x->init(x); + + return -EINVAL; +} + +static inline void sata_shutdown_phy(struct sata_phy *x) +{ + if (x && x->shutdown) + x->shutdown(x); +} + +struct sata_phy *sata_get_phy(enum sata_phy_type); +int sata_add_phy(struct sata_phy *, enum sata_phy_type); +void sata_remove_phy(struct sata_phy *); +void sata_put_phy(struct sata_phy *); diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index d7ad425ab9b3..a65a710f9985 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -248,14 +248,16 @@ static void __cpuinit arch_timer_stop(struct clock_event_device *clk) static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu) { - struct clock_event_device *evt = this_cpu_ptr(arch_timer_evt); - + /* + * Grab cpu pointer in each case to avoid spurious + * preemptible warnings + */ switch (action & ~CPU_TASKS_FROZEN) { case CPU_STARTING: - arch_timer_setup(evt); + arch_timer_setup(this_cpu_ptr(arch_timer_evt)); break; case CPU_DYING: - arch_timer_stop(evt); + arch_timer_stop(this_cpu_ptr(arch_timer_evt)); break; } diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c index 78057a357ddb..64e872fe7b74 100644 --- a/drivers/cpufreq/exynos-cpufreq.c +++ b/drivers/cpufreq/exynos-cpufreq.c @@ -17,6 +17,8 @@ #include <linux/regulator/consumer.h> #include <linux/cpufreq.h> #include <linux/suspend.h> +#include <linux/notifier.h> +#include <linux/reboot.h> #include <plat/cpu.h> @@ -242,8 +244,35 @@ static struct notifier_block exynos_cpufreq_nb = { .notifier_call = exynos_cpufreq_pm_notifier, }; +static int exynos_cpufreq_reboot_notifier(struct notifier_block *this, + unsigned long code, void *_cmd) +{ + struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */ + mutex_lock(&cpufreq_lock); + + if (frequency_locked) + goto out; + frequency_locked = true; + + if (locking_frequency) { + mutex_unlock(&cpufreq_lock); + exynos_target(policy, locking_frequency, CPUFREQ_RELATION_H); + mutex_lock(&cpufreq_lock); + } + +out: + mutex_unlock(&cpufreq_lock); + return NOTIFY_DONE; +} + +static struct notifier_block exynos_cpufreq_reboot_nb = { + .notifier_call = exynos_cpufreq_reboot_notifier, +}; + static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) { + int ret; + policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu); cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu); @@ -253,7 +282,13 @@ static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) cpumask_setall(policy->cpus); - return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table); + ret = cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table); + if (ret) + return ret; + + cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu); + return 0; + } static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy) @@ -316,6 +351,7 @@ static int __init exynos_cpufreq_init(void) locking_frequency = exynos_getspeed(0); register_pm_notifier(&exynos_cpufreq_nb); + register_reboot_notifier(&exynos_cpufreq_reboot_nb); if (cpufreq_register_driver(&exynos_driver)) { pr_err("%s: failed to register cpufreq driver\n", __func__); diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 3da5c2d214d8..8010f70d7c93 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -294,7 +294,7 @@ static int exynos_drm_platform_probe(struct platform_device *pdev) { DRM_DEBUG_DRIVER("%s\n", __FILE__); - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); exynos_drm_driver.num_ioctls = DRM_ARRAY_SIZE(exynos_ioctls); return drm_platform_init(&exynos_drm_driver, pdev); diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 2c5f266154ad..730f31ef0a4e 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1996,7 +1996,7 @@ static irqreturn_t hdmi_irq_thread(int irq, void *arg) struct hdmi_context *hdata = ctx->ctx; mutex_lock(&hdata->hdmi_mutex); - hdata->hpd = gpio_get_value(hdata->hpd_gpio); + hdata->hpd = true; mutex_unlock(&hdata->hdmi_mutex); if (ctx->drm_dev) @@ -2340,7 +2340,7 @@ static int hdmi_resume(struct device *dev) DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); - hdata->hpd = gpio_get_value(hdata->hpd_gpio); + hdata->hpd = true; enable_irq(hdata->irq); diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index f6b880ba1932..580199c24107 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -49,6 +49,7 @@ #define QUIRK_S3C2440 (1 << 0) #define QUIRK_HDMIPHY (1 << 1) #define QUIRK_NO_GPIO (1 << 2) +#define QUIRK_SATAPHY (1 << 3) /* Max time to wait for bus to become idle after a xfer (in us) */ #define S3C2410_IDLE_TIMEOUT 5000 @@ -105,10 +106,14 @@ static struct platform_device_id s3c24xx_driver_ids[] = { }; MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); +static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); + #ifdef CONFIG_OF static const struct of_device_id s3c24xx_i2c_match[] = { { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, + { .compatible = "samsung,exynos5-sata-phy-i2c", + .data = (void *)(QUIRK_S3C2440 | QUIRK_SATAPHY | QUIRK_NO_GPIO) }, { .compatible = "samsung,s3c2440-hdmiphy-i2c", .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, { .compatible = "samsung,exynos5440-i2c", @@ -151,7 +156,8 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) if (ret) i2c->msg_idx = ret; - wake_up(&i2c->wait); + if (!(i2c->quirks & QUIRK_SATAPHY)) + wake_up(&i2c->wait); } static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) @@ -189,6 +195,23 @@ static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) } +static bool is_ack(struct s3c24xx_i2c *i2c) +{ + u32 time_out = i2c->tx_setup; + + while (--time_out) { + if (readl(i2c->regs + S3C2410_IICCON) + & S3C2410_IICCON_IRQPEND) { + if (!(readl(i2c->regs + S3C2410_IICSTAT) + & S3C2410_IICSTAT_LASTBIT)) + return true; + } + udelay(time_out); + } + + return false; +} + /* s3c24xx_i2c_message_start * * put the start of a message onto the bus @@ -232,6 +255,15 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, stat |= S3C2410_IICSTAT_START; writel(stat, i2c->regs + S3C2410_IICSTAT); + + if (i2c->quirks & QUIRK_SATAPHY) { + while ((i2c->msg_num != 0) && is_ack(i2c)) { + i2c_s3c_irq_nextbyte(i2c, stat); + stat = readl(i2c->regs + S3C2410_IICSTAT); + if (stat & S3C2410_IICSTAT_ARBITR) + dev_err(i2c->dev, "deal with arbitration loss\n"); + } + } } static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) @@ -630,21 +662,25 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, s3c24xx_i2c_enable_irq(i2c); s3c24xx_i2c_message_start(i2c, msgs); - timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); - - ret = i2c->msg_idx; + if (!(i2c->quirks & QUIRK_SATAPHY)) { - /* having these next two as dev_err() makes life very - * noisy when doing an i2cdetect */ + timeout = wait_event_timeout(i2c->wait, + i2c->msg_num == 0, HZ * 5); - if (timeout == 0) - dev_dbg(i2c->dev, "timeout\n"); - else if (ret != num) - dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); + ret = i2c->msg_idx; - /* For QUIRK_HDMIPHY, bus is already disabled */ - if (i2c->quirks & QUIRK_HDMIPHY) - goto out; + /* having these next two as dev_err() makes life very + * noisy when doing an i2cdetect + */ + if (timeout == 0) + dev_dbg(i2c->dev, "timeout\n"); + else if (ret != num) + dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); + + /* For QUIRK_HDMIPHY, bus is already disabled */ + if (i2c->quirks & QUIRK_HDMIPHY) + goto out; + } s3c24xx_i2c_wait_idle(i2c); @@ -775,6 +811,9 @@ static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) if (div1 == 512) iiccon |= S3C2410_IICCON_TXDIV_512; + if (i2c->quirks & QUIRK_SATAPHY) + iiccon |= S3C2410_IICCON_SCALE(2); + writel(iiccon, i2c->regs + S3C2410_IICCON); if (i2c->quirks & QUIRK_S3C2440) { @@ -1077,18 +1116,20 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev) * ensure no current IRQs pending */ - i2c->irq = ret = platform_get_irq(pdev, 0); - if (ret <= 0) { - dev_err(&pdev->dev, "cannot find IRQ\n"); - return ret; - } + if (!(i2c->quirks & QUIRK_SATAPHY)) { + i2c->irq = ret = platform_get_irq(pdev, 0); + if (ret <= 0) { + dev_err(&pdev->dev, "cannot find IRQ\n"); + return ret; + } - ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, - dev_name(&pdev->dev), i2c); + ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, + dev_name(&pdev->dev), i2c); - if (ret != 0) { - dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); - return ret; + if (ret != 0) { + dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); + return ret; + } } ret = s3c24xx_i2c_register_cpufreq(i2c); diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index b357c98ddc2c..fffc88069614 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -32,6 +32,7 @@ struct combiner_chip_data { unsigned int irq_offset; unsigned int irq_mask; void __iomem *base; + unsigned int parent_irq; }; static struct irq_domain *combiner_irq_domain; @@ -88,10 +89,28 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } +#ifdef CONFIG_SMP +static int combiner_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d); + struct irq_chip *chip = irq_get_chip(chip_data->parent_irq); + struct irq_data *data = irq_get_irq_data(chip_data->parent_irq); + + if (chip && chip->irq_set_affinity) + return chip->irq_set_affinity(data, mask_val, force); + else + return -EINVAL; +} +#endif + static struct irq_chip combiner_chip = { .name = "COMBINER", .irq_mask = combiner_mask_irq, .irq_unmask = combiner_unmask_irq, +#ifdef CONFIG_SMP + .irq_set_affinity = combiner_set_affinity, +#endif }; static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) @@ -111,12 +130,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i } static void __init combiner_init_one(unsigned int combiner_nr, - void __iomem *base) + void __iomem *base, unsigned int irq) { combiner_data[combiner_nr].base = base; combiner_data[combiner_nr].irq_offset = irq_find_mapping( combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); + combiner_data[combiner_nr].parent_irq = irq; /* Disable all interrupts */ __raw_writel(combiner_data[combiner_nr].irq_mask, @@ -200,12 +220,13 @@ void __init combiner_init(void __iomem *combiner_base, } for (i = 0; i < max_nr; i++) { - combiner_init_one(i, combiner_base + (i >> 2) * 0x10); + //combiner_init_one(i, combiner_base + (i >> 2) * 0x10); irq = IRQ_SPI(i); #ifdef CONFIG_OF if (np) irq = irq_of_parse_and_map(np, i); #endif + combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq); combiner_cascade_irq(i, irq); } } diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c index 4582473978ca..fb422a7d71a9 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c @@ -196,6 +196,16 @@ static struct mfc_control controls[] = { .default_value = 1, .is_volatile = 1, }, + { + .id = V4L2_CID_CODEC_FRAME_TAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame Tag", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + .is_volatile = 1, + }, }; #define NUM_CTRLS ARRAY_SIZE(controls) @@ -724,6 +734,9 @@ static int s5p_mfc_dec_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE: ctx->slice_interface = ctrl->val; break; + case V4L2_CID_CODEC_FRAME_TAG: + ctx->frame_tag = ctrl->val; + break; default: mfc_err("Invalid control 0x%08x\n", ctrl->id); return -EINVAL; @@ -758,6 +771,9 @@ static int s5p_mfc_dec_g_v_ctrl(struct v4l2_ctrl *ctrl) return -EINVAL; } break; + case V4L2_CID_CODEC_FRAME_TAG: + ctrl->val = s5p_mfc_hw_call(dev->mfc_ops, get_frame_tag, ctx); + break; } return 0; } diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h index 754c540e7a7e..498ff09a8158 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h @@ -77,6 +77,7 @@ struct s5p_mfc_hw_ops { unsigned int (*get_pic_type_bot)(struct s5p_mfc_ctx *ctx); unsigned int (*get_crop_info_h)(struct s5p_mfc_ctx *ctx); unsigned int (*get_crop_info_v)(struct s5p_mfc_ctx *ctx); + unsigned int (*get_frame_tag)(struct s5p_mfc_ctx *ctx); }; void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c index f61dba837899..6e3a33b6cb3c 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c @@ -1074,6 +1074,9 @@ static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL); + + s5p_mfc_write_info_v5(ctx, ctx->frame_tag, + S5P_FIMV_SHARED_SET_FRAME_TAG); } /* Decode a single frame */ @@ -1672,6 +1675,11 @@ unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx) return s5p_mfc_read_info_v5(ctx, CROP_INFO_V); } +unsigned int s5p_mfc_get_frame_tag(struct s5p_mfc_ctx *ctx) +{ + return s5p_mfc_read_info_v5(ctx, GET_FRAME_TAG_TOP); +} + /* Initialize opr function pointers for MFC v5 */ static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = { .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5, @@ -1725,6 +1733,7 @@ static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = { .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5, .get_crop_info_h = s5p_mfc_get_crop_info_h_v5, .get_crop_info_v = s5p_mfc_get_crop_info_v_v5, + .get_frame_tag = s5p_mfc_get_frame_tag, }; struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void) diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 6b28b5800500..820a6eacd6c7 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -695,6 +695,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_DEC_PTS: return "Video Decoder PTS"; case V4L2_CID_MPEG_VIDEO_DEC_FRAME: return "Video Decoder Frame Count"; case V4L2_CID_MPEG_VIDEO_VBV_DELAY: return "Initial Delay for VBV Control"; + case V4L2_CID_CODEC_FRAME_TAG: return "Video Decoder Frame Tag"; /* CAMERA controls */ /* Keep the order of the 'case's the same as in videodev2.h! */ @@ -962,6 +963,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, *flags |= V4L2_CTRL_FLAG_READ_ONLY; *min = *max = *step = *def = 0; break; + case V4L2_CID_CODEC_FRAME_TAG: + *type = V4L2_CTRL_TYPE_INTEGER; + *step = 1; + *min = 0; + *max = INT_MAX; + break; default: *type = V4L2_CTRL_TYPE_INTEGER; break; diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 72fd0f2c9013..ebe7417d712a 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -16,6 +16,7 @@ #include <linux/mmc/dw_mmc.h> #include <linux/of.h> #include <linux/of_gpio.h> +#include <linux/dma-mapping.h> #include "dw_mmc.h" #include "dw_mmc-pltfm.h" @@ -222,6 +223,8 @@ int dw_mci_exynos_probe(struct platform_device *pdev) match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); drv_data = match->data; + /* set the dma coherent mask */ + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); return dw_mci_pltfm_register(pdev, drv_data); } diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 41c27b74b003..5b6d9e22a9c5 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -21,6 +21,7 @@ #include <linux/mmc/mmc.h> #include <linux/mmc/dw_mmc.h> #include <linux/of.h> +#include <linux/dma-mapping.h> #include "dw_mmc.h" @@ -65,6 +66,8 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_register); static int dw_mci_pltfm_probe(struct platform_device *pdev) { + /* set the coherent dma_mask */ + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); return dw_mci_pltfm_register(pdev, NULL); } diff --git a/drivers/net/ethernet/8390/ax88796.c b/drivers/net/ethernet/8390/ax88796.c index cab306a9888e..230763da8b17 100644 --- a/drivers/net/ethernet/8390/ax88796.c +++ b/drivers/net/ethernet/8390/ax88796.c @@ -828,7 +828,14 @@ static int ax_probe(struct platform_device *pdev) struct ei_device *ei_local; struct ax_device *ax; struct resource *irq, *mem, *mem2; +#ifndef CONFIG_ARM_LPAE + /* LPAE breaks this code as __aeabi_uldivmod for 64-bit + * is not supported in lib1funcs.s yet + */ resource_size_t mem_size, mem2_size = 0; +#else + u32 mem_size, mem2_size = 0; +#endif int ret = 0; dev = ax__alloc_ei_netdev(sizeof(struct ax_device)); diff --git a/drivers/net/usb/asix_devices.c b/drivers/net/usb/asix_devices.c index 709753469099..1f6feec0e75e 100644 --- a/drivers/net/usb/asix_devices.c +++ b/drivers/net/usb/asix_devices.c @@ -44,6 +44,35 @@ struct ax88172_int_data { __le16 res3; } __packed; +static char asix_mac_addr[6]; +static int __init asix_setup_mac(char *macstr) +{ + int i, h, l; + + if (!macstr) + return 0; + + for (i = 0; i < 6; i++) { + if (i != 5 && *(macstr + 2) != ':') + return 0; + + h = hex_to_bin(*macstr++); + if (h == -1) + return 0; + + l = hex_to_bin(*macstr++); + if (l == -1) + return 0; + + macstr++; + asix_mac_addr[i] = (h << 4) + l; + } + + return 0; +} + +__setup("mac=", asix_setup_mac); + static void asix_status(struct usbnet *dev, struct urb *urb) { struct ax88172_int_data *event; @@ -66,6 +95,9 @@ static void asix_status(struct usbnet *dev, struct urb *urb) static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) { + if (!is_valid_ether_addr(addr)) + memcpy(addr, asix_mac_addr, ETH_ALEN); + if (is_valid_ether_addr(addr)) { memcpy(dev->net->dev_addr, addr, ETH_ALEN); } else { diff --git a/drivers/of/platform.c b/drivers/of/platform.c index e0a6514ab46c..360c6b9e8ebe 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -214,7 +214,7 @@ struct platform_device *of_platform_device_create_pdata( #if defined(CONFIG_MICROBLAZE) dev->archdata.dma_mask = 0xffffffffUL; #endif - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + dev->dev.coherent_dma_mask = DMA_BIT_MASK(64); dev->dev.bus = &platform_bus_type; dev->dev.platform_data = platform_data; diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 2769a38d15b6..fb4ebae095d9 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -524,6 +524,28 @@ static int s3c64xx_serial_startup(struct uart_port *port) return ret; } +static void s3c64xx_serial_shutdown(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + + if (ourport->tx_claimed) { + free_irq(port->irq, ourport); + tx_enabled(port) = 0; + ourport->tx_claimed = 0; + } + + if (ourport->rx_claimed) { + ourport->rx_claimed = 0; + rx_enabled(port) = 0; + } + + /* Clear pending interrupts and mask all interrupts */ + if (s3c24xx_serial_has_interrupt_mask(port)) { + wr_regl(port, S3C64XX_UINTP, 0xf); + wr_regl(port, S3C64XX_UINTM, 0xf); + } +} + /* power power management control */ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, @@ -1009,6 +1031,9 @@ static void s3c24xx_serial_resetport(struct uart_port *port, wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); wr_regl(port, S3C2410_UFCON, cfg->ufcon); + wr_regl(port, S3C64XX_UINTM, 0xf); + wr_regl(port, S3C64XX_UINTP, 0xf); + /* some delay is required after fifo reset */ udelay(1); } @@ -1121,8 +1146,10 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, port->dev = &platdev->dev; /* Startup sequence is different for s3c64xx and higher SoC's */ - if (s3c24xx_serial_has_interrupt_mask(port)) + if (s3c24xx_serial_has_interrupt_mask(port)) { s3c24xx_serial_ops.startup = s3c64xx_serial_startup; + s3c24xx_serial_ops.shutdown = s3c64xx_serial_shutdown; + } port->uartclk = 1; diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 640ae6c6d2d2..f39c215371b7 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -54,6 +54,7 @@ config USB_ARCH_HAS_EHCI # some non-PCI HCDs implement xHCI config USB_ARCH_HAS_XHCI boolean + default y if ARCH_EXYNOS5 default PCI menuconfig USB_SUPPORT diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 8f5ebced5df0..3cc766d4276c 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -6,6 +6,8 @@ obj-$(CONFIG_USB) += core/ +obj-$(CONFIG_USB_COMMON) += phy/ + obj-$(CONFIG_USB_OTG_UTILS) += otg/ obj-$(CONFIG_USB_DWC3) += dwc3/ diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index ffa6b004a84b..924cf3e836e2 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -447,6 +447,8 @@ static int dwc3_probe(struct platform_device *pdev) dwc->regs = regs; dwc->regs_size = resource_size(res); dwc->dev = dev; + /* set the dma coherent mask */ + dwc->dev->coherent_dma_mask = DMA_BIT_MASK(64); if (!strncmp("super", maximum_speed, 5)) dwc->maximum_speed = DWC3_DCFG_SUPERSPEED; @@ -480,7 +482,9 @@ static int dwc3_probe(struct platform_device *pdev) goto err0; } - mode = DWC3_MODE(dwc->hwparams.hwparams0); + //mode = DWC3_MODE(dwc->hwparams.hwparams0); + /* Putting controller in Host mode here */ + mode = DWC3_MODE_HOST; /* Just a hack for time being */ switch (mode) { case DWC3_MODE_DEVICE: diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index b082bec7343e..d560b53f955c 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -102,6 +102,13 @@ static int dwc3_exynos_probe(struct platform_device *pdev) dev_err(dev, "not enough memory\n"); return -ENOMEM; } + /* + * Right now device-tree probed devices don't get dma_mask set. + * Since shared usb code relies on it, set it here for now. + * Once we move to full device tree support this will vanish off. + */ + if (!pdev->dev.dma_mask) + pdev->dev.dma_mask = &dwc3_exynos_dma_mask; /* * Right now device-tree probed devices don't get dma_mask set. diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c index 20ebf6a8b7f4..a93ab9903ada 100644 --- a/drivers/usb/host/ehci-s5p.c +++ b/drivers/usb/host/ehci-s5p.c @@ -90,6 +90,26 @@ static void s5p_ehci_phy_disable(struct s5p_ehci_hcd *s5p_ehci) s5p_ehci->pdata->phy_exit(pdev, USB_PHY_TYPE_HOST); } +static void s5p_setup_hub_gpio(struct platform_device *pdev, const char *propname, int level) +{ + int err; + int gpio; + + if (!pdev->dev.of_node) + return; + + gpio = of_get_named_gpio(pdev->dev.of_node, propname, 0); + if (!gpio_is_valid(gpio)) + return; + + err = gpio_request_one(gpio, level, "ehci_vbus_gpio"); + + if (err) + dev_err(&pdev->dev, "can't request ehci hub-reset gpio %d", gpio); + else + gpio_free(gpio); +} + static void s5p_setup_vbus_gpio(struct platform_device *pdev) { int err; @@ -200,8 +220,15 @@ static int s5p_ehci_probe(struct platform_device *pdev) if (s5p_ehci->otg) s5p_ehci->otg->set_host(s5p_ehci->otg, &s5p_ehci->hcd->self); + s5p_setup_hub_gpio(pdev, "samsung,hub-reset", GPIOF_OUT_INIT_LOW); + s5p_setup_hub_gpio(pdev, "samsung,hub-connect", GPIOF_OUT_INIT_LOW); + s5p_ehci_phy_enable(s5p_ehci); + mdelay(1); + s5p_setup_hub_gpio(pdev, "samsung,hub-reset", GPIOF_OUT_INIT_HIGH); + s5p_setup_hub_gpio(pdev, "samsung,hub-connect", GPIOF_OUT_INIT_HIGH); + ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs; diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index 967101ec15fd..e6afc4102341 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -158,6 +158,99 @@ #define EXYNOS5_PHY_OTG_TUNE (0x40) +/* USB 3.0: DRD */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL (1 << 27) + +#define EXYNOS5_DRD_PHYUTMI (0x08) + +#define PHYUTMI_OTGDISABLE (1 << 6) +#define PHYUTMI_FORCESUSPEND (1 << 1) +#define PHYUTMI_FORCESLEEP (1 << 0) + +#define EXYNOS5_DRD_PHYPIPE (0x0C) + +#define EXYNOS5_DRD_PHYCLKRST (0x10) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define PHYCLKRST_SSC_EN (1 << 20) +#define PHYCLKRST_REF_SSP_EN (1 << 19) +#define PHYCLKRST_REF_CLKDIV2 (1 << 18) + +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define PHYCLKRST_MPLL_MULTIPLIER(_x) ((_x) << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF \ + PHYCLKRST_MPLL_MULTIPLIER(0x19) +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF \ + PHYCLKRST_MPLL_MULTIPLIER(0x02) +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF \ + PHYCLKRST_MPLL_MULTIPLIER(0x68) +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF \ + PHYCLKRST_MPLL_MULTIPLIER(0x7d) +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF \ + PHYCLKRST_MPLL_MULTIPLIER(0x02) + +#define PHYCLKRST_FSEL_MASK (0x3f << 5) +#define PHYCLKRST_FSEL(_x) ((_x) << 5) +#define PHYCLKRST_FSEL_PAD_100MHZ \ + PHYCLKRST_FSEL(0x27) +#define PHYCLKRST_FSEL_PAD_24MHZ \ + PHYCLKRST_FSEL(0x2a) +#define PHYCLKRST_FSEL_PAD_20MHZ \ ++ PHYCLKRST_FSEL(0x31) +#define PHYCLKRST_FSEL_PAD_19_2MHZ \ + PHYCLKRST_FSEL(0x38) + +#define PHYCLKRST_RETENABLEN (1 << 4) + +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define PHYCLKRST_REFCLKSEL(_x) ((_x) << 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK \ + PHYCLKRST_REFCLKSEL(2) +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK \ + PHYCLKRST_REFCLKSEL(3) + +#define PHYCLKRST_PORTRESET (1 << 1) +#define PHYCLKRST_COMMONONN (1 << 0) + +#define EXYNOS5_DRD_PHYREG0 (0x14) +#define EXYNOS5_DRD_PHYREG1 (0x18) + +#define EXYNOS5_DRD_PHYPARAM0 (0x1C) + +#define PHYPARAM0_REF_USE_PAD (0x1 << 31) +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) + +#define EXYNOS5_DRD_PHYPARAM1 (0x20) + +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) +#define PHYPARAM1_PCS_TXDEEMPH (0x1C) + +#define EXYNOS5_DRD_PHYTERM (0x24) + +#define EXYNOS5_DRD_PHYTEST (0x28) + +#define PHYTEST_POWERDOWN_SSP (1 << 3) +#define PHYTEST_POWERDOWN_HSP (1 << 2) + +#define EXYNOS5_DRD_PHYADP (0x2C) + +#define EXYNOS5_DRD_PHYBATCHG (0x30) + +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) + +#define EXYNOS5_DRD_PHYRESUME (0x34) +#define EXYNOS5_DRD_LINKPORT (0x44) + #ifndef MHZ #define MHZ (1000*1000) #endif @@ -206,10 +299,12 @@ struct samsung_usbphy_drvdata { /* * struct samsung_usbphy - transceiver driver state * @phy: transceiver structure + * @phy3: transceiver structure for USB 3.0 * @plat: platform data * @dev: The parent device supplied to the probe function * @clk: usb phy clock * @regs: usb phy controller registers memory base + * @regs_phy3: usb 3.0 phy register memory base * @pmuregs: USB device PHY_CONTROL register memory base * @sysreg: USB2.0 PHY_CFG register memory base * @ref_clk_freq: reference clock frequency selection @@ -221,10 +316,12 @@ struct samsung_usbphy_drvdata { */ struct samsung_usbphy { struct usb_phy phy; + struct usb_phy phy3; struct samsung_usbphy_data *plat; struct device *dev; struct clk *clk; void __iomem *regs; + void __iomem *regs_phy3; void __iomem *pmuregs; void __iomem *sysreg; int ref_clk_freq; @@ -235,6 +332,7 @@ struct samsung_usbphy { }; #define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy) +#define phy3_to_sphy(x) container_of((x), struct samsung_usbphy, phy3) int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host) { @@ -753,6 +851,209 @@ static void samsung_usbphy_shutdown(struct usb_phy *phy) clk_disable_unprepare(sphy->clk); } + /* + * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock form clock core. + */ +static u32 exynos5_usbphy3_set_clock(struct samsung_usbphy *sphy) +{ + u32 reg; + u32 refclk; + + refclk = sphy->ref_clk_freq; + + reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | + PHYCLKRST_FSEL(refclk); + + switch (refclk) { + case FSEL_CLKSEL_50M: + reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | + PHYCLKRST_SSC_REFCLKSEL(0x00)); + break; + case FSEL_CLKSEL_20M: + reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF | + PHYCLKRST_SSC_REFCLKSEL(0x00)); + break; + case FSEL_CLKSEL_19200K: + reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF | + PHYCLKRST_SSC_REFCLKSEL(0x88)); + break; + case FSEL_CLKSEL_24M: + default: + reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | + PHYCLKRST_SSC_REFCLKSEL(0x88)); + break; + } + + return reg; +} + +static int samsung_exynos5_usbphy3_enable(struct samsung_usbphy *sphy) +{ + void __iomem *regs = sphy->regs_phy3; + u32 phyparam0; + u32 phyparam1; + u32 linksystem; + u32 phybatchg; + u32 phytest; + u32 phyclkrst; + /* Reset USB 3.0 PHY */ + writel(0x0, regs + EXYNOS5_DRD_PHYREG0); + + phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0); + /* Select PHY CLK source */ + phyparam0 &= ~PHYPARAM0_REF_USE_PAD; + /* Set Loss-of-Signal Detector sensitivity */ + phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK; + phyparam0 |= PHYPARAM0_REF_LOSLEVEL; + writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0); + + writel(0x0, regs + EXYNOS5_DRD_PHYRESUME); + + /* + * Setting the Frame length Adj value[6:1] to default 0x20 + * See xHCI 1.0 spec, 5.2.4 + */ + linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL | + LINKSYSTEM_FLADJ(0x20); + writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM); + + phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1); + /* Set Tx De-Emphasis level */ + phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; + phyparam1 |= PHYPARAM1_PCS_TXDEEMPH; + writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1); + + phybatchg = readl(regs + EXYNOS5_DRD_PHYBATCHG); + phybatchg |= PHYBATCHG_UTMI_CLKSEL; + writel(phybatchg, regs + EXYNOS5_DRD_PHYBATCHG); + + /* PHYTEST POWERDOWN Control */ + phytest = readl(regs + EXYNOS5_DRD_PHYTEST); + phytest &= ~(PHYTEST_POWERDOWN_SSP | + PHYTEST_POWERDOWN_HSP); + writel(phytest, regs + EXYNOS5_DRD_PHYTEST); + + /* UTMI Power Control */ + writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI); + + phyclkrst = exynos5_usbphy3_set_clock(sphy); + + phyclkrst |= PHYCLKRST_PORTRESET | + /* Digital power supply in normal operating mode */ + PHYCLKRST_RETENABLEN | + /* Enable ref clock for SS function */ + PHYCLKRST_REF_SSP_EN | + /* Enable spread spectrum */ + PHYCLKRST_SSC_EN | + /* Power down HS Bias and PLL blocks in suspend mode */ + PHYCLKRST_COMMONONN; + + writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST); + + udelay(10); + + phyclkrst &= ~(PHYCLKRST_PORTRESET); + writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST); + + return 0; +} + +static void samsung_exynos5_usbphy3_disable(struct samsung_usbphy *sphy) +{ + u32 phyutmi; + u32 phyclkrst; + u32 phytest; + void __iomem *regs = sphy->regs_phy3; + + phyutmi = PHYUTMI_OTGDISABLE | + PHYUTMI_FORCESUSPEND | + PHYUTMI_FORCESLEEP; + writel(phyutmi, regs + EXYNOS5_DRD_PHYUTMI); + + /* Resetting the PHYCLKRST enable bits to reduce leakage current */ + phyclkrst = readl(regs + EXYNOS5_DRD_PHYCLKRST); + phyclkrst &= ~(PHYCLKRST_REF_SSP_EN | + PHYCLKRST_SSC_EN | + PHYCLKRST_COMMONONN); + writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST); + + /* Control PHYTEST to remove leakage current */ + phytest = readl(regs + EXYNOS5_DRD_PHYTEST); + phytest |= (PHYTEST_POWERDOWN_SSP | + PHYTEST_POWERDOWN_HSP); + writel(phytest, regs + EXYNOS5_DRD_PHYTEST); +} + +static int samsung_usbphy3_init(struct usb_phy *phy3) +{ + struct samsung_usbphy *sphy; + int ret = 0; + + sphy = phy3_to_sphy(phy3); + + if (sphy->drv_data->cpu_type != TYPE_EXYNOS5250) { + dev_err(sphy->dev, "Not a valid cpu_type for USB 3.0\n"); + return -ENODEV; + } + /* setting default phy-type for USB 3.0 */ + samsung_usbphy_set_type(&sphy->phy3, USB_PHY_TYPE_DRD); + + /* Enable the phy clock */ + ret = clk_prepare_enable(sphy->clk); + if (ret) { + dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__); + return ret; + } + + /* Disable phy isolation */ + if (sphy->plat && sphy->plat->pmu_isolation) + sphy->plat->pmu_isolation(false); + else + samsung_usbphy_set_isolation(sphy, false); + + /* Initialize usb phy registers */ + samsung_exynos5_usbphy3_enable(sphy); + + /* Disable the phy clock */ + clk_disable_unprepare(sphy->clk); + + return ret; +} + +/* + * The function passed to the usb driver for phy shutdown + */ +static void samsung_usbphy3_shutdown(struct usb_phy *phy3) +{ + struct samsung_usbphy *sphy; + + sphy = phy3_to_sphy(phy3); + + if (sphy->drv_data->cpu_type != TYPE_EXYNOS5250) { + dev_err(sphy->dev, "Not a valid cpu_type for USB 3.0\n"); + return; + } + + /* setting default phy-type for USB 3.0 */ + samsung_usbphy_set_type(&sphy->phy3, USB_PHY_TYPE_DRD); + + if (clk_prepare_enable(sphy->clk)) { + dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__); + return; + } + + /* De-initialize usb phy registers */ + samsung_exynos5_usbphy3_disable(sphy); + + /* Enable phy isolation */ + if (sphy->plat && sphy->plat->pmu_isolation) + sphy->plat->pmu_isolation(true); + else + samsung_usbphy_set_isolation(sphy, true); + + clk_disable_unprepare(sphy->clk); +} + static const struct of_device_id samsung_usbphy_dt_match[]; static inline const struct samsung_usbphy_drvdata @@ -778,6 +1079,8 @@ static int samsung_usbphy_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct resource *phy_mem; void __iomem *phy_base; + struct resource *phy3_mem; + void __iomem *phy3_base = NULL; struct clk *clk; int ret; @@ -842,7 +1145,38 @@ static int samsung_usbphy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sphy); - return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2); + if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) { + phy3_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!phy3_mem) { + dev_err(dev, "%s: missing mem resource\n", __func__); + return -ENODEV; + } + phy3_base = devm_request_and_ioremap(dev, phy3_mem); + if (!phy3_base) { + dev_err(dev, "%s: register mapping failed\n", __func__); + return -ENXIO; + } + } + + sphy->regs_phy3 = phy3_base; + sphy->phy3.dev = sphy->dev; + sphy->phy3.label = "samsung-usbphy3"; + sphy->phy3.init = samsung_usbphy3_init; + sphy->phy3.shutdown = samsung_usbphy3_shutdown; + + ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2); + + if (ret) + return ret; + + if (sphy->drv_data->cpu_type != TYPE_EXYNOS5250) { + dev_warn(dev, "Not a valid cpu_type for USB 3.0\n"); + } else { + ret = usb_add_phy(&sphy->phy3, USB_PHY_TYPE_USB3); + if (ret) + return ret; + } + return ret; } static int samsung_usbphy_remove(struct platform_device *pdev) @@ -851,6 +1185,9 @@ static int samsung_usbphy_remove(struct platform_device *pdev) usb_remove_phy(&sphy->phy); + if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) + usb_remove_phy(&sphy->phy3); + if (sphy->pmuregs) iounmap(sphy->pmuregs); if (sphy->sysreg) diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index fa00304a63d8..12cdf5fb06c6 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c @@ -274,6 +274,11 @@ static int pwm_backlight_remove(struct platform_device *pdev) return 0; } +static void pwm_backlight_shutdown(struct platform_device *pdev) +{ + pwm_backlight_remove(pdev); +} + #ifdef CONFIG_PM static int pwm_backlight_suspend(struct device *dev) { @@ -313,6 +318,7 @@ static struct platform_driver pwm_backlight_driver = { }, .probe = pwm_backlight_probe, .remove = pwm_backlight_remove, + .shutdown = pwm_backlight_shutdown, }; module_platform_driver(pwm_backlight_driver); diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c index 968a62571df7..1b6b01940682 100644 --- a/drivers/video/s3c-fb.c +++ b/drivers/video/s3c-fb.c @@ -24,10 +24,13 @@ #include <linux/uaccess.h> #include <linux/interrupt.h> #include <linux/pm_runtime.h> +#include <linux/of.h> +#include <linux/of_gpio.h> #include <video/samsung_fimd.h> #include <mach/map.h> #include <plat/fb.h> +#include <plat/cpu.h> /* This driver will export a number of framebuffer interfaces depending * on the configuration passed in via the platform data. Each fb instance @@ -67,6 +70,8 @@ struct s3c_fb; #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08) #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C) +#define S3CFB_WIN_SET_PIXEL_ALPHA _IOW('F', 204, __u32) + /** * struct s3c_fb_variant - fb variant information * @is_2443: Set if S3C2443/S3C2416 style hardware. @@ -220,6 +225,7 @@ struct s3c_fb { int irq_no; unsigned long irq_flags; struct s3c_fb_vsync vsync_info; + int *gpios; }; /** @@ -1015,6 +1021,33 @@ static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc) return 0; } +int s3cfb_set_alpha_blending(struct s3c_fb *ctrl, int id) +{ + u32 avalue = 0, cfg; + + if (id == 0) { + dev_err(ctrl->dev, "[fb%d] does not support alpha blending\n", + id); + return -EINVAL; + } + + cfg = readl(ctrl->regs + S3C_WINCON(id)); + cfg |= (1 << 0); + writel(cfg, ctrl->regs + S3C_WINCON(id)); + cfg = readl(ctrl->regs + S3C_WINSHMAP); + cfg |= S3C_WINSHMAP_CH_ENABLE(id); + writel(cfg, ctrl->regs + S3C_WINSHMAP); + cfg = readl(ctrl->regs + S3C_WINCON(id)); + cfg &= ~(S3C_WINCON_BLD_MASK | S3C_WINCON_ALPHA_SEL_MASK); + + cfg |= (S3C_WINCON_BLD_PIXEL | S3C_WINCON_ALPHA1_SEL); + writel(cfg, ctrl->regs + S3C_WINCON(id)); + writel(avalue, ctrl->regs + S3C_VIDOSD_C(id)); + + cfg = readl(ctrl->regs + S3C_WINCON(id)); + return 0; +} + static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { @@ -1032,6 +1065,9 @@ static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, ret = s3c_fb_wait_for_vsync(sfb, crtc); break; + case S3CFB_WIN_SET_PIXEL_ALPHA: + ret = s3cfb_set_alpha_blending(sfb, win->index); + break; default: ret = -ENOTTY; } @@ -1039,8 +1075,30 @@ static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, return ret; } +int s3c_fb_open(struct fb_info *info, int user) +{ + s3c_fb_set_par(info); + return 0; +} + +int s3c_fb_release(struct fb_info *info, int user) +{ + struct s3c_fb_win *win = info->par; + struct s3c_fb *sfb = win->parent; + void __iomem *regs = sfb->regs; + int win_no = win->index; + + if (win_no != 2) { + printk(KERN_DEBUG"Releasing window %d\n", win_no); + writel(0, regs + WINCON(win_no)); + } + return 0; +} + static struct fb_ops s3c_fb_ops = { .owner = THIS_MODULE, + .fb_open = s3c_fb_open, + .fb_release = s3c_fb_release, .fb_check_var = s3c_fb_check_var, .fb_set_par = s3c_fb_set_par, .fb_blank = s3c_fb_blank, @@ -1269,8 +1327,6 @@ static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no, else dev_err(sfb->dev, "failed to allocate fb cmap\n"); - s3c_fb_set_par(fbinfo); - dev_dbg(sfb->dev, "about to register framebuffer\n"); /* run the check_var and set_par on our configuration. */ @@ -1359,27 +1415,217 @@ static void s3c_fb_clear_win(struct s3c_fb *sfb, int win) } } +#ifdef CONFIG_OF +static int s3c_fb_dt_parse_gpios(struct device *dev, struct s3c_fb *sfb, + bool request) +{ + int nr_gpios, idx, gpio, ret; + + if (soc_is_exynos5250()) + return 0; + + nr_gpios = sfb->pdata->win[0]->max_bpp + 4; + sfb->gpios = devm_kzalloc(dev, sizeof(int) * nr_gpios, GFP_KERNEL); + if (!sfb->gpios) { + dev_err(dev, "unable to allocate private data for gpio\n"); + return -ENOMEM; + } + + for (idx = 0; idx < nr_gpios; idx++) { + gpio = of_get_gpio(dev->of_node, idx); + if (!gpio_is_valid(gpio)) { + dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio); + return -EINVAL; + } + + if (!request) + continue; + + ret = gpio_request(gpio, "fimd"); + if (ret) { + dev_err(dev, "gpio [%d] request failed\n", gpio); + goto gpio_free; + } + sfb->gpios[idx] = gpio; + } + return 0; + +gpio_free: + while (--idx >= 0) + gpio_free(sfb->gpios[idx]); + return ret; +} + +static void s3c_fb_dt_free_gpios(struct s3c_fb *sfb) +{ + unsigned int idx, nr_gpio; + + nr_gpio = sfb->pdata->win[0]->max_bpp + 4; + for (idx = 0; idx < nr_gpio; idx++) + gpio_free(sfb->gpios[idx]); +} + +static struct s3c_fb_platdata *s3c_fb_dt_parse_pdata(struct device *dev) +{ + struct device_node *np = dev->of_node, *win_np; + struct device_node *disp_np; + struct s3c_fb_platdata *pd; + struct s3c_fb_pd_win *win; + u32 wnum = 0, data[4]; + + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) { + dev_err(dev, "memory allocation for pdata failed\n"); + return ERR_PTR(-ENOMEM); + } + + pd->vtiming = devm_kzalloc(dev, sizeof(*pd->vtiming), GFP_KERNEL); + if (!pd->vtiming) { + dev_err(dev, "memory allocation for vtiming failed\n"); + return ERR_PTR(-ENOMEM); + } + + if (of_get_property(np, "samsung,fimd-vidout-rgb", NULL)) + pd->vidcon0 |= VIDCON0_VIDOUT_RGB; + if (of_get_property(np, "samsung,fimd-vidout-tv", NULL)) + pd->vidcon0 |= VIDCON0_VIDOUT_TV; + if (of_get_property(np, "samsung,fimd-inv-hsync", NULL)) + pd->vidcon1 |= VIDCON1_INV_HSYNC; + if (of_get_property(np, "samsung,fimd-inv-vsync", NULL)) + pd->vidcon1 |= VIDCON1_INV_VSYNC; + if (of_get_property(np, "samsung,fimd-inv-vclk", NULL)) + pd->vidcon1 |= VIDCON1_INV_VCLK; + if (of_get_property(np, "samsung,fimd-inv-vden", NULL)) + pd->vidcon1 |= VIDCON1_INV_VDEN; + + disp_np = of_parse_phandle(np, "samsung,fimd-display", 0); + if (!disp_np) { + dev_err(dev, "unable to find display panel info\n"); + return ERR_PTR(-EINVAL); + } + + if (of_property_read_u32_array(disp_np, "lcd-htiming", data, 4)) { + dev_err(dev, "invalid horizontal timing\n"); + return ERR_PTR(-EINVAL); + } + pd->vtiming->left_margin = data[0]; + pd->vtiming->right_margin = data[1]; + pd->vtiming->hsync_len = data[2]; + pd->vtiming->xres = data[3]; + + if (of_property_read_u32_array(disp_np, "lcd-vtiming", data, 4)) { + dev_err(dev, "invalid vertical timing\n"); + return ERR_PTR(-EINVAL); + } + pd->vtiming->upper_margin = data[0]; + pd->vtiming->lower_margin = data[1]; + pd->vtiming->vsync_len = data[2]; + pd->vtiming->yres = data[3]; + + of_property_read_u32_array(np, "samsung,fimd-frame-rate", + &pd->vtiming->refresh, 1); + + for_each_child_of_node(np, win_np) { + if (of_property_read_u32_array(win_np, "samsung,fimd-win-id", + &wnum, 1)) { + dev_err(dev, "window id not specified\n"); + return ERR_PTR(-EINVAL); + } + + win = devm_kzalloc(dev, sizeof(*win), GFP_KERNEL); + if (!win) { + dev_err(dev, "no memory for window[%d] data\n", wnum); + return ERR_PTR(-ENOMEM); + } + pd->win[wnum] = win; + + if (of_property_read_u32_array(win_np, "samsung,fimd-win-bpp", + data, 2)) { + dev_err(dev, "invalid window bpp\n"); + return ERR_PTR(-EINVAL); + } + win->default_bpp = data[0]; + win->max_bpp = data[1]; + + if (of_property_read_u32_array(win_np, "samsung,fimd-win-res", + data, 2)) { + dev_info(dev, "window [%d] resolution not specified. " + "Using lcd resolution X[%d] and Y[%d]", wnum, + pd->vtiming->xres, pd->vtiming->yres); + win->xres = pd->vtiming->xres; + win->yres = pd->vtiming->yres; + } else { + win->xres = data[0]; + win->yres = data[1]; + } + + if (!of_property_read_u32_array(win_np, + "samsung,fimd-win-virtres", data, 2)) { + win->virtual_x = data[0]; + win->virtual_y = data[1]; + } + } + + return pd; +} +#else +static int s3c_fb_dt_parse_gpios(struct device *dev, struct s3c_fb *sfb, + bool request) +{ + return 0; +} + +static void s3c_fb_dt_free_gpios(struct s3c_fb *sfb) +{ + return 0; +} + +static int s3c_fb_dt_parse_pdata(struct device *dev) +{ + return 0; +} +#endif /* CONFIG_OF */ + +static const struct of_device_id s3c_fb_dt_match[]; + +static inline struct s3c_fb_driverdata *s3c_fb_get_driver_data( + struct platform_device *pdev) +{ +#ifdef CONFIG_OF + if (pdev->dev.of_node) { + const struct of_device_id *match; + match = of_match_node(s3c_fb_dt_match, pdev->dev.of_node); + return (struct s3c_fb_driverdata *)match->data; + } +#endif + return (struct s3c_fb_driverdata *) + platform_get_device_id(pdev)->driver_data; +} + static int s3c_fb_probe(struct platform_device *pdev) { - const struct platform_device_id *platid; struct s3c_fb_driverdata *fbdrv; struct device *dev = &pdev->dev; - struct s3c_fb_platdata *pd; + struct s3c_fb_platdata *pd = pdev->dev.platform_data; struct s3c_fb *sfb; struct resource *res; int win; int ret = 0; u32 reg; - platid = platform_get_device_id(pdev); - fbdrv = (struct s3c_fb_driverdata *)platid->driver_data; + fbdrv = s3c_fb_get_driver_data(pdev); if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) { dev_err(dev, "too many windows, cannot attach\n"); return -EINVAL; } - pd = pdev->dev.platform_data; + if (pdev->dev.of_node) { + pd = s3c_fb_dt_parse_pdata(&pdev->dev); + if (IS_ERR(pd)) + return PTR_ERR(pd); + } + if (!pd) { dev_err(dev, "no platform data specified\n"); return -EINVAL; @@ -1448,7 +1694,12 @@ static int s3c_fb_probe(struct platform_device *pdev) /* setup gpio and output polarity controls */ - pd->setup_gpio(); + if (dev->of_node) { + if (s3c_fb_dt_parse_gpios(dev, sfb, true)) + goto err_lcd_clk; + } else { + pd->setup_gpio(); + } writel(pd->vidcon1, sfb->regs + VIDCON1); @@ -1498,6 +1749,7 @@ static int s3c_fb_probe(struct platform_device *pdev) return 0; err_pm_runtime: + s3c_fb_dt_free_gpios(sfb); pm_runtime_put_sync(sfb->dev); err_lcd_clk: @@ -1537,6 +1789,7 @@ static int s3c_fb_remove(struct platform_device *pdev) pm_runtime_put_sync(sfb->dev); pm_runtime_disable(sfb->dev); + s3c_fb_dt_free_gpios(sfb); return 0; } @@ -1585,7 +1838,10 @@ static int s3c_fb_resume(struct device *dev) clk_prepare_enable(sfb->lcd_clk); /* setup gpio and output polarity controls */ - pd->setup_gpio(); + if (dev->of_node) + s3c_fb_dt_parse_gpios(dev, sfb, false); + else + pd->setup_gpio(); writel(pd->vidcon1, sfb->regs + VIDCON1); /* set video clock running at under-run */ @@ -1655,7 +1911,10 @@ static int s3c_fb_runtime_resume(struct device *dev) clk_prepare_enable(sfb->lcd_clk); /* setup gpio and output polarity controls */ - pd->setup_gpio(); + if (dev->of_node) + s3c_fb_dt_parse_gpios(dev, sfb, false); + else + pd->setup_gpio(); writel(pd->vidcon1, sfb->regs + VIDCON1); return 0; @@ -2025,6 +2284,15 @@ static struct platform_device_id s3c_fb_driver_ids[] = { }; MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids); +#ifdef CONFIG_OF +static const struct of_device_id s3c_fb_dt_match[] = { + { .compatible = "samsung,exynos4210-fimd", + .data = (void *)&s3c_fb_data_exynos4 }, + {}, +}; +MODULE_DEVICE_TABLE(of, s3c_fb_dt_match); +#endif + static const struct dev_pm_ops s3cfb_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume) SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume, @@ -2039,6 +2307,7 @@ static struct platform_driver s3c_fb_driver = { .name = "s3c-fb", .owner = THIS_MODULE, .pm = &s3cfb_pm_ops, + .of_match_table = of_match_ptr(s3c_fb_dt_match), }, }; diff --git a/firmware/edid-1920x1080.fw b/firmware/edid-1920x1080.fw Binary files differnew file mode 100644 index 000000000000..e90256c4fd2c --- /dev/null +++ b/firmware/edid-1920x1080.fw diff --git a/include/linux/printk.h b/include/linux/printk.h index 822171fcb1c8..976fae1a6f7d 100644 --- a/include/linux/printk.h +++ b/include/linux/printk.h @@ -6,6 +6,7 @@ extern const char linux_banner[]; extern const char linux_proc_banner[]; +extern const char linux_scm_version_banner[]; static inline int printk_get_level(const char *buffer) { diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h index 2d8bdaef9611..82e0bca2f426 100644 --- a/include/linux/scatterlist.h +++ b/include/linux/scatterlist.h @@ -229,7 +229,7 @@ size_t sg_copy_to_buffer(struct scatterlist *sgl, unsigned int nents, * Maximum number of entries that will be allocated in one piece, if * a list larger than this is required then chaining will be utilized. */ -#define SG_MAX_SINGLE_ALLOC (PAGE_SIZE / sizeof(struct scatterlist)) +#define SG_MAX_SINGLE_ALLOC ((PAGE_SIZE<<4) / sizeof(struct scatterlist)) /* * sg page iterator diff --git a/include/linux/usb/samsung_usb_phy.h b/include/linux/usb/samsung_usb_phy.h index 916782699f1c..327ac18493e6 100644 --- a/include/linux/usb/samsung_usb_phy.h +++ b/include/linux/usb/samsung_usb_phy.h @@ -13,4 +13,5 @@ enum samsung_usb_phy_type { USB_PHY_TYPE_DEVICE, USB_PHY_TYPE_HOST, + USB_PHY_TYPE_DRD, }; diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index dcd63745e83a..77fdfbaa5243 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -137,8 +137,10 @@ enum v4l2_colorfx { #define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) #define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) +#define V4L2_CID_CODEC_FRAME_TAG (V4L2_CID_BASE+43) + /* last CID + 1 */ -#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+44) /* USER-class private control IDs */ diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index b0393209679b..ed5230bfb772 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -435,6 +435,22 @@ #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) +/* Blending control registers */ +#define S3C_WINCON_BLD_PIXEL (1 << 6) +#define S3C_WINCON_BLD_MASK (1 << 6) +#define S3C_WINCON_ALPHA1_SEL (1 << 1) +#define S3C_WINCON_ALPHA_SEL_MASK (1 << 1) +#define S3C_WINCON(x) (0x0020 + (x * 0x04)) +#define S3C_VIDOSD_C(x) (0x0048 + (x * 0x10)) +#define S3C_WINSHMAP (0x0034) +#define S3C_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define S3C_WINCON_BLD_PLANE (0 << 6) +#define S3C_WINCON_ALPHA0_SEL (0 << 1) +#define S3C_VIDOSD_ALPHA0_SHIFT (12) +#define S3C_VIDOSD_ALPHA1_SHIFT (0) + +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ + /* Notes on per-window bpp settings * * Value Win0 Win1 Win2 Win3 Win 4 diff --git a/init/main.c b/init/main.c index 63534a141b4e..be64d1d307a0 100644 --- a/init/main.c +++ b/init/main.c @@ -498,6 +498,7 @@ asmlinkage void __init start_kernel(void) boot_cpu_init(); page_address_init(); printk(KERN_NOTICE "%s", linux_banner); + printk(KERN_NOTICE "%s", linux_scm_version_banner); setup_arch(&command_line); mm_init_owner(&init_mm, &init_task); mm_init_cpumask(&init_mm); diff --git a/init/version.c b/init/version.c index 58170f18912d..9d9f3f9dfb82 100644 --- a/init/version.c +++ b/init/version.c @@ -48,3 +48,6 @@ const char linux_proc_banner[] = "%s version %s" " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ")" " (" LINUX_COMPILER ") %s\n"; + +const char linux_scm_version_banner [] = + "Kernel was built at commit id '" KERNEL_GIT_ID "'\n"; diff --git a/linaro/configs/arndale.conf b/linaro/configs/arndale.conf index a4e44f4058ba..a3082308c731 100644 --- a/linaro/configs/arndale.conf +++ b/linaro/configs/arndale.conf @@ -1,5 +1,3 @@ -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_KALLSYMS_ALL=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y @@ -8,8 +6,8 @@ CONFIG_ARCH_EXYNOS=y CONFIG_S3C_LOWLEVEL_UART_PORT=2 # CONFIG_ARCH_EXYNOS4 is not set CONFIG_ARCH_EXYNOS5=y +CONFIG_VMSPLIT_2G=y CONFIG_NR_CPUS=2 -CONFIG_PREEMPT=y CONFIG_HIGHMEM=y # CONFIG_COMPACTION is not set CONFIG_ARM_APPENDED_DTB=y @@ -18,16 +16,16 @@ CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttyS CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_VFP=y CONFIG_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_EXTRA_FIRMWARE="edid-1920x1080.fw" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y CONFIG_ATA=y CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_EXYNOS=y CONFIG_AX88796=y CONFIG_AX88796_93CX6=y -CONFIG_SMC91X=y -CONFIG_SMC911X=y -CONFIG_SMSC911X=y CONFIG_USB_USBNET=y CONFIG_USB_NET_DM9601=y CONFIG_USB_NET_MCS7830=y @@ -44,14 +42,27 @@ CONFIG_CPU_THERMAL=y CONFIG_EXYNOS_THERMAL=y CONFIG_MFD_SEC_CORE=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_S5M8767=y +CONFIG_DRM=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_EXYNOS=y +CONFIG_DRM_EXYNOS_DMABUF=y +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DWC3=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_S5P=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_STORAGE=y +CONFIG_SAMSUNG_USBPHY=y +CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_IDMAC=y diff --git a/linaro/configs/origen_quad.conf b/linaro/configs/origen_quad.conf new file mode 100644 index 000000000000..ecfd3575ca23 --- /dev/null +++ b/linaro/configs/origen_quad.conf @@ -0,0 +1,92 @@ +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S3C24XX_PWM=y +CONFIG_MACH_SMDKC210=y +CONFIG_MACH_ARMLEX4210=y +CONFIG_MACH_UNIVERSAL_C210=y +CONFIG_MACH_NURI=y +CONFIG_MACH_ORIGEN=y +CONFIG_MACH_SMDK4412=y +CONFIG_MACH_ORIGEN_QUAD=y +CONFIG_MACH_EXYNOS4_DT=y +CONFIG_NR_CPUS=4 +CONFIG_AEABI=y +CONFIG_CMDLINE="root=/dev/mmcblk0p1 rw rootwait console=ttySAC2,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CFG80211=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_DM9601=y +CONFIG_USB_NET_MCS7830=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_SAMSUNG=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_S3C2410=y +CONFIG_MFD_SEC_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_FIMC=y +CONFIG_VIDEO_S5P_FIMC=y +CONFIG_VIDEO_SAMSUNG_S5P_TV=y +CONFIG_VIDEO_SAMSUNG_S5P_HDMI=y +CONFIG_VIDEO_SAMSUNG_S5P_SDO=y +CONFIG_VIDEO_SAMSUNG_S5P_MIXER=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_G2D=y +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=y +CONFIG_VIDEO_SAMSUNG_S5P_MFC=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_LOGO=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_NETDEVICES=y +CONFIG_USB_USBNET=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_S3C_UART2=y +CONFIG_EARLY_PRINTK=y +CONFIG_HID=y +CONFIG_USB_HID=y |