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| author | Mark Brown <broonie@linaro.org> | 2014-07-24 23:01:11 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-07-24 23:01:11 +0100 |
| commit | b9eb2f16785f31e4b38d1fff0c60c0817368acfc (patch) | |
| tree | 060d10afc969a95bcb1a191ca8768c5e77fae1be /Documentation | |
| parent | c5767dc1dc9cb86d60b001d22f77e82921f2d4f4 (diff) | |
| parent | bcddae4453f74e9d1dbc8db78c5c9bc552c600cb (diff) | |
Merge branch 'linux-linaro-lsk' into linux-linaro-lsk-rt
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/arm64/booting.txt | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 5273c4d60e65..1b0c968098aa 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -111,8 +111,14 @@ Before jumping into the kernel, the following conditions must be met: - Caches, MMUs The MMU must be off. Instruction cache may be on or off. - Data cache must be off and invalidated. - External caches (if present) must be configured and disabled. + The address range corresponding to the loaded kernel image must be + cleaned to the PoC. In the presence of a system cache or other + coherent masters with caches enabled, this will typically require + cache maintenance by VA rather than set/way operations. + System caches which respect the architected cache maintenance by VA + operations must be configured and may be enabled. + System caches which do not respect architected cache maintenance by VA + operations (not recommended) must be configured and disabled. - Architected timers CNTFRQ must be programmed with the timer frequency. |