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Currently the supported ISA is only printed on the latest architectures.
Print it also on legacy platforms.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6295/
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Add support for including VPE and TC ids in /proc/cpuinfo output as
appropriate when MT/SMTC is enabled.
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6065/
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MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything
ever build in the MIPS empire is either MIPS I or at least contains MIPS I.
If it's running Linux, that is.
So there is little point in having cpu_has_mips_1 because it will always
evaluate as true - though usually only at runtime. Thus there is no
point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it.
Little complication: traps.c was using a test for a pure MIPS I ISA as
a test for an R3000-style cp0. To deal with that, use a check for
cpu_has_3kex or cpu_has_4kex instead.
cpu_has_3kex is a new macro. At the moment its default implementation is
!cpu_has_4kex but this may eventually change if Linux is ever going to
support the oddball MIPS processors R6000 and R8000 so users of either
of these macros should not make any assumptions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5551/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
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This adds the option to build the Linux kernel using only the
microMIPS ISA. The resulting kernel binary is, at a minimum,
20% smaller than using the MIPS32R2 ISA.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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Previously this functionality was only available to users of the mips_machine
api. Moving the code to prom.c allows us to also add a OF wrapper.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5164/
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There is a missing " " inside /proc/cpuinfo.
The bad commit was:
commit a96102be700f87283f168942cd09a2b30f86f324
Author: Steven J. Hill <sjhill@mips.com>
Date: Fri Dec 7 04:31:36 2012 +0000
MIPS: Add printing of ISA version in cpuinfo.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4988/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
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The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23]. Probe for this and report it in
/proc/cpuinfo.
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4904/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4682/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Display the MIPS ISA version release in the /proc/cpuinfo file.
[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions. Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.
Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it. For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code. The same for a 32-bit kernel running on a 64-bit processor. This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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The number of %s was just getting ridiculous.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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This has been obsolescent for a while; time for the final push.
In adjacent context, replaced old cpus_* with cpumask_*.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Acked-by: David S. Miller <davem@davemloft.net> (arch/sparc)
Acked-by: Chris Metcalf <cmetcalf@tilera.com> (arch/tile)
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: linux-hexagon@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Helge Deller <deller@gmx.de>
Cc: sparclinux@vger.kernel.org
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Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1877/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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This patch adds a generic solution to support multiple machines based on
a given SoC within a single kernel image. It is implemented already for
several other architectures but MIPS has no generic support for that yet.
[Ralf: This competes with DT but DT is a much more complex solution and this
code has been used by OpenWRT for a long time so for now DT is a bad reason
to stop the merge but longer term this should be migrated to DT.]
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: kaloz@openwrt.org
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1814/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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They tend to get not updated when files are moved around or copied and
lack any obvious use. While at it zap some only too obvious comments and
as per Shinya's suggestion, add a copyright header to extable.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
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Outlining fixes the issue were on certain CPUs such as the R10000 family
the delay loop would need an extra cycle if it overlaps a cacheline
boundary.
The rewrite also fixes build errors with GCC 4.4 which was changed in
way incompatible with the kernel's inline assembly.
Relying on pure C for computation of the delay value removes the need for
explicit. The price we pay is a slight slowdown of the computation - to
be fixed on another day.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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It should print the type of the Nth processor.
Signed-off-by: Johannes Dickgreber <tanzy@gmx.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Probe for watch register characteristics, and report them in /proc/cpuinfo.
Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Jan Engelhardt <jengelh@computergmbh.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Shadow register support would not possibly have worked on multicore
systems. The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.
SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code. So fix
the allocator by ditching it. Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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So far /proc/cpuinfo has been the only user but human readable processor
name are more useful than that for proc.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.
It originally comes from the OpenWrt patches.
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Make sure cpu_has_fpu (which uses smp_processor_id()) is used only in
atomic context.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Currently, /proc/cpuinfo contains several copies of the information for
whatever processor we happen to be scheduled on. This patch makes it contain
the proper information for each CPU, which is particularly useful on mixed
R12k/R10k IP27 machines.
Signed-off-by: Karl-Johan Karlsson <creideiki@lysator.liu.se>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
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Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Nothing exciting; Linux just didn't know it yet so this is most adding
a value to a case statement.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Put in a blank line between CPU entries in /proc/cpuinfo, just like
most other architectures (i386, ia64, x86_64) do.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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the value for the last CPU having calibrated it's delay loop.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
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