diff options
author | Harry Liebel <Harry.Liebel@arm.com> | 2014-02-14 14:42:48 +0000 |
---|---|---|
committer | Dan Handley <dan.handley@arm.com> | 2014-02-17 18:51:44 +0000 |
commit | 561cd33eceaff56a1c6cabe5a3e6e03e21e9dc9a (patch) | |
tree | 838cc81a5f823db5344f3581cf7f77e72efd636c /plat/fvp/bl2_plat_setup.c | |
parent | f58ad36f2f51798b093d282b56a3a311fdc78ca9 (diff) |
Add Firmware Image Package (FIP) driver
The Firmware Image Package (FIP) driver allows for data to be loaded
from a FIP on platform storage. The FVP supports loading bootloader
images from a FIP located in NOR FLASH.
The implemented FVP policy states that bootloader images will be
loaded from a FIP in NOR FLASH if available and fall back to loading
individual images from semi-hosting.
NOTE:
- BL3-3(e.g. UEFI) is loaded into DRAM and needs to be configured
to run from the BL33_BASE address. This is currently set to
DRAM_BASE+128MB for the FVP.
Change-Id: I2e4821748e3376b5f9e467cf3ec09509e43579a0
Diffstat (limited to 'plat/fvp/bl2_plat_setup.c')
-rw-r--r-- | plat/fvp/bl2_plat_setup.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index 4efb436..f8c922e 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -28,7 +28,6 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include <string.h> #include <assert.h> #include <arch_helpers.h> #include <platform.h> @@ -71,12 +70,21 @@ extern unsigned char **bl2_el_change_mem_ptr; static meminfo bl2_tzram_layout __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), section("tzfw_coherent_mem"))); +/* Data structure which holds the extents of the Non-Secure DRAM for BL33 */ +static meminfo bl33_dram_layout +__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), + section("tzfw_coherent_mem"))); meminfo *bl2_plat_sec_mem_layout(void) { return &bl2_tzram_layout; } +meminfo *bl2_get_ns_mem_layout(void) +{ + return &bl33_dram_layout; +} + /******************************************************************************* * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted SRAM. @@ -93,6 +101,16 @@ void bl2_early_platform_setup(meminfo *mem_layout, bl2_tzram_layout.attr = mem_layout->attr; bl2_tzram_layout.next = 0; + /* Setup the BL3-3 memory layout. + * Normal World Firmware loaded into main DRAM. + */ + bl33_dram_layout.total_base = DRAM_BASE; + bl33_dram_layout.total_size = DRAM_SIZE; + bl33_dram_layout.free_base = DRAM_BASE; + bl33_dram_layout.free_size = DRAM_SIZE; + bl33_dram_layout.attr = 0; + bl33_dram_layout.next = 0; + /* Initialize the platform config for future decision making */ platform_config_setup(); |