From 438311a3bd32df6ab0352da55d3391fc8da3ae4e Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Wed, 6 Jul 2011 16:35:30 +0000 Subject: ArmPkg: Minor coding style changes git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11993 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Drivers/CpuPei/CpuPei.c | 6 ++- ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c | 57 +++++++++++----------- ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf | 1 + .../Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf | 1 + ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf | 3 ++ 5 files changed, 38 insertions(+), 30 deletions(-) (limited to 'ArmPkg') diff --git a/ArmPkg/Drivers/CpuPei/CpuPei.c b/ArmPkg/Drivers/CpuPei/CpuPei.c index 0a97745fa..bc01f306b 100755 --- a/ArmPkg/Drivers/CpuPei/CpuPei.c +++ b/ArmPkg/Drivers/CpuPei/CpuPei.c @@ -47,7 +47,7 @@ Abstract: #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED EFI_STATUS -FindMainMemory( +FindMainMemory ( OUT UINT32 *PhysicalBase, OUT UINT32 *Length ) @@ -71,7 +71,9 @@ FindMainMemory( } VOID -ConfigureMmu ( VOID ) +ConfigureMmu ( + VOID + ) { EFI_STATUS Status; UINTN Idx; diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c index 526af02d3..c2089fe84 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c @@ -12,6 +12,7 @@ * **/ +#include #include #include @@ -23,10 +24,10 @@ PL390GicEnableInterruptInterface ( ) { /* - * Enable the CPU interface in Non-Secure world - * Note: The ICCICR register is banked when Security extensions are implemented - */ - MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001); + * Enable the CPU interface in Non-Secure world + * Note: The ICCICR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001); } VOID @@ -35,11 +36,11 @@ PL390GicEnableDistributor ( IN INTN GicDistributorBase ) { - /* - * Enable GIC distributor in Non-Secure world. - * Note: The ICDDCR register is banked when Security extensions are implemented - */ - MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001); + /* + * Enable GIC distributor in Non-Secure world. + * Note: The ICDDCR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001); } VOID @@ -50,7 +51,7 @@ PL390GicSendSgiTo ( IN INTN CPUTargetList ) { - MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); + MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); } UINT32 @@ -60,18 +61,18 @@ PL390GicAcknowledgeSgiFrom ( IN INTN CoreId ) { - INTN InterruptId; + INTN InterruptId; - InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); + InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR); - //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID + // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { - //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR - MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); - return 1; - } else { - return 0; - } + // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR + MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); + return 1; + } else { + return 0; + } } UINT32 @@ -82,16 +83,16 @@ PL390GicAcknowledgeSgi2From ( IN INTN SgiId ) { - INTN InterruptId; + INTN InterruptId; - InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); + InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); - //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID + // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { - //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR - MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); - return 1; - } else { - return 0; - } + // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR + MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); + return 1; + } else { + return 0; + } } diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf index c847d89ec..17afbaf3b 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf @@ -42,6 +42,7 @@ MdePkg/MdePkg.dec [LibraryClasses] + IoLib MemoryAllocationLib [Protocols] diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf index e1de26f42..09c16db42 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf @@ -40,6 +40,7 @@ MdePkg/MdePkg.dec [LibraryClasses] + IoLib PrePiLib [Protocols] diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf index 05c8d362f..d3afed0af 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf @@ -36,6 +36,9 @@ ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec +[LibraryClasses] + IoLib + [Protocols] gEfiCpuArchProtocolGuid -- cgit v1.2.3