exynos: boot serial endian fix

uncompress serial line write utils need to use endian neutral functions to
read h/w register - i.e in case of BE host byteswap is needed. Fix uart_rd,
uart_wr and serial chip fifo related macros

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>

3 files changed, 31 insertions, 0 deletions

diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index f3a9cff6d5d4..4e09ca66aea0 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -9,17 +9,20 @@
  * published by the Free Software Foundation.
 */
 
+#include <asm/assembler.h>
 #include <plat/regs-serial.h>
 
 /* The S5PV210/S5PC110 implementations are as belows. */
 
 	.macro fifo_level_s5pv210 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+	ARM_BE8(rev	\rd, \rd)
 		and	\rd, \rd, #S5PV210_UFSTAT_TXMASK
 	.endm
 
 	.macro  fifo_full_s5pv210 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+	ARM_BE8(rev	\rd, \rd)
 		tst	\rd, #S5PV210_UFSTAT_TXFULL
 	.endm
 
@@ -28,6 +31,7 @@
 
 	.macro fifo_level_s3c2440 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+	ARM_BE8(rev	\rd, \rd)
 		and	\rd, \rd, #S3C2440_UFSTAT_TXMASK
 	.endm
 
@@ -37,6 +41,7 @@
 
 	.macro  fifo_full_s3c2440 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+	ARM_BE8(rev	\rd, \rd)
 		tst	\rd, #S3C2440_UFSTAT_TXFULL
 	.endm
 
@@ -50,6 +55,7 @@
 
 	.macro	busyuart, rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFCON]
+	ARM_BE8(rev	\rd, \rd)
 		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
 		beq	1001f				@
 		@ FIFO enabled...
@@ -61,6 +67,7 @@
 1001:
 		@ busy waiting for non fifo
 		ldr	\rd, [\rx, # S3C2410_UTRSTAT]
+	ARM_BE8(rev	\rd, \rd)
 		tst	\rd, #S3C2410_UTRSTAT_TXFE
 		beq	1001b
 
@@ -69,6 +76,7 @@
 
 	.macro	waituart,rd,rx
 		ldr	\rd, [\rx, # S3C2410_UFCON]
+	ARM_BE8(rev	\rd, \rd)
 		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
 		beq	1001f				@
 		@ FIFO enabled...
@@ -80,6 +88,7 @@
 1001:
 		@ idle waiting for non fifo
 		ldr	\rd, [\rx, # S3C2410_UTRSTAT]
+	ARM_BE8(rev	\rd, \rd)
 		tst	\rd, #S3C2410_UTRSTAT_TXFE
 		beq	1001b
 
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 5d7ce36be46f..7106a436883a 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -17,9 +17,15 @@
 #include <mach/map.h>
 #include <plat/uncompress.h>
 
+#include <linux/swab.h>
+
 static unsigned int __raw_readl(unsigned int ptr)
 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	return __swab32(*((volatile unsigned int *)ptr));
+#else
 	return *((volatile unsigned int *)ptr);
+#endif /* CONFIG_CPU_BIG_ENDIAN */
 }
 
 static void arch_detect_cpu(void)
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index f48dc0a4736c..94fef0470777 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_PLAT_UNCOMPRESS_H
 #define __ASM_PLAT_UNCOMPRESS_H
 
+#include <linux/swab.h>
+
 typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 
 /* uart setup */
@@ -54,6 +56,9 @@ uart_wr(unsigned int reg, unsigned int val)
 	volatile unsigned int *ptr;
 
 	ptr = (volatile unsigned int *)(reg + uart_base);
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	val = __swab32(val);
+#endif /* CONFIG_CPU_BIG_ENDIAN */
 	*ptr = val;
 }
 
@@ -63,7 +68,11 @@ uart_rd(unsigned int reg)
 	volatile unsigned int *ptr;
 
 	ptr = (volatile unsigned int *)(reg + uart_base);
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	return __swab32(*ptr);
+#else
 	return *ptr;
+#endif /* CONFIG_CPU_BIG_ENDIAN */
 }
 
 /* we can deal with the case the UARTs are being run
@@ -102,10 +111,17 @@ static inline void flush(void)
 {
 }
 
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __raw_writel(d, ad)			\
+	do {							\
+		*((volatile unsigned int __force *)(ad)) = __swab32(d); \
+	} while (0)
+#else
 #define __raw_writel(d, ad)			\
 	do {							\
 		*((volatile unsigned int __force *)(ad)) = (d); \
 	} while (0)
+#endif /* CONFIG_CPU_BIG_ENDIAN */
 
 #ifdef CONFIG_S3C_BOOT_ERROR_RESET