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author | Stephen Rothwell <sfr@canb.auug.org.au> | 2015-06-24 12:28:51 +1000 |
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committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2015-06-24 12:28:51 +1000 |
commit | 2d9aa35423017fc366d57d3efe97b75db5740e06 (patch) | |
tree | 1696ef7f669f4fe4f7bb9d954a7a12e979f5789a /Documentation | |
parent | e5797a06d7c2398bc3d6a6a6e5033a450b33e3e6 (diff) | |
parent | 5ffde2f67181195d457b95df44b8f88e8d969d89 (diff) |
Merge remote-tracking branch 'iommu/next'
Conflicts:
drivers/iommu/dmar.c
drivers/iommu/intel_irq_remapping.c
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt new file mode 100644 index 000000000000..c03eec116872 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -0,0 +1,37 @@ +* ARM SMMUv3 Architecture Implementation + +The SMMUv3 architecture is a significant deparature from previous +revisions, replacing the MMIO register interface with in-memory command +and event queues and adding support for the ATS and PRI components of +the PCIe specification. + +** SMMUv3 required properties: + +- compatible : Should include: + + * "arm,smmu-v3" for any SMMUv3 compliant + implementation. This entry should be last in the + compatible list. + +- reg : Base address and size of the SMMU. + +- interrupts : Non-secure interrupt list describing the wired + interrupt sources corresponding to entries in + interrupt-names. If no wired interrupts are + present then this property may be omitted. + +- interrupt-names : When the interrupts property is present, should + include the following: + * "eventq" - Event Queue not empty + * "priq" - PRI Queue not empty + * "cmdq-sync" - CMD_SYNC complete + * "gerror" - Global Error activated + +** SMMUv3 optional properties: + +- dma-coherent : Present if DMA operations made by the SMMU (page + table walks, stream table accesses etc) are cache + coherent with the CPU. + + NOTE: this only applies to the SMMU itself, not + masters connected upstream of the SMMU. |