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| author | Steven Rostedt <srostedt@redhat.com> | 2011-12-21 22:22:04 -0500 |
|---|---|---|
| committer | Steven Rostedt <rostedt@goodmis.org> | 2011-12-21 22:22:04 -0500 |
| commit | d41ad8673f19afae15351a8aee5cea466aa01cc6 (patch) | |
| tree | 1eea954744122faa117ab4e87d9f923040648920 /arch/arm/Kconfig | |
| parent | b6154617aa6dc001d1ccf0e90a19cd857619dd03 (diff) | |
| parent | 6636552f1dd0d2e2be2f87605ea2cd3aa4d2e5b6 (diff) | |
Merge commit 'v3.0.14' into v3.0-rt-next
Conflicts:
kernel/hrtimer.c
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5c224f5b188b..0fd9288d893c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1313,6 +1313,18 @@ config ARM_ERRATA_764369 relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. +config PL310_ERRATA_769419 + bool "PL310 errata: no automatic Store Buffer drain" + depends on CACHE_L2X0 + help + On revisions of the PL310 prior to r3p2, the Store Buffer does + not automatically drain. This can cause normal, non-cacheable + writes to be retained when the memory system is idle, leading + to suboptimal I/O performance for drivers using coherent DMA. + This option adds a write barrier to the cpu_idle loop so that, + on systems with an outer cache, the store buffer is drained + explicitly. + endmenu menu "Kernel Features" |