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| author | Anders Roxell <anders.roxell@linaro.org> | 2014-09-30 20:38:55 +0200 |
|---|---|---|
| committer | Anders Roxell <anders.roxell@linaro.org> | 2014-09-30 20:38:55 +0200 |
| commit | b3f90769b6aed6d4e97061cd26e8fa06a4478901 (patch) | |
| tree | a3245cae4ead8e173f92d2b88cb5fa2cd11016a1 /arch/arm/mach-exynos/headsmp.S | |
| parent | 72df321f602520b6ea09f47a71b6795efc0a83c8 (diff) | |
| parent | 1c3a7e235d7a2afbf6d99097e3aa117b4ff55ff1 (diff) | |
Merge commit '1c3a7e2' into linux-linaro-lng-v3.14-rtInitial_commit_of_LSK-based_LNG_RT_kernel
Diffstat (limited to 'arch/arm/mach-exynos/headsmp.S')
| -rw-r--r-- | arch/arm/mach-exynos/headsmp.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index cdd9d91e9933..bec41317c4ac 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -12,6 +12,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> +#include <asm/assembler.h> /* * exynos4 specific entry point for secondary CPUs. This provides @@ -19,8 +20,13 @@ * ready for them to initialise. */ ENTRY(exynos4_secondary_startup) + /* + * ROM code operates in little endian mode, when we get control we + * need to switch it to big endian mode. + */ +ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 + and r0, r0, #0xffffff adr r4, 1f ldmia r4, {r5, r6} sub r4, r4, r5 |