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authorCatalin Marinas <catalin.marinas@arm.com>2010-12-07 16:56:29 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-12 23:25:58 +0000
commitda30e0ac0f9a521f0cfec8145ddd1ad131f66d61 (patch)
tree4a9002e6fca4d4763b40908403fc177153b9a6a8 /arch/arm/tools
parentf91e2c3bd427239c198351f44814dd39db91afe0 (diff)
ARM: 6528/1: Use CTR for the I-cache line size on ARMv7
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/tools')
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