diff options
author | Gary S. Robertson <gary.robertson@linaro.org> | 2015-10-21 01:59:12 -0500 |
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committer | Gary S. Robertson <gary.robertson@linaro.org> | 2015-10-21 01:59:12 -0500 |
commit | 8797b9d0f050f5d5c5b6ccb9b3c993bc02d6937b (patch) | |
tree | c6305b31b18ca2f49c1e1b88fec9c920be0252f2 /drivers/clk/keystone/pll.c | |
parent | 48ffd0d5e7b2fb6e7d47344320dbeeaf15d6fd5a (diff) | |
parent | a143f427f3e7c6d80bc1d288334706a1f8237f5f (diff) |
Merge tag 'lsk-v4.1-15.09-rt' of http://git.linaro.org/kernel/linux-linaro-stable into linux-linaro-lng-v4.1-rtlinux-lng-preempt-rt-4.1.7-2015.12linux-lng-preempt-rt-4.1.7-2015.11linux-lng-preempt-rt-4.1.7-2015.10
LSK RT 15.09 v4.1
Signed-off-by: Gary S. Robertson <gary.robertson@linaro.org>
Conflicts:
linaro/configs/distribution.conf
Diffstat (limited to 'drivers/clk/keystone/pll.c')
-rw-r--r-- | drivers/clk/keystone/pll.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 0dd8a4b12747..4a375ead70e9 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -37,7 +37,8 @@ * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL * or PA PLL available on keystone2. These PLLs are controlled by * this register. Main PLL is controlled by a PLL controller. - * @pllm: PLL register map address + * @pllm: PLL register map address for multiplier bits + * @pllod: PLL register map address for post divider bits * @pll_ctl0: PLL controller map address * @pllm_lower_mask: multiplier lower mask * @pllm_upper_mask: multiplier upper mask @@ -53,6 +54,7 @@ struct clk_pll_data { u32 phy_pllm; u32 phy_pll_ctl0; void __iomem *pllm; + void __iomem *pllod; void __iomem *pll_ctl0; u32 pllm_lower_mask; u32 pllm_upper_mask; @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, /* read post divider from od bits*/ postdiv = ((val & pll_data->clkod_mask) >> pll_data->clkod_shift) + 1; - else + else if (pll_data->pllod) { + postdiv = readl(pll_data->pllod); + postdiv = ((postdiv & pll_data->clkod_mask) >> + pll_data->clkod_shift) + 1; + } else postdiv = pll_data->postdiv; rate /= (prediv + 1); @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) /* assume the PLL has output divider register bits */ pll_data->clkod_mask = CLKOD_MASK; pll_data->clkod_shift = CLKOD_SHIFT; + + /* + * Check if there is an post-divider register. If not + * assume od bits are part of control register. + */ + i = of_property_match_string(node, "reg-names", + "post-divider"); + pll_data->pllod = of_iomap(node, i); } i = of_property_match_string(node, "reg-names", "control"); pll_data->pll_ctl0 = of_iomap(node, i); if (!pll_data->pll_ctl0) { pr_err("%s: ioremap failed\n", __func__); + iounmap(pll_data->pllod); goto out; } @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) pll_data->pllm = of_iomap(node, i); if (!pll_data->pllm) { iounmap(pll_data->pll_ctl0); + iounmap(pll_data->pllod); goto out; } } |