diff options
| author | Gary S. Robertson <gary.robertson@linaro.org> | 2015-12-16 20:33:52 -0600 |
|---|---|---|
| committer | Gary S. Robertson <gary.robertson@linaro.org> | 2015-12-16 20:33:52 -0600 |
| commit | 75e2d5300fc98dccb3b99031daf1081a8952a738 (patch) | |
| tree | df130108bbac39067b9ad1cbda2f4fd4116da59e /drivers/irqchip/irq-atmel-aic5.c | |
| parent | fe7e08f8621d68222f1c65599d8c8d10f0cf5164 (diff) | |
| parent | 6844488aaa6b23d45106c9c3c3ba2f2ee4a612f9 (diff) | |
Merge tag 'lsk-v4.1-15.11' of http://git.linaro.org/kernel/linux-linaro-stable into linux-linaro-lng-v4.1linux-lng-4.1.13-2015.12
LSK 15.11 v4.1
Signed-off-by: Gary S. Robertson <gary.robertson@linaro.org>
Conflicts:
linaro/configs/preempt-rt.conf
linaro/configs/vexpress64.conf
Diffstat (limited to 'drivers/irqchip/irq-atmel-aic5.c')
| -rw-r--r-- | drivers/irqchip/irq-atmel-aic5.c | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index a2e8c3f876cb..c2c578f0b268 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -88,28 +88,36 @@ static void aic5_mask(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *gc = dgc->gc[0]; + struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - /* Disable interrupt on AIC5 */ - irq_gc_lock(gc); + /* + * Disable interrupt on AIC5. We always take the lock of the + * first irq chip as all chips share the same registers. + */ + irq_gc_lock(bgc); irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(gc, 1, AT91_AIC5_IDCR); gc->mask_cache &= ~d->mask; - irq_gc_unlock(gc); + irq_gc_unlock(bgc); } static void aic5_unmask(struct irq_data *d) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; - struct irq_chip_generic *gc = dgc->gc[0]; + struct irq_chip_generic *bgc = dgc->gc[0]; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - /* Enable interrupt on AIC5 */ - irq_gc_lock(gc); + /* + * Enable interrupt on AIC5. We always take the lock of the + * first irq chip as all chips share the same registers. + */ + irq_gc_lock(bgc); irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(gc, 1, AT91_AIC5_IECR); gc->mask_cache |= d->mask; - irq_gc_unlock(gc); + irq_gc_unlock(bgc); } static int aic5_retrigger(struct irq_data *d) |