diff options
48 files changed, 455 insertions, 248 deletions
diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S index 8d8d922e5e44..dc62d4ae04d0 100644 --- a/arch/arm/include/debug/samsung.S +++ b/arch/arm/include/debug/samsung.S @@ -9,17 +9,20 @@ * published by the Free Software Foundation. */ +#include <asm/assembler.h> #include <linux/serial_s3c.h> /* The S5PV210/S5PC110 implementations are as belows. */ .macro fifo_level_s5pv210 rd, rx ldr \rd, [\rx, # S3C2410_UFSTAT] + ARM_BE8(rev \rd, \rd) and \rd, \rd, #S5PV210_UFSTAT_TXMASK .endm .macro fifo_full_s5pv210 rd, rx ldr \rd, [\rx, # S3C2410_UFSTAT] + ARM_BE8(rev \rd, \rd) tst \rd, #S5PV210_UFSTAT_TXFULL .endm @@ -28,6 +31,7 @@ .macro fifo_level_s3c2440 rd, rx ldr \rd, [\rx, # S3C2410_UFSTAT] + ARM_BE8(rev \rd, \rd) and \rd, \rd, #S3C2440_UFSTAT_TXMASK .endm @@ -37,6 +41,7 @@ .macro fifo_full_s3c2440 rd, rx ldr \rd, [\rx, # S3C2410_UFSTAT] + ARM_BE8(rev \rd, \rd) tst \rd, #S3C2440_UFSTAT_TXFULL .endm @@ -50,6 +55,7 @@ .macro busyuart, rd, rx ldr \rd, [\rx, # S3C2410_UFCON] + ARM_BE8(rev \rd, \rd) tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? beq 1001f @ @ FIFO enabled... @@ -61,6 +67,7 @@ 1001: @ busy waiting for non fifo ldr \rd, [\rx, # S3C2410_UTRSTAT] + ARM_BE8(rev \rd, \rd) tst \rd, #S3C2410_UTRSTAT_TXFE beq 1001b @@ -69,6 +76,7 @@ .macro waituart,rd,rx ldr \rd, [\rx, # S3C2410_UFCON] + ARM_BE8(rev \rd, \rd) tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? beq 1001f @ @ FIFO enabled... @@ -80,6 +88,7 @@ 1001: @ idle waiting for non fifo ldr \rd, [\rx, # S3C2410_UTRSTAT] + ARM_BE8(rev \rd, \rd) tst \rd, #S3C2410_UTRSTAT_TXFE beq 1001b diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 81064cd61a0a..803c4d6eeff2 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -44,6 +44,8 @@ config ARCH_EXYNOS4 select CPU_EXYNOS4210 select GIC_NON_BANKED select KEYBOARD_SAMSUNG if INPUT_KEYBOARD + select HAVE_ARM_SCU if SMP + select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help Samsung EXYNOS4 (Cortex-A9) SoC based systems @@ -51,6 +53,10 @@ config ARCH_EXYNOS4 config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" default y + select ARCH_SUPPORTS_BIG_ENDIAN + select CLKSRC_OF + select HAVE_SMP + select USB_ARCH_HAS_XHCI help Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems @@ -100,6 +106,8 @@ config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y depends on ARCH_EXYNOS5 + select S5P_PM if PM + select S5P_SLEEP if PM config SOC_EXYNOS5440 bool "SAMSUNG EXYNOS5440" diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 5f5cd562c593..52a5ccf03796 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -167,12 +167,12 @@ extern void __iomem *cpu_boot_reg_base(void); static inline void pmu_raw_writel(u32 val, u32 offset) { - __raw_writel(val, pmu_base_addr + offset); + writel_relaxed(val, pmu_base_addr + offset); } static inline u32 pmu_raw_readl(u32 offset) { - return __raw_readl(pmu_base_addr + offset); + return readl_relaxed(pmu_base_addr + offset); } #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 1bd35763f12e..46fb218d9712 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -100,7 +100,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) if (soc_is_exynos4412()) boot_reg += 4 * cpu; - __raw_writel(boot_addr, boot_reg); + writel_relaxed(boot_addr, boot_reg); return 0; } diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index b54f9701e421..45b3006e4e58 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -11,6 +11,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> +#include <asm/assembler.h> /* * exynos4 specific entry point for secondary CPUs. This provides @@ -18,6 +19,11 @@ * ready for them to initialise. */ ENTRY(exynos4_secondary_startup) + /* + * ROM code operates in little endian mode, when we get control we + * need to switch it to big endian mode. + */ +ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 adr r4, 1f diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 56978199c479..89c354e59583 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -219,9 +219,9 @@ static void exynos_mcpm_setup_entry_point(void) * mcpm_entry_point(). This is done during both secondary boot-up as * well as system resume. */ - __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ - __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ - __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); + writel_relaxed(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ + writel_relaxed(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ + writel_relaxed(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); } static struct syscore_ops exynos_mcpm_syscore_ops = { diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index a825bca2a2b6..e2dcee687f1c 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -321,7 +321,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) ret = PTR_ERR(boot_reg); goto fail; } - __raw_writel(boot_addr, boot_reg); + writel_relaxed(boot_addr, boot_reg); } call_firmware_op(cpu_boot, core_id); @@ -415,7 +415,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) if (IS_ERR(boot_reg)) break; - __raw_writel(boot_addr, boot_reg); + writel_relaxed(boot_addr, boot_reg); } } } diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index cc75ab448be3..f0b5cb37d9e5 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -26,6 +26,9 @@ #include <mach/map.h> #include <plat/pm-common.h> +#include <plat/regs-srom.h> + +#include <mach/map.h> #include "common.h" #include "exynos-pmu.h" @@ -133,9 +136,9 @@ static void exynos_set_wakeupmask(long mask) static void exynos_cpu_set_boot_vector(long flags) { - __raw_writel(virt_to_phys(exynos_cpu_resume), + writel_relaxed(virt_to_phys(exynos_cpu_resume), exynos_boot_vector_addr()); - __raw_writel(flags, exynos_boot_vector_flag()); + writel_relaxed(flags, exynos_boot_vector_flag()); } static int exynos_aftr_finisher(unsigned long flags) @@ -221,7 +224,7 @@ static int exynos_cpu0_enter_aftr(void) * boot back up again, getting stuck in the * boot rom code */ - if (__raw_readl(cpu_boot_reg_base()) == 0) + if (readl_relaxed(cpu_boot_reg_base()) == 0) goto abort; cpu_relax(); @@ -236,7 +239,7 @@ abort: /* * Set the boot vector to something non-zero */ - __raw_writel(virt_to_phys(exynos_cpu_resume), + writel_relaxed(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base()); dsb(); @@ -251,7 +254,7 @@ abort: /* * Poke cpu1 out of the boot rom */ - __raw_writel(virt_to_phys(exynos_cpu_resume), + writel_relaxed(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base()); arch_send_wakeup_ipi_mask(cpumask_of(1)); @@ -299,7 +302,7 @@ cpu1_aborted: static void exynos_pre_enter_aftr(void) { - __raw_writel(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base()); + writel_relaxed(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base()); } static void exynos_post_enter_aftr(void) diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index a9686535f9ed..5950d0937494 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -69,12 +69,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) } pwr = power_on ? INT_LOCAL_PWR_EN : 0; - __raw_writel(pwr, base); + writel_relaxed(pwr, base); /* Wait max 1ms */ timeout = 10; - while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) { + while ((readl_relaxed(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) { if (!timeout) { op = (power_on) ? "enable" : "disable"; pr_err("Power domain %s %s failed\n", domain->name, op); @@ -174,7 +174,7 @@ static __init int exynos4_pm_init_power_domain(void) clk_put(pd->oscclk); no_clk: - on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN; + on = readl_relaxed(pd->base + 0x4) & INT_LOCAL_PWR_EN; pm_genpd_init(&pd->pd, NULL, !on); of_genpd_add_provider_simple(np, &pd->pd); diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c index 71333bb61013..bd12a55401e0 100644 --- a/arch/arm/plat-samsung/cpu.c +++ b/arch/arm/plat-samsung/cpu.c @@ -29,14 +29,14 @@ EXPORT_SYMBOL(samsung_rev); void __init s3c64xx_init_cpu(void) { - samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118); + samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118); if (!samsung_cpu_id) { /* * S3C6400 has the ID register in a different place, * and needs a write before it can be read. */ - __raw_writel(0x0, S3C_VA_SYS + 0xA1C); - samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C); + writel_relaxed(0x0, S3C_VA_SYS + 0xA1C); + samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); } samsung_cpu_rev = 0; @@ -46,7 +46,7 @@ void __init s3c64xx_init_cpu(void) void __init s5p_init_cpu(void __iomem *cpuid_addr) { - samsung_cpu_id = __raw_readl(cpuid_addr); + samsung_cpu_id = readl_relaxed(cpuid_addr); samsung_cpu_rev = samsung_cpu_id & 0xFF; pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id); diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/plat-samsung/pm-common.c index 515cd53372bd..6534c3ff9fe2 100644 --- a/arch/arm/plat-samsung/pm-common.c +++ b/arch/arm/plat-samsung/pm-common.c @@ -31,7 +31,7 @@ void s3c_pm_do_save(struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) { - ptr->val = __raw_readl(ptr->reg); + ptr->val = readl_relaxed(ptr->reg); S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); } } @@ -51,9 +51,9 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) { pr_debug("restore %p (restore %08lx, was %08x)\n", - ptr->reg, ptr->val, __raw_readl(ptr->reg)); + ptr->reg, ptr->val, readl_relaxed(ptr->reg)); - __raw_writel(ptr->val, ptr->reg); + writel_relaxed(ptr->val, ptr->reg); } } @@ -71,5 +71,5 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count) void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) - __raw_writel(ptr->val, ptr->reg); + writel_relaxed(ptr->val, ptr->reg); } diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c index 64e15da33b42..9ae05006e092 100644 --- a/arch/arm/plat-samsung/pm-debug.c +++ b/arch/arm/plat-samsung/pm-debug.c @@ -68,14 +68,14 @@ void s3c_pm_save_uarts(void) void __iomem *regs = s3c_pm_uart_base(); struct pm_uart_save *save = &uart_save; - save->ulcon = __raw_readl(regs + S3C2410_ULCON); - save->ucon = __raw_readl(regs + S3C2410_UCON); - save->ufcon = __raw_readl(regs + S3C2410_UFCON); - save->umcon = __raw_readl(regs + S3C2410_UMCON); - save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); + save->ulcon = readl_relaxed(regs + S3C2410_ULCON); + save->ucon = readl_relaxed(regs + S3C2410_UCON); + save->ufcon = readl_relaxed(regs + S3C2410_UFCON); + save->umcon = readl_relaxed(regs + S3C2410_UMCON); + save->ubrdiv = readl_relaxed(regs + S3C2410_UBRDIV); if (!soc_is_s3c2410()) - save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); + save->udivslot = readl_relaxed(regs + S3C2443_DIVSLOT); S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); @@ -88,12 +88,12 @@ void s3c_pm_restore_uarts(void) s3c_pm_arch_update_uart(regs, save); - __raw_writel(save->ulcon, regs + S3C2410_ULCON); - __raw_writel(save->ucon, regs + S3C2410_UCON); - __raw_writel(save->ufcon, regs + S3C2410_UFCON); - __raw_writel(save->umcon, regs + S3C2410_UMCON); - __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); + writel_relaxed(save->ulcon, regs + S3C2410_ULCON); + writel_relaxed(save->ucon, regs + S3C2410_UCON); + writel_relaxed(save->ufcon, regs + S3C2410_UFCON); + writel_relaxed(save->umcon, regs + S3C2410_UMCON); + writel_relaxed(save->ubrdiv, regs + S3C2410_UBRDIV); if (!soc_is_s3c2410()) - __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); + writel_relaxed(save->udivslot, regs + S3C2443_DIVSLOT); } diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index f9a09262f2fa..75a3d386b4d9 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -32,15 +32,15 @@ static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip) { - chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); - chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); + chip->pm_save[0] = readl_relaxed(chip->base + OFFS_CON); + chip->pm_save[1] = readl_relaxed(chip->base + OFFS_DAT); } static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip) { void __iomem *base = chip->base; - u32 old_gpcon = __raw_readl(base + OFFS_CON); - u32 old_gpdat = __raw_readl(base + OFFS_DAT); + u32 old_gpcon = readl_relaxed(base + OFFS_CON); + u32 old_gpdat = readl_relaxed(base + OFFS_DAT); u32 gps_gpcon = chip->pm_save[0]; u32 gps_gpdat = chip->pm_save[1]; u32 gpcon; @@ -51,12 +51,12 @@ static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip) /* first set all SFN bits to SFN */ gpcon = old_gpcon | gps_gpcon; - __raw_writel(gpcon, base + OFFS_CON); + writel_relaxed(gpcon, base + OFFS_CON); /* now set all the other bits */ - __raw_writel(gps_gpdat, base + OFFS_DAT); - __raw_writel(gps_gpcon, base + OFFS_CON); + writel_relaxed(gps_gpdat, base + OFFS_DAT); + writel_relaxed(gps_gpcon, base + OFFS_CON); S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); @@ -69,9 +69,9 @@ struct samsung_gpio_pm samsung_gpio_pm_1bit = { static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip) { - chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); - chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); - chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); + chip->pm_save[0] = readl_relaxed(chip->base + OFFS_CON); + chip->pm_save[1] = readl_relaxed(chip->base + OFFS_DAT); + chip->pm_save[2] = readl_relaxed(chip->base + OFFS_UP); } /* Test whether the given masked+shifted bits of an GPIO configuration @@ -126,8 +126,8 @@ static inline int is_out(unsigned long con) static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip) { void __iomem *base = chip->base; - u32 old_gpcon = __raw_readl(base + OFFS_CON); - u32 old_gpdat = __raw_readl(base + OFFS_DAT); + u32 old_gpcon = readl_relaxed(base + OFFS_CON); + u32 old_gpdat = readl_relaxed(base + OFFS_DAT); u32 gps_gpcon = chip->pm_save[0]; u32 gps_gpdat = chip->pm_save[1]; u32 gpcon, old, new, mask; @@ -135,7 +135,7 @@ static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip) int nr; /* restore GPIO pull-up settings */ - __raw_writel(chip->pm_save[2], base + OFFS_UP); + writel_relaxed(chip->pm_save[2], base + OFFS_UP); /* Create a change_mask of all the items that need to have * their CON value changed before their DAT value, so that @@ -178,12 +178,12 @@ static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip) gpcon = old_gpcon & ~change_mask; gpcon |= gps_gpcon & change_mask; - __raw_writel(gpcon, base + OFFS_CON); + writel_relaxed(gpcon, base + OFFS_CON); /* Now change any items that require DAT,CON */ - __raw_writel(gps_gpdat, base + OFFS_DAT); - __raw_writel(gps_gpcon, base + OFFS_CON); + writel_relaxed(gps_gpdat, base + OFFS_DAT); + writel_relaxed(gps_gpcon, base + OFFS_CON); S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); @@ -197,12 +197,12 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = { #if defined(CONFIG_ARCH_S3C64XX) static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) { - chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); - chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); - chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); + chip->pm_save[1] = readl_relaxed(chip->base + OFFS_CON); + chip->pm_save[2] = readl_relaxed(chip->base + OFFS_DAT); + chip->pm_save[3] = readl_relaxed(chip->base + OFFS_UP); if (chip->chip.ngpio > 8) - chip->pm_save[0] = __raw_readl(chip->base - 4); + chip->pm_save[0] = readl_relaxed(chip->base - 4); } static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) @@ -247,7 +247,7 @@ static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index) { void __iomem *con = chip->base + (index * 4); - u32 old_gpcon = __raw_readl(con); + u32 old_gpcon = readl_relaxed(con); u32 gps_gpcon = chip->pm_save[index + 1]; u32 gpcon, mask; @@ -256,47 +256,47 @@ static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index) gpcon = old_gpcon & ~mask; gpcon |= gps_gpcon & mask; - __raw_writel(gpcon, con); + writel_relaxed(gpcon, con); } static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip) { void __iomem *base = chip->base; u32 old_gpcon[2]; - u32 old_gpdat = __raw_readl(base + OFFS_DAT); + u32 old_gpdat = readl_relaxed(base + OFFS_DAT); u32 gps_gpdat = chip->pm_save[2]; /* First, modify the CON settings */ old_gpcon[0] = 0; - old_gpcon[1] = __raw_readl(base + OFFS_CON); + old_gpcon[1] = readl_relaxed(base + OFFS_CON); samsung_gpio_pm_4bit_con(chip, 0); if (chip->chip.ngpio > 8) { - old_gpcon[0] = __raw_readl(base - 4); + old_gpcon[0] = readl_relaxed(base - 4); samsung_gpio_pm_4bit_con(chip, -1); } /* Now change the configurations that require DAT,CON */ - __raw_writel(chip->pm_save[2], base + OFFS_DAT); - __raw_writel(chip->pm_save[1], base + OFFS_CON); + writel_relaxed(chip->pm_save[2], base + OFFS_DAT); + writel_relaxed(chip->pm_save[1], base + OFFS_CON); if (chip->chip.ngpio > 8) - __raw_writel(chip->pm_save[0], base - 4); + writel_relaxed(chip->pm_save[0], base - 4); - __raw_writel(chip->pm_save[2], base + OFFS_DAT); - __raw_writel(chip->pm_save[3], base + OFFS_UP); + writel_relaxed(chip->pm_save[2], base + OFFS_DAT); + writel_relaxed(chip->pm_save[3], base + OFFS_UP); if (chip->chip.ngpio > 8) { S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n", chip->chip.label, old_gpcon[0], old_gpcon[1], - __raw_readl(base - 4), - __raw_readl(base + OFFS_CON), + readl_relaxed(base - 4), + readl_relaxed(base + OFFS_CON), old_gpdat, gps_gpdat); } else S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n", chip->chip.label, old_gpcon[1], - __raw_readl(base + OFFS_CON), + readl_relaxed(base + OFFS_CON), old_gpdat, gps_gpdat); } diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c index 20c3d9117cc2..877ede44390e 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/plat-samsung/wakeup-mask.c @@ -25,7 +25,7 @@ void samsung_sync_wakemask(void __iomem *reg, struct irq_data *data; u32 val; - val = __raw_readl(reg); + val = readl_relaxed(reg); for (; nr_mask > 0; nr_mask--, mask++) { if (mask->irq == NO_WAKEUP_IRQ) { @@ -42,6 +42,6 @@ void samsung_sync_wakemask(void __iomem *reg, val |= mask->bit; } - printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); - __raw_writel(val, reg); + printk(KERN_INFO "wakemask %08x => %08x\n", readl_relaxed(reg), val); + writel_relaxed(val, reg); } diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c index 2ecb50bea044..e4d5a4ce1e19 100644 --- a/arch/arm/plat-samsung/watchdog-reset.c +++ b/arch/arm/plat-samsung/watchdog-reset.c @@ -44,14 +44,14 @@ void samsung_wdt_reset(void) clk_prepare_enable(wdt_clock); /* disable watchdog, to be safe */ - __raw_writel(0, wdt_base + S3C2410_WTCON); + writel_relaxed(0, wdt_base + S3C2410_WTCON); /* put initial values into count and data */ - __raw_writel(0x80, wdt_base + S3C2410_WTCNT); - __raw_writel(0x80, wdt_base + S3C2410_WTDAT); + writel_relaxed(0x80, wdt_base + S3C2410_WTCNT); + writel_relaxed(0x80, wdt_base + S3C2410_WTDAT); /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | + writel_relaxed(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), wdt_base + S3C2410_WTCON); diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h index b7710a59672c..669d385c500b 100644 --- a/arch/arm64/include/asm/pmu.h +++ b/arch/arm64/include/asm/pmu.h @@ -65,6 +65,7 @@ struct arm_pmu { u64 max_period; struct platform_device *plat_device; struct pmu_hw_events *(*get_hw_events)(void); + int attr_rdpmc; }; #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 7778453762d8..407f9959867b 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -634,6 +634,16 @@ static void armpmu_disable(struct pmu *pmu) armpmu->stop(); } +static int armpmu_event_idx(struct perf_event *event) +{ + int idx = event->hw.idx; + + if (!cpu_pmu->attr_rdpmc) + return 0; + + return idx + 1; +} + static void __init armpmu_init(struct arm_pmu *armpmu) { atomic_set(&armpmu->active_events, 0); @@ -648,6 +658,7 @@ static void __init armpmu_init(struct arm_pmu *armpmu) .start = armpmu_start, .stop = armpmu_stop, .read = armpmu_read, + .event_idx = armpmu_event_idx, }; } @@ -1379,6 +1390,17 @@ static struct pmu_hw_events *armpmu_get_cpu_events(void) return this_cpu_ptr(&cpu_hw_events); } +void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) +{ + userpg->cap_user_rdpmc = cpu_pmu->attr_rdpmc; +} + +void arch_perf_uspace_access(void *enable) +{ + cpu_pmu->attr_rdpmc = *(int *)enable; + asm volatile("msr pmuserenr_el0, %0" : : "r" (!!*(int *)enable)); +} + static void __init cpu_pmu_init(struct arm_pmu *armpmu) { int cpu; diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 70ec3d2608a1..e76f7772fd54 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -806,7 +806,7 @@ static void __init exynos5250_clk_init(struct device_node *np) PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); - __raw_writel(tmp, reg_base + PWR_CTRL1); + writel_relaxed(tmp, reg_base + PWR_CTRL1); /* * Enable arm clock up (on exiting idle). Set arm divider @@ -816,7 +816,7 @@ static void __init exynos5250_clk_init(struct device_node *np) tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN | PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL | PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); - __raw_writel(tmp, reg_base + PWR_CTRL2); + writel_relaxed(tmp, reg_base + PWR_CTRL2); exynos5250_clk_sleep_init(); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 9d70e5c03804..7a79aead59f6 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -77,7 +77,7 @@ static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; @@ -110,7 +110,7 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; @@ -147,7 +147,7 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; @@ -184,19 +184,19 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); if (!(samsung_pll35xx_mp_change(rate, tmp))) { /* If only s change, change just s value only*/ tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); return 0; } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, + writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */ @@ -206,12 +206,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | (rate->pdiv << PLL35XX_PDIV_SHIFT) | (rate->sdiv << PLL35XX_SDIV_SHIFT); - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); /* wait_lock_time */ do { cpu_relax(); - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (PLL35XX_LOCK_STAT_MASK << PLL35XX_LOCK_STAT_SHIFT))); return 0; @@ -251,8 +251,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, s16 kdiv; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 4); mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; @@ -292,20 +292,20 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 4); if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { /* If only s change, change just s value only*/ pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); - __raw_writel(pll_con0, pll->con_reg); + writel_relaxed(pll_con0, pll->con_reg); return 0; } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */ pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | @@ -314,16 +314,16 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | (rate->pdiv << PLL36XX_PDIV_SHIFT) | (rate->sdiv << PLL36XX_SDIV_SHIFT); - __raw_writel(pll_con0, pll->con_reg); + writel_relaxed(pll_con0, pll->con_reg); pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; - __raw_writel(pll_con1, pll->con_reg + 4); + writel_relaxed(pll_con1, pll->con_reg + 4); /* wait_lock_time */ do { cpu_relax(); - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); return 0; @@ -364,7 +364,7 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; @@ -407,14 +407,14 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - con0 = __raw_readl(pll->con_reg); - con1 = __raw_readl(pll->con_reg + 0x4); + con0 = readl_relaxed(pll->con_reg); + con1 = readl_relaxed(pll->con_reg + 0x4); if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { /* If only s change, change just s value only*/ con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; - __raw_writel(con0, pll->con_reg); + writel_relaxed(con0, pll->con_reg); return 0; } @@ -428,29 +428,29 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL45XX_SDIV_SHIFT); /* Set PLL AFC value. */ - con1 = __raw_readl(pll->con_reg + 0x4); + con1 = readl_relaxed(pll->con_reg + 0x4); con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); con1 |= (rate->afc << PLL45XX_AFC_SHIFT); /* Set PLL lock time. */ switch (pll->type) { case pll_4502: - __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); break; case pll_4508: - __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); break; default: break; } /* Set new configuration. */ - __raw_writel(con1, pll->con_reg + 0x4); - __raw_writel(con0, pll->con_reg); + writel_relaxed(con1, pll->con_reg + 0x4); + writel_relaxed(con0, pll->con_reg); /* Wait for locking. */ start = ktime_get(); - while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) { + while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) { ktime_t delta = ktime_sub(ktime_get(), start); if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { @@ -511,8 +511,8 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 4); mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; @@ -558,14 +558,14 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - con0 = __raw_readl(pll->con_reg); - con1 = __raw_readl(pll->con_reg + 0x4); + con0 = readl_relaxed(pll->con_reg); + con1 = readl_relaxed(pll->con_reg + 0x4); if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { /* If only s change, change just s value only*/ con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; - __raw_writel(con0, pll->con_reg); + writel_relaxed(con0, pll->con_reg); return 0; } @@ -594,7 +594,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL46XX_SDIV_SHIFT); /* Set PLL K, MFR and MRR values. */ - con1 = __raw_readl(pll->con_reg + 0x4); + con1 = readl_relaxed(pll->con_reg + 0x4); con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); @@ -603,13 +603,13 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->mrr << PLL46XX_MRR_SHIFT); /* Write configuration to PLL */ - __raw_writel(lock, pll->lock_reg); - __raw_writel(con0, pll->con_reg); - __raw_writel(con1, pll->con_reg + 0x4); + writel_relaxed(lock, pll->lock_reg); + writel_relaxed(con0, pll->con_reg); + writel_relaxed(con1, pll->con_reg + 0x4); /* Wait for locking. */ start = ktime_get(); - while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) { + while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) { ktime_t delta = ktime_sub(ktime_get(), start); if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { @@ -654,7 +654,7 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); if (pll->type == pll_6552_s3c2416) { mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; @@ -694,8 +694,8 @@ static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con1 = __raw_readl(pll->con_reg + 0x4); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con1 = readl_relaxed(pll->con_reg + 0x4); mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; @@ -732,7 +732,7 @@ static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK; pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK; sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; @@ -750,7 +750,7 @@ static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw, u32 pll_con, mdiv, pdiv, sdiv; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK; pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK; sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; @@ -776,7 +776,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); /* Change PLL PMS values */ tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) | @@ -785,7 +785,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) | (rate->pdiv << PLLS3C2410_PDIV_SHIFT) | (rate->sdiv << PLLS3C2410_SDIV_SHIFT); - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); /* Time to settle according to the manual */ udelay(300); @@ -796,7 +796,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) { struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 pll_en = __raw_readl(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); + u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); u32 pll_en_orig = pll_en; if (enable) @@ -804,7 +804,7 @@ static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) else pll_en |= BIT(bit); - __raw_writel(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); + writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); /* if we started the UPLL, then allow to settle */ if (enable && (pll_en_orig & BIT(bit))) @@ -903,7 +903,7 @@ static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, u32 r, p, m, s, pll_stat; u64 fvco = parent_rate; - pll_stat = __raw_readl(pll->reg_base + pll->offset * 3); + pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3); r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; if (!r) return 0; @@ -981,7 +981,7 @@ static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->con_reg); + pll_con = readl_relaxed(pll->con_reg); mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; @@ -1017,19 +1017,19 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { /* If only s change, change just s value only*/ tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); tmp |= rate->sdiv << PLL2550XX_S_SHIFT; - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); return 0; } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */ tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | @@ -1038,12 +1038,12 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | (rate->pdiv << PLL2550XX_P_SHIFT) | (rate->sdiv << PLL2550XX_S_SHIFT); - __raw_writel(tmp, pll->con_reg); + writel_relaxed(tmp, pll->con_reg); /* wait_lock_time */ do { cpu_relax(); - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT))); @@ -1087,8 +1087,8 @@ static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, s16 kdiv; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->con_reg); - pll_con2 = __raw_readl(pll->con_reg + 8); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con2 = readl_relaxed(pll->con_reg + 8); mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; @@ -1115,8 +1115,8 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - pll_con0 = __raw_readl(pll->con_reg); - pll_con2 = __raw_readl(pll->con_reg + 8); + pll_con0 = readl_relaxed(pll->con_reg); + pll_con2 = readl_relaxed(pll->con_reg + 8); /* Change PLL PMS values */ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | @@ -1133,13 +1133,13 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, << PLL2650XX_KDIV_SHIFT; /* Set PLL lock time. */ - __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); - __raw_writel(pll_con0, pll->con_reg); - __raw_writel(pll_con2, pll->con_reg + 8); + writel_relaxed(pll_con0, pll->con_reg); + writel_relaxed(pll_con2, pll->con_reg + 8); do { - tmp = __raw_readl(pll->con_reg); + tmp = readl_relaxed(pll->con_reg); } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); return 0; diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c index 5645cfc90c41..19aaddd247d3 100644 --- a/drivers/clocksource/samsung_pwm_timer.c +++ b/drivers/clocksource/samsung_pwm_timer.c @@ -130,9 +130,9 @@ static void samsung_time_stop(unsigned int channel) spin_lock_irqsave(&samsung_pwm_lock, flags); - tcon = __raw_readl(pwm.base + REG_TCON); + tcon = readl_relaxed(pwm.base + REG_TCON); tcon &= ~TCON_START(channel); - __raw_writel(tcon, pwm.base + REG_TCON); + writel_relaxed(tcon, pwm.base + REG_TCON); spin_unlock_irqrestore(&samsung_pwm_lock, flags); } @@ -148,14 +148,14 @@ static void samsung_time_setup(unsigned int channel, unsigned long tcnt) spin_lock_irqsave(&samsung_pwm_lock, flags); - tcon = __raw_readl(pwm.base + REG_TCON); + tcon = readl_relaxed(pwm.base + REG_TCON); tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); tcon |= TCON_MANUALUPDATE(tcon_chan); - __raw_writel(tcnt, pwm.base + REG_TCNTB(channel)); - __raw_writel(tcnt, pwm.base + REG_TCMPB(channel)); - __raw_writel(tcon, pwm.base + REG_TCON); + writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel)); + writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel)); + writel_relaxed(tcon, pwm.base + REG_TCON); spin_unlock_irqrestore(&samsung_pwm_lock, flags); } @@ -170,7 +170,7 @@ static void samsung_time_start(unsigned int channel, bool periodic) spin_lock_irqsave(&samsung_pwm_lock, flags); - tcon = __raw_readl(pwm.base + REG_TCON); + tcon = readl_relaxed(pwm.base + REG_TCON); tcon &= ~TCON_MANUALUPDATE(channel); tcon |= TCON_START(channel); @@ -180,7 +180,7 @@ static void samsung_time_start(unsigned int channel, bool periodic) else tcon &= ~TCON_AUTORELOAD(channel); - __raw_writel(tcon, pwm.base + REG_TCON); + writel_relaxed(tcon, pwm.base + REG_TCON); spin_unlock_irqrestore(&samsung_pwm_lock, flags); } diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index 843ec824fd91..834fb3775d48 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -63,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index) tmp = apll_freq_4210[div_index].clk_div_cpu0; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); do { - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU); } while (tmp & 0x1111111); /* Change Divider - CPU1 */ tmp = apll_freq_4210[div_index].clk_div_cpu1; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); do { - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); } while (tmp & 0x11); } @@ -88,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index) clk_set_parent(moutcore, mout_mpll); do { - tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) + tmp = (readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); tmp &= 0x7; } while (tmp != 0x2); @@ -99,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index) clk_set_parent(moutcore, mout_apll); do { - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index 9e78a850e29f..01bf7d9159d2 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -103,25 +103,26 @@ static struct apll_freq apll_freq_4412[] = { static void exynos4x12_set_clkdiv(unsigned int div_index) { unsigned int tmp; + unsigned int stat_cpu1; /* Change Divider - CPU0 */ tmp = apll_freq_4x12[div_index].clk_div_cpu0; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); - while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU) + while (readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU) & 0x11111111) cpu_relax(); /* Change Divider - CPU1 */ tmp = apll_freq_4x12[div_index].clk_div_cpu1; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); do { cpu_relax(); - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); } while (tmp != 0x0); } @@ -134,7 +135,7 @@ static void exynos4x12_set_apll(unsigned int index) do { cpu_relax(); - tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) + tmp = (readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); tmp &= 0x7; } while (tmp != 0x2); @@ -146,7 +147,7 @@ static void exynos4x12_set_apll(unsigned int index) do { cpu_relax(); - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c index 3eafdc7ba787..0acee0c5295e 100644 --- a/drivers/cpufreq/exynos5250-cpufreq.c +++ b/drivers/cpufreq/exynos5250-cpufreq.c @@ -88,18 +88,18 @@ static void set_clkdiv(unsigned int div_index) tmp = apll_freq_5250[div_index].clk_div_cpu0; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0); - while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0) + while (readl_relaxed(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0) & 0x11111111) cpu_relax(); /* Change Divider - CPU1 */ tmp = apll_freq_5250[div_index].clk_div_cpu1; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1); - while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11) + while (readl_relaxed(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11) cpu_relax(); } @@ -113,7 +113,7 @@ static void set_apll(unsigned int index) do { cpu_relax(); - tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU) + tmp = (readl_relaxed(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU) >> 16); tmp &= 0x7; } while (tmp != 0x2); @@ -125,7 +125,7 @@ static void set_apll(unsigned int index) do { cpu_relax(); - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU); tmp &= (0x7 << 16); } while (tmp != (0x1 << 16)); } diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c index 21a90ed7f3d8..a09e609c7763 100644 --- a/drivers/cpufreq/exynos5440-cpufreq.c +++ b/drivers/cpufreq/exynos5440-cpufreq.c @@ -155,7 +155,7 @@ static int init_div_table(void) tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT) | ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT)); - __raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * + writel_relaxed(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * (pos - freq_tbl)); } @@ -169,17 +169,17 @@ static void exynos_enable_dvfs(unsigned int cur_frequency) struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table; struct cpufreq_frequency_table *pos; /* Disable DVFS */ - __raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL); + writel_relaxed(0, dvfs_info->base + XMU_DVFS_CTRL); /* Enable PSTATE Change Event */ - tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN); + tmp = readl_relaxed(dvfs_info->base + XMU_PMUEVTEN); tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN); + writel_relaxed(tmp, dvfs_info->base + XMU_PMUEVTEN); /* Enable PSTATE Change IRQ */ - tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN); + tmp = readl_relaxed(dvfs_info->base + XMU_PMUIRQEN); tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN); + writel_relaxed(tmp, dvfs_info->base + XMU_PMUIRQEN); /* Set initial performance index */ cpufreq_for_each_entry(pos, freq_table) @@ -197,14 +197,14 @@ static void exynos_enable_dvfs(unsigned int cur_frequency) cur_frequency); for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) { - tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); + tmp = readl_relaxed(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT); tmp |= ((pos - freq_table) << C0_3_PSTATE_NEW_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); + writel_relaxed(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); } /* Enable DVFS */ - __raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT, + writel_relaxed(1 << XMU_DVFS_CTRL_EN_SHIFT, dvfs_info->base + XMU_DVFS_CTRL); } @@ -223,11 +223,11 @@ static int exynos_target(struct cpufreq_policy *policy, unsigned int index) /* Set the target frequency in all C0_3_PSTATE register */ for_each_cpu(i, policy->cpus) { - tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4); + tmp = readl_relaxed(dvfs_info->base + XMU_C0_3_PSTATE + i * 4); tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT); tmp |= (index << C0_3_PSTATE_NEW_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4); + writel_relaxed(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4); } mutex_unlock(&cpufreq_lock); return 0; @@ -246,7 +246,7 @@ static void exynos_cpufreq_work(struct work_struct *work) mutex_lock(&cpufreq_lock); freqs.old = policy->cur; - cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS); + cur_pstate = readl_relaxed(dvfs_info->base + XMU_P_STATUS); if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1) index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK; else @@ -270,9 +270,9 @@ static irqreturn_t exynos_cpufreq_irq(int irq, void *id) { unsigned int tmp; - tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ); + tmp = readl_relaxed(dvfs_info->base + XMU_PMUIRQ); if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) { - __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ); + writel_relaxed(tmp, dvfs_info->base + XMU_PMUIRQ); disable_irq_nosync(irq); schedule_work(&dvfs_info->irq_work); } diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index 7c288ba4dc87..6cf65636ef9c 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -47,10 +47,10 @@ int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, int shift = off * 2; u32 pup; - pup = __raw_readl(reg); + pup = readl_relaxed(reg); pup &= ~(3 << shift); pup |= pull << shift; - __raw_writel(pup, reg); + writel_relaxed(pup, reg); return 0; } @@ -60,7 +60,7 @@ samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, { void __iomem *reg = chip->base + 0x08; int shift = off * 2; - u32 pup = __raw_readl(reg); + u32 pup = readl_relaxed(reg); pup >>= shift; pup &= 0x3; @@ -113,7 +113,7 @@ static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip, samsung_gpio_pull_t updown) { void __iomem *reg = chip->base + 0x08; - u32 pup = __raw_readl(reg); + u32 pup = readl_relaxed(reg); if (pull == updown) pup &= ~(1 << off); @@ -122,7 +122,7 @@ static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip, else return -EINVAL; - __raw_writel(pup, reg); + writel_relaxed(pup, reg); return 0; } @@ -131,7 +131,7 @@ static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip samsung_gpio_pull_t updown) { void __iomem *reg = chip->base + 0x08; - u32 pup = __raw_readl(reg); + u32 pup = readl_relaxed(reg); pup &= (1 << off); return pup ? S3C_GPIO_PULL_NONE : updown; @@ -190,10 +190,10 @@ static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip, cfg <<= shift; } - con = __raw_readl(reg); + con = readl_relaxed(reg); con &= ~(0x3 << shift); con |= cfg; - __raw_writel(con, reg); + writel_relaxed(con, reg); return 0; } @@ -213,7 +213,7 @@ static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip, { u32 con; - con = __raw_readl(chip->base); + con = readl_relaxed(chip->base); con >>= off * 2; con &= 3; @@ -253,10 +253,10 @@ static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip, cfg <<= shift; } - con = __raw_readl(reg); + con = readl_relaxed(reg); con &= ~(0xf << shift); con |= cfg; - __raw_writel(con, reg); + writel_relaxed(con, reg); return 0; } @@ -283,7 +283,7 @@ static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip, if (off < 8 && chip->chip.ngpio > 8) reg -= 4; - con = __raw_readl(reg); + con = readl_relaxed(reg); con >>= shift; con &= 0xf; @@ -321,10 +321,10 @@ static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip, cfg <<= shift; } - con = __raw_readl(reg); + con = readl_relaxed(reg); con &= ~(0x1 << shift); con |= cfg; - __raw_writel(con, reg); + writel_relaxed(con, reg); return 0; } @@ -346,7 +346,7 @@ static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip, { u32 con; - con = __raw_readl(chip->base); + con = readl_relaxed(chip->base); con >>= off; con &= 1; con++; @@ -437,10 +437,10 @@ static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset) samsung_gpio_lock(ourchip, flags); - con = __raw_readl(base + 0x00); + con = readl_relaxed(base + 0x00); con &= ~(3 << (offset * 2)); - __raw_writel(con, base + 0x00); + writel_relaxed(con, base + 0x00); samsung_gpio_unlock(ourchip, flags); return 0; @@ -457,18 +457,18 @@ static int samsung_gpiolib_2bit_output(struct gpio_chip *chip, samsung_gpio_lock(ourchip, flags); - dat = __raw_readl(base + 0x04); + dat = readl_relaxed(base + 0x04); dat &= ~(1 << offset); if (value) dat |= 1 << offset; - __raw_writel(dat, base + 0x04); + writel_relaxed(dat, base + 0x04); - con = __raw_readl(base + 0x00); + con = readl_relaxed(base + 0x00); con &= ~(3 << (offset * 2)); con |= 1 << (offset * 2); - __raw_writel(con, base + 0x00); - __raw_writel(dat, base + 0x04); + writel_relaxed(con, base + 0x00); + writel_relaxed(dat, base + 0x04); samsung_gpio_unlock(ourchip, flags); return 0; @@ -497,12 +497,12 @@ static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, void __iomem *base = ourchip->base; unsigned long con; - con = __raw_readl(base + GPIOCON_OFF); + con = readl_relaxed(base + GPIOCON_OFF); if (ourchip->bitmap_gpio_int & BIT(offset)) con |= 0xf << con_4bit_shift(offset); else con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + GPIOCON_OFF); + writel_relaxed(con, base + GPIOCON_OFF); pr_debug("%s: %p: CON now %08lx\n", __func__, base, con); @@ -517,20 +517,20 @@ static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, unsigned long con; unsigned long dat; - con = __raw_readl(base + GPIOCON_OFF); + con = readl_relaxed(base + GPIOCON_OFF); con &= ~(0xf << con_4bit_shift(offset)); con |= 0x1 << con_4bit_shift(offset); - dat = __raw_readl(base + GPIODAT_OFF); + dat = readl_relaxed(base + GPIODAT_OFF); if (value) dat |= 1 << offset; else dat &= ~(1 << offset); - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, base + GPIOCON_OFF); - __raw_writel(dat, base + GPIODAT_OFF); + writel_relaxed(dat, base + GPIODAT_OFF); + writel_relaxed(con, base + GPIOCON_OFF); + writel_relaxed(dat, base + GPIODAT_OFF); pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); @@ -572,9 +572,9 @@ static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, else regcon -= 4; - con = __raw_readl(regcon); + con = readl_relaxed(regcon); con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); + writel_relaxed(con, regcon); pr_debug("%s: %p: CON %08lx\n", __func__, base, con); @@ -596,20 +596,20 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, else regcon -= 4; - con = __raw_readl(regcon); + con = readl_relaxed(regcon); con &= ~(0xf << con_4bit_shift(con_offset)); con |= 0x1 << con_4bit_shift(con_offset); - dat = __raw_readl(base + GPIODAT_OFF); + dat = readl_relaxed(base + GPIODAT_OFF); if (value) dat |= 1 << offset; else dat &= ~(1 << offset); - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, regcon); - __raw_writel(dat, base + GPIODAT_OFF); + writel_relaxed(dat, base + GPIODAT_OFF); + writel_relaxed(con, regcon); + writel_relaxed(dat, base + GPIODAT_OFF); pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); @@ -635,19 +635,19 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, local_irq_save(flags); - con = __raw_readl(base + 0x00); - dat = __raw_readl(base + 0x04); + con = readl_relaxed(base + 0x00); + dat = readl_relaxed(base + 0x04); dat &= ~(1 << offset); if (value) dat |= 1 << offset; - __raw_writel(dat, base + 0x04); + writel_relaxed(dat, base + 0x04); con &= ~(1 << offset); - __raw_writel(con, base + 0x00); - __raw_writel(dat, base + 0x04); + writel_relaxed(con, base + 0x00); + writel_relaxed(dat, base + 0x04); local_irq_restore(flags); return 0; @@ -664,11 +664,11 @@ static void samsung_gpiolib_set(struct gpio_chip *chip, samsung_gpio_lock(ourchip, flags); - dat = __raw_readl(base + 0x04); + dat = readl_relaxed(base + 0x04); dat &= ~(1 << offset); if (value) dat |= 1 << offset; - __raw_writel(dat, base + 0x04); + writel_relaxed(dat, base + 0x04); samsung_gpio_unlock(ourchip, flags); } @@ -678,7 +678,7 @@ static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset) struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); unsigned long val; - val = __raw_readl(ourchip->base + 0x04); + val = readl_relaxed(ourchip->base + 0x04); val >>= offset; val &= 1; @@ -1316,10 +1316,10 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) unsigned long misccr; local_irq_save(flags); - misccr = __raw_readl(S3C24XX_MISCCR); + misccr = readl_relaxed(S3C24XX_MISCCR); misccr &= ~clear; misccr ^= change; - __raw_writel(misccr, S3C24XX_MISCCR); + writel_relaxed(misccr, S3C24XX_MISCCR); local_irq_restore(flags); return misccr; diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index 5945223b73fa..e176b4fd0803 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -50,14 +50,14 @@ static void combiner_mask_irq(struct irq_data *data) { u32 mask = 1 << (data->hwirq % 32); - __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); + writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); } static void combiner_unmask_irq(struct irq_data *data) { u32 mask = 1 << (data->hwirq % 32); - __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); + writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET); } static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) @@ -70,7 +70,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); - status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); + status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS); spin_unlock(&irq_controller_lock); status &= chip_data->irq_mask; @@ -131,7 +131,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data, combiner_data->parent_irq = irq; /* Disable all interrupts */ - __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); + writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); } static int combiner_irq_domain_xlate(struct irq_domain *d, diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 1e0d9b8c48c9..ee7c37502d30 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -85,6 +85,42 @@ static void dbg(const char *fmt, ...) #define S3C24XX_TX_DMA 2 #define S3C24XX_RX_PIO 1 #define S3C24XX_RX_DMA 2 + +#ifndef CONFIG_CPU_BIG_ENDIAN /* little endian */ +static inline void __hw_set_bit(int nr, volatile unsigned long *addr) +{ + __set_bit(nr, addr); +} + +static inline void __hw_clear_bit(int nr, volatile unsigned long *addr) +{ + __clear_bit(nr, addr); +} +#else +static inline void __hw_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long val = le32_to_cpu(*p); + + val |= mask; + + *p = cpu_to_le32(val); +} + +static inline void __hw_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + unsigned long val = le32_to_cpu(*p); + + val &= ~mask; + + *p = cpu_to_le32(val); +} +#endif + /* macros to change one thing to another */ #define tx_enabled(port) ((port)->unused[0]) @@ -170,7 +206,7 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port) return; if (s3c24xx_serial_has_interrupt_mask(port)) - __set_bit(S3C64XX_UINTM_TXD, + __hw_set_bit(S3C64XX_UINTM_TXD, portaddrl(port, S3C64XX_UINTM)); else disable_irq_nosync(ourport->tx_irq); @@ -236,7 +272,7 @@ static void enable_tx_dma(struct s3c24xx_uart_port *ourport) /* Mask Tx interrupt */ if (s3c24xx_serial_has_interrupt_mask(port)) - __set_bit(S3C64XX_UINTM_TXD, + __hw_set_bit(S3C64XX_UINTM_TXD, portaddrl(port, S3C64XX_UINTM)); else disable_irq_nosync(ourport->tx_irq); @@ -270,7 +306,7 @@ static void enable_tx_pio(struct s3c24xx_uart_port *ourport) /* Unmask Tx interrupt */ if (s3c24xx_serial_has_interrupt_mask(port)) - __clear_bit(S3C64XX_UINTM_TXD, + __hw_clear_bit(S3C64XX_UINTM_TXD, portaddrl(port, S3C64XX_UINTM)); else enable_irq(ourport->tx_irq); @@ -424,7 +460,7 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port) if (rx_enabled(port)) { dbg("s3c24xx_serial_stop_rx: port=%p\n", port); if (s3c24xx_serial_has_interrupt_mask(port)) - __set_bit(S3C64XX_UINTM_RXD, + __hw_set_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM)); else disable_irq_nosync(ourport->rx_irq); @@ -792,7 +828,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) if (uart_circ_empty(xmit)) s3c24xx_serial_stop_tx(port); -out: + out: spin_unlock_irqrestore(&port->lock, flags); return IRQ_HANDLED; } @@ -1086,7 +1122,7 @@ static int s3c64xx_serial_startup(struct uart_port *port) spin_unlock_irqrestore(&port->lock, flags); /* Enable Rx Interrupt */ - __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM)); + __hw_clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM)); dbg("s3c64xx_serial_startup ok\n"); return ret; diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h index fc5deaa4f382..8818bddb0e18 100644 --- a/drivers/tty/serial/samsung.h +++ b/drivers/tty/serial/samsung.h @@ -118,9 +118,9 @@ struct s3c24xx_uart_port { ((unsigned long *)(unsigned long)((port)->membase + (reg))) #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg))) -#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) +#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg)) -#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) +#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) #endif diff --git a/fs/nfs/nfsroot.c b/fs/nfs/nfsroot.c index 9bc9f04fb7f6..82937437e524 100644 --- a/fs/nfs/nfsroot.c +++ b/fs/nfs/nfsroot.c @@ -198,11 +198,17 @@ static int __init root_nfs_parse_options(char *incoming, char *exppath, /* * @incoming now points to the rest of the string; if it * contains something, append it to our root options buffer + * (but first make sure to delete any extraneous trailing + * options passed in on the boot command line) */ - if (incoming != NULL && *incoming != '\0') + if (incoming != NULL && *incoming != '\0') { + p = strpbrk(incoming, " "); + if ( p != NULL ) + *p = '\0'; if (root_nfs_cat(nfs_root_options, incoming, sizeof(nfs_root_options))) return -1; + } return 0; } diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index 29975c73a953..bf0c539ff26a 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -413,11 +413,11 @@ static inline map_word inline_map_read(struct map_info *map, unsigned long ofs) map_word r; if (map_bankwidth_is_1(map)) - r.x[0] = __raw_readb(map->virt + ofs); + r.x[0] = readb_relaxed(map->virt + ofs); else if (map_bankwidth_is_2(map)) - r.x[0] = __raw_readw(map->virt + ofs); + r.x[0] = readw_relaxed(map->virt + ofs); else if (map_bankwidth_is_4(map)) - r.x[0] = __raw_readl(map->virt + ofs); + r.x[0] = readl_relaxed(map->virt + ofs); #if BITS_PER_LONG >= 64 else if (map_bankwidth_is_8(map)) r.x[0] = __raw_readq(map->virt + ofs); @@ -433,11 +433,11 @@ static inline map_word inline_map_read(struct map_info *map, unsigned long ofs) static inline void inline_map_write(struct map_info *map, const map_word datum, unsigned long ofs) { if (map_bankwidth_is_1(map)) - __raw_writeb(datum.x[0], map->virt + ofs); + writeb_relaxed(datum.x[0], map->virt + ofs); else if (map_bankwidth_is_2(map)) - __raw_writew(datum.x[0], map->virt + ofs); + writew_relaxed(datum.x[0], map->virt + ofs); else if (map_bankwidth_is_4(map)) - __raw_writel(datum.x[0], map->virt + ofs); + writel_relaxed(datum.x[0], map->virt + ofs); #if BITS_PER_LONG >= 64 else if (map_bankwidth_is_8(map)) __raw_writeq(datum.x[0], map->virt + ofs); diff --git a/include/linux/tick.h b/include/linux/tick.h index f8492da57ad3..4191b5623a28 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -134,6 +134,12 @@ static inline bool tick_nohz_full_cpu(int cpu) return cpumask_test_cpu(cpu, tick_nohz_full_mask); } +static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) +{ + if (tick_nohz_full_enabled()) + cpumask_or(mask, mask, tick_nohz_full_mask); +} + extern void __tick_nohz_full_check(void); extern void tick_nohz_full_kick(void); extern void tick_nohz_full_kick_cpu(int cpu); @@ -142,6 +148,7 @@ extern void __tick_nohz_task_switch(struct task_struct *tsk); #else static inline bool tick_nohz_full_enabled(void) { return false; } static inline bool tick_nohz_full_cpu(int cpu) { return false; } +static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) { } static inline void __tick_nohz_full_check(void) { } static inline void tick_nohz_full_kick_cpu(int cpu) { } static inline void tick_nohz_full_kick(void) { } diff --git a/kernel/events/core.c b/kernel/events/core.c index e1af58e23bee..8aea4c9f7260 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4235,12 +4235,18 @@ static void calc_timer_values(struct perf_event *event, *running = ctx_time - event->tstamp_running; } +void __weak arch_perf_uspace_access(void *enable) +{ +} + static void perf_event_init_userpage(struct perf_event *event) { struct perf_event_mmap_page *userpg; struct ring_buffer *rb; + int enable = 1; rcu_read_lock(); + on_each_cpu(arch_perf_uspace_access, (void *)&enable, true); rb = rcu_dereference(event->rb); if (!rb) goto unlock; @@ -4461,6 +4467,7 @@ static void perf_mmap_open(struct vm_area_struct *vma) static void perf_mmap_close(struct vm_area_struct *vma) { struct perf_event *event = vma->vm_file->private_data; + int disable = 0; struct ring_buffer *rb = ring_buffer_get(event); struct user_struct *mmap_user = rb->mmap_user; @@ -4553,6 +4560,8 @@ again: out_put: ring_buffer_put(rb); /* could be last */ + if (!atomic_read(&rb->mmap_count)) + on_each_cpu(arch_perf_uspace_access, (void *)&disable, true); } static const struct vm_operations_struct perf_mmap_vmops = { diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 4d870eb6086b..a8a1bab4e595 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -2516,6 +2516,8 @@ void scheduler_tick(void) } #ifdef CONFIG_NO_HZ_FULL +static u32 sched_tick_max_deferment = HZ; + /** * scheduler_tick_max_deferment * @@ -2534,13 +2536,25 @@ u64 scheduler_tick_max_deferment(void) struct rq *rq = this_rq(); unsigned long next, now = ACCESS_ONCE(jiffies); - next = rq->last_sched_tick + HZ; + if (sched_tick_max_deferment == -1) + return KTIME_MAX; + + next = rq->last_sched_tick + sched_tick_max_deferment; if (time_before_eq(next, now)) return 0; return jiffies_to_nsecs(next - now); } + +static __init int sched_nohz_full_init_debug(void) +{ + debugfs_create_u32("sched_tick_max_deferment", 0644, NULL, + &sched_tick_max_deferment); + + return 0; +} +late_initcall(sched_nohz_full_init_debug); #endif notrace unsigned long get_parent_ip(unsigned long addr) @@ -7047,6 +7061,9 @@ void __init sched_init_smp(void) alloc_cpumask_var(&non_isolated_cpus, GFP_KERNEL); alloc_cpumask_var(&fallback_doms, GFP_KERNEL); + /* nohz_full won't take effect without isolating the cpus. */ + tick_nohz_full_add_cpus_to(cpu_isolated_map); + sched_init_numa(); /* diff --git a/linaro/configs/android.conf b/linaro/configs/android.conf index f1aefaebcc93..54b3526e189a 100644 --- a/linaro/configs/android.conf +++ b/linaro/configs/android.conf @@ -45,3 +45,8 @@ CONFIG_SECURITY_NETWORK=y CONFIG_LSM_MMAP_MIN_ADDR=4096 CONFIG_SECURITY_SELINUX=y CONFIG_EXT4_FS_SECURITY=y +CONFIG_ADF=y +CONFIG_ADF_FBDEV=y +CONFIG_ADF_MEMBLOCK=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_TUN=y diff --git a/linaro/configs/arndale.conf b/linaro/configs/arndale.conf index 6d6f6de3024f..35a69609eaf2 100644 --- a/linaro/configs/arndale.conf +++ b/linaro/configs/arndale.conf @@ -7,7 +7,7 @@ CONFIG_S3C_LOWLEVEL_UART_PORT=2 CONFIG_ARCH_EXYNOS5=y CONFIG_VMSPLIT_2G=y CONFIG_NR_CPUS=2 -# CONFIG_THUMB2_KERNEL is not set +CONFIG_THUMB2_KERNEL=y CONFIG_HIGHMEM=y # CONFIG_COMPACTION is not set CONFIG_ARM_APPENDED_DTB=y diff --git a/linaro/configs/big-LITTLE-IKS.conf b/linaro/configs/big-LITTLE-IKS.conf index eccb00f851e0..b067fde86eaa 100644 --- a/linaro/configs/big-LITTLE-IKS.conf +++ b/linaro/configs/big-LITTLE-IKS.conf @@ -1,4 +1,5 @@ CONFIG_BIG_LITTLE=y CONFIG_BL_SWITCHER=y CONFIG_ARM_DT_BL_CPUFREQ=y +CONFIG_ARM_VEXPRESS_BL_CPUFREQ=y CONFIG_CPU_FREQ_GOV_USERSPACE=y diff --git a/linaro/configs/distribution.conf b/linaro/configs/distribution.conf index 6329bd98cab4..3e07a2cb1a05 100644 --- a/linaro/configs/distribution.conf +++ b/linaro/configs/distribution.conf @@ -1,3 +1,4 @@ +# CONFIG_LOCALVERSION_AUTO is not set CONFIG_FHANDLE=y CONFIG_CGROUPS=y CONFIG_NAMESPACES=y @@ -6,7 +7,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 CONFIG_SECCOMP=y CONFIG_CC_STACKPROTECTOR_REGULAR=y CONFIG_SYN_COOKIES=y -CONFIG_IPV6=m +CONFIG_IPV6=y CONFIG_NETLABEL=y CONFIG_BRIDGE_NETFILTER=y CONFIG_NF_CONNTRACK=m @@ -43,6 +44,7 @@ CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE=m +CONFIG_TUN=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -63,3 +65,7 @@ CONFIG_SECURITY_SMACK=y CONFIG_SECURITY_APPARMOR=y CONFIG_DEFAULT_SECURITY_APPARMOR=y CONFIG_OF_SELFTEST=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y diff --git a/linaro/configs/kvm-guest.conf b/linaro/configs/kvm-guest.conf index cf174f89d043..7ff6fb422582 100644 --- a/linaro/configs/kvm-guest.conf +++ b/linaro/configs/kvm-guest.conf @@ -13,5 +13,7 @@ CONFIG_VIRTIO=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_RING=y CONFIG_VIRTUALIZATION=y # CONFIG_THUMB2_KERNEL is not set diff --git a/linaro/configs/kvm-host.conf b/linaro/configs/kvm-host.conf index d0fb67b35175..4912bb4acec9 100644 --- a/linaro/configs/kvm-host.conf +++ b/linaro/configs/kvm-host.conf @@ -1,11 +1,15 @@ CONFIG_VIRTUALIZATION=y CONFIG_ARM_LPAE=y CONFIG_ARM_VIRT_EXT=y +CONFIG_HAVE_KVM=y CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_KVM_ARM_HOST=y CONFIG_KVM_ARM_MAX_VCPUS=4 CONFIG_KVM_ARM_TIMER=y CONFIG_KVM_ARM_VGIC=y +CONFIG_KVM_AMD=y +CONFIG_KVM_INTEL=y CONFIG_KVM_MMIO=y CONFIG_KVM=y CONFIG_BLK_DEV_NBD=m diff --git a/linaro/configs/linaro-base.conf b/linaro/configs/linaro-base.conf index 1988c42cedea..117810318116 100644 --- a/linaro/configs/linaro-base.conf +++ b/linaro/configs/linaro-base.conf @@ -6,6 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y CONFIG_EMBEDDED=y +CONFIG_HOTPLUG=y CONFIG_PERF_EVENTS=y CONFIG_SLAB=y CONFIG_PROFILING=y @@ -70,6 +71,7 @@ CONFIG_JFFS2_RUBIN=y CONFIG_CRAMFS=y CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y +CONFIG_NFS_V2=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y @@ -92,9 +94,25 @@ CONFIG_HW_PERF_EVENTS=y CONFIG_FUNCTION_TRACER=y CONFIG_ENABLE_DEFAULT_TRACERS=y CONFIG_PROC_DEVICETREE=y +CONFIG_JUMP_LABEL=y +CONFIG_STRICT_DEVMEM=y +CONFIG_KGDB=y +CONFIG_KGDB_TESTS=y +CONFIG_OF_IDLE_STATES=y +CONFIG_FTRACE=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_STACK_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_MAILBOX=y CONFIG_AUDIT=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_IP_NF_SECURITY=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y +CONFIG_LSM_MMAP_MIN_ADDR=4096 CONFIG_SECURITY_SELINUX=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS_SECURITY=y @@ -113,3 +131,9 @@ CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_CAPABILITIES=y CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_DEBUG_INFO=y +CONFIG_FANOTIFY=y +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_TORTURE_TEST_RUNNABLE=n +CONFIG_UIO=m diff --git a/linaro/configs/no_hz_full.conf b/linaro/configs/no_hz_full.conf new file mode 100644 index 000000000000..672907721bf7 --- /dev/null +++ b/linaro/configs/no_hz_full.conf @@ -0,0 +1,17 @@ +### config fragment to add NO_HZ_FULL support +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ_FULL_ALL=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_IDLE=n +CONFIG_HZ_PERIODIC=n +CONFIG_RCU_USER_QS=y +CONFIG_RCU_NOCB_CPU=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_CONTEXT_TRACKING_FORCE=y +CONFIG_IRQ_WORK=y +CONFIG_CPUSETS=y +CONFIG_CGROUPS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_THUMB2_KERNEL=y diff --git a/linaro/configs/omap4.conf b/linaro/configs/omap4.conf index 50fb9d9cb5b5..d0a2b808ff12 100644 --- a/linaro/configs/omap4.conf +++ b/linaro/configs/omap4.conf @@ -9,6 +9,8 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_GPIO_PCA953X=y CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_MUX_DEBUG=y +CONFIG_ARCH_OMAP3=y +CONFIG_ARCH_OMAP4=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SOC_OMAP5=y # CONFIG_ARCH_OMAP2 is not set diff --git a/linaro/configs/ovs.conf b/linaro/configs/ovs.conf new file mode 100644 index 000000000000..9d11399f95ab --- /dev/null +++ b/linaro/configs/ovs.conf @@ -0,0 +1,11 @@ +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_BRIDGE=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_HFSC=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_OPENVSWITCH=m +CONFIG_TUN=y diff --git a/linaro/configs/preemption.conf b/linaro/configs/preemption.conf new file mode 100644 index 000000000000..6f19eadbbdce --- /dev/null +++ b/linaro/configs/preemption.conf @@ -0,0 +1,2 @@ +CONFIG_PREEMPT=y +# CONFIG_CPU_FREQ is not set diff --git a/linaro/configs/ubuntu-minimal.conf b/linaro/configs/ubuntu-minimal.conf new file mode 120000 index 000000000000..794e82f3bc17 --- /dev/null +++ b/linaro/configs/ubuntu-minimal.conf @@ -0,0 +1 @@ +distribution.conf
\ No newline at end of file diff --git a/linaro/configs/vexpress-tuning.conf b/linaro/configs/vexpress-tuning.conf new file mode 100644 index 000000000000..adea6cc66ded --- /dev/null +++ b/linaro/configs/vexpress-tuning.conf @@ -0,0 +1 @@ +# CONFIG_PROVE_LOCKING is not set diff --git a/linaro/configs/x86.conf b/linaro/configs/x86.conf new file mode 100644 index 000000000000..df67e4445854 --- /dev/null +++ b/linaro/configs/x86.conf @@ -0,0 +1,4 @@ +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_E1000E=y +CONFIG_IXGBE=y diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index d9b1fef0c67e..670e61defcf3 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -13,6 +13,8 @@ endif ifeq ($(quiet),silent_) silent := -s +else +silent := endif # We need this, in case the user has it in its environment |