diff options
| -rw-r--r-- | arch/arm/mach-omap2/am35xx-emac.c | 90 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clock3xxx_data.c | 28 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/am35xx.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 143 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prcm-common.h | 4 |
6 files changed, 200 insertions, 71 deletions
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 447682c4e11c..2c90ac686686 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -15,27 +15,13 @@ * General Public License for more details. */ -#include <linux/clk.h> +#include <linux/err.h> #include <linux/davinci_emac.h> -#include <linux/platform_device.h> -#include <plat/irqs.h> +#include <asm/system.h> +#include <plat/omap_device.h> #include <mach/am35xx.h> - #include "control.h" - -static struct mdio_platform_data am35xx_emac_mdio_pdata; - -static struct resource am35xx_emac_mdio_resources[] = { - DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K), -}; - -static struct platform_device am35xx_emac_mdio_device = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(am35xx_emac_mdio_resources), - .resource = am35xx_emac_mdio_resources, - .dev.platform_data = &am35xx_emac_mdio_pdata, -}; +#include "am35xx-emac.h" static void am35xx_enable_emac_int(void) { @@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = { .interrupt_disable = am35xx_disable_emac_int, }; -static struct resource am35xx_emac_resources[] = { - DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000), - DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ), - DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ), - DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ), - DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ), -}; +static struct mdio_platform_data am35xx_mdio_pdata; -static struct platform_device am35xx_emac_device = { - .name = "davinci_emac", - .id = -1, - .num_resources = ARRAY_SIZE(am35xx_emac_resources), - .resource = am35xx_emac_resources, - .dev = { - .platform_data = &am35xx_emac_pdata, - }, -}; +static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh, + void *pdata, int pdata_len) +{ + struct platform_device *pdev; + + pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len, + NULL, 0, false); + if (IS_ERR(pdev)) { + WARN(1, "Can't build omap_device for %s:%s.\n", + oh->class->name, oh->name); + return PTR_ERR(pdev); + } + + return 0; +} void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) { + struct omap_hwmod *oh; u32 v; - int err; + int ret; - am35xx_emac_pdata.rmii_en = rmii_en; - am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq; - err = platform_device_register(&am35xx_emac_device); - if (err) { - pr_err("AM35x: failed registering EMAC device: %d\n", err); + oh = omap_hwmod_lookup("davinci_mdio"); + if (!oh) { + pr_err("Could not find davinci_mdio hwmod\n"); + return; + } + + am35xx_mdio_pdata.bus_freq = mdio_bus_freq; + + ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata, + sizeof(am35xx_mdio_pdata)); + if (ret) { + pr_err("Could not build davinci_mdio hwmod device\n"); return; } - err = platform_device_register(&am35xx_emac_mdio_device); - if (err) { - pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err); - platform_device_unregister(&am35xx_emac_device); + oh = omap_hwmod_lookup("davinci_emac"); + if (!oh) { + pr_err("Could not find davinci_emac hwmod\n"); + return; + } + + am35xx_emac_pdata.rmii_en = rmii_en; + + ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata, + sizeof(am35xx_emac_pdata)); + if (ret) { + pr_err("Could not build davinci_emac hwmod device\n"); return; } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 1efdec236ae8..a67aaa97dcd8 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -2490,13 +2490,13 @@ static struct clk uart4_fck = { }; static struct clk uart4_fck_am35xx = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_UART4_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, + .name = "uart4_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = AM35XX_EN_UART4_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, }; static struct clk gpt2_fck = { @@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = { }; /* - * The UART1/2 functional clock acts as the functional - * clock for UART4. No separate fclk control available. + * The UART1/2 functional clock acts as the functional clock for + * UART4. No separate fclk control available. XXX Well now we have a + * uart4_fck that is apparently used as the UART4 functional clock, + * but it also seems that uart1_fck or uart2_fck are still needed, at + * least for UART4 softresets to complete. This really needs + * clarification. */ static struct clk uart4_ick_am35xx = { .name = "uart4_ick", @@ -3474,12 +3478,12 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), - CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX), + CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), - CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), - CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), + CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 8083a8cdc55f..766338fe4d34 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -169,8 +169,6 @@ /* AM35XX specific CM_ICLKEN1_CORE bits */ #define AM35XX_EN_IPSS_MASK (1 << 4) #define AM35XX_EN_IPSS_SHIFT 4 -#define AM35XX_EN_UART4_MASK (1 << 23) -#define AM35XX_EN_UART4_SHIFT 23 /* CM_ICLKEN2_CORE */ #define OMAP3430_EN_PKA_MASK (1 << 4) @@ -207,6 +205,8 @@ #define OMAP3430_ST_DES2_MASK (1 << 26) #define OMAP3430_ST_MSPRO_SHIFT 23 #define OMAP3430_ST_MSPRO_MASK (1 << 23) +#define AM35XX_ST_UART4_SHIFT 23 +#define AM35XX_ST_UART4_MASK (1 << 23) #define OMAP3430_ST_HDQ_SHIFT 22 #define OMAP3430_ST_HDQ_MASK (1 << 22) #define OMAP3430ES1_ST_FAC_SHIFT 8 diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h index f1e13d1ca5e7..95594495fcf6 100644 --- a/arch/arm/mach-omap2/include/mach/am35xx.h +++ b/arch/arm/mach-omap2/include/mach/am35xx.h @@ -36,6 +36,8 @@ #define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) #define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) #define AM35XX_EMAC_MDIO_OFFSET (0x30000) +#define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \ + AM35XX_EMAC_MDIO_OFFSET) #define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) #define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ AM3517_EMAC_CNTRL_RAM_OFFSET) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b26d3c9bca16..a8653af19697 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -527,11 +527,27 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { { .irq = INT_35XX_UART4_IRQ, }, + { .irq = -1 } }; static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, + { .dma_req = -1 } +}; + +/* + * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or + * uart2_fck being enabled. So we add uart1_fck as an optional clock, + * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really + * should not be needed. The functional clock structure of the AM35xx + * UART4 is extremely unclear and opaque; it is unclear what the role + * of uart1/2_fck is for the UART4. Any clarification from either + * empirical testing or the AM3505/3517 hardware designers would be + * most welcome. + */ +static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { + { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, }; static struct omap_hwmod am35xx_uart4_hwmod = { @@ -543,11 +559,14 @@ static struct omap_hwmod am35xx_uart4_hwmod = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART4_SHIFT, + .module_bit = AM35XX_EN_UART4_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, + .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, }, }, + .opt_clks = am35xx_uart4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap2_uart_class, }; @@ -1638,25 +1657,20 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { /* usb_otg_hs */ static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 71 }, { .irq = -1 } }; static struct omap_hwmod_class am35xx_usbotg_class = { .name = "am35xx_usbotg", - .sysc = NULL, }; static struct omap_hwmod am35xx_usbhsotg_hwmod = { .name = "am35x_otg_hs", .mpu_irqs = am35xx_usbhsotg_mpu_irqs, - .main_clk = NULL, - .prcm = { - .omap2 = { - }, - }, + .main_clk = "hsotgusb_fck", .class = &am35xx_usbotg_class, + .flags = HWMOD_NO_IDLEST, }; /* MMC/SD/SDIO common */ @@ -2097,9 +2111,10 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { .master = &am35xx_usbhsotg_hwmod, .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", + .clk = "hsotgusb_ick", .user = OCP_USER_MPU, }; + /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .master = &omap3xxx_l4_core_hwmod, @@ -2243,6 +2258,7 @@ static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, }, + { } }; static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { @@ -2393,7 +2409,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { .master = &omap3xxx_l4_core_hwmod, .slave = &am35xx_usbhsotg_hwmod, - .clk = "l4_ick", + .clk = "hsotgusb_ick", .addr = am35xx_usbhsotg_addrs, .user = OCP_USER_MPU, }; @@ -3138,6 +3154,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* am35xx has Davinci MDIO & EMAC */ +static struct omap_hwmod_class am35xx_mdio_class = { + .name = "davinci_mdio", +}; + +static struct omap_hwmod am35xx_mdio_hwmod = { + .name = "davinci_mdio", + .class = &am35xx_mdio_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* + * XXX Should be connected to an IPSS hwmod, not the L3 directly; + * but this will probably require some additional hwmod core support, + * so is left as a future to-do item. + */ +static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { + .master = &am35xx_mdio_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "emac_fck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { + { + .pa_start = AM35XX_IPSS_MDIO_BASE, + .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> davinci mdio */ +/* + * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; + * but this will probably require some additional hwmod core support, + * so is left as a future to-do item. + */ +static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_mdio_hwmod, + .clk = "emac_fck", + .addr = am35xx_mdio_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { + { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ }, + { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ }, + { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ }, + { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ }, + { .irq = -1 } +}; + +static struct omap_hwmod_class am35xx_emac_class = { + .name = "davinci_emac", +}; + +static struct omap_hwmod am35xx_emac_hwmod = { + .name = "davinci_emac", + .mpu_irqs = am35xx_emac_mpu_irqs, + .class = &am35xx_emac_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* l3_core -> davinci emac interface */ +/* + * XXX Should be connected to an IPSS hwmod, not the L3 directly; + * but this will probably require some additional hwmod core support, + * so is left as a future to-do item. + */ +static struct omap_hwmod_ocp_if am35xx_emac__l3 = { + .master = &am35xx_emac_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "emac_ick", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { + { + .pa_start = AM35XX_IPSS_EMAC_BASE, + .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> davinci emac */ +/* + * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; + * but this will probably require some additional hwmod core support, + * so is left as a future to-do item. + */ +static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_emac_hwmod, + .clk = "emac_ick", + .addr = am35xx_emac_addrs, + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3266,6 +3383,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__usb_tll_hs, &omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc2, + &am35xx_mdio__l3, + &am35xx_l4_core__mdio, + &am35xx_emac__l3, + &am35xx_l4_core__emac, NULL }; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6da3ba483ad1..cc1398e8b469 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -203,8 +203,8 @@ #define OMAP3430_EN_MMC2_SHIFT 25 #define OMAP3430_EN_MMC1_MASK (1 << 24) #define OMAP3430_EN_MMC1_SHIFT 24 -#define OMAP3430_EN_UART4_MASK (1 << 23) -#define OMAP3430_EN_UART4_SHIFT 23 +#define AM35XX_EN_UART4_MASK (1 << 23) +#define AM35XX_EN_UART4_SHIFT 23 #define OMAP3430_EN_MCSPI4_MASK (1 << 21) #define OMAP3430_EN_MCSPI4_SHIFT 21 #define OMAP3430_EN_MCSPI3_MASK (1 << 20) |