diff options
Diffstat (limited to 'arch/arm/mach-exynos/pm.c')
| -rw-r--r-- | arch/arm/mach-exynos/pm.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e00025bbbe89..f429e34e7280 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -130,19 +130,19 @@ static void exynos_pm_prepare(void) } else { s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); /* Disable USE_RETENTION of JPEG_MEM_OPTION */ - tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); + tmp = readl_relaxed(EXYNOS5_JPEG_MEM_OPTION); tmp &= ~EXYNOS5_OPTION_USE_RETENTION; - __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); + writel_relaxed(tmp, EXYNOS5_JPEG_MEM_OPTION); } /* Set value of power down register for sleep mode */ exynos_sys_powerdown_conf(SYS_SLEEP); - __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); + writel_relaxed(S5P_CHECK_SLEEP, S5P_INFORM1); /* ensure at least INFORM0 has the resume address */ - __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); + writel_relaxed(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); /* Before enter central sequence mode, clock src register have to set */ @@ -187,7 +187,7 @@ static void exynos4_restore_pll(void) locktime = (3000 / pll_in_rate) * p_div; lockcnt = locktime * 10000 / (10000 / pll_in_rate); - __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); + writel_relaxed(lockcnt, EXYNOS4_EPLL_LOCK); s3c_pm_do_restore_core(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); @@ -205,7 +205,7 @@ static void exynos4_restore_pll(void) locktime = 750; lockcnt = locktime * 10000 / (10000 / pll_in_rate); - __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); + writel_relaxed(lockcnt, EXYNOS4_VPLL_LOCK); s3c_pm_do_restore_core(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -216,13 +216,13 @@ static void exynos4_restore_pll(void) do { if (epll_wait) { - pll_con = __raw_readl(EXYNOS4_EPLL_CON0); + pll_con = readl_relaxed(EXYNOS4_EPLL_CON0); if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) epll_wait = 0; } if (vpll_wait) { - pll_con = __raw_readl(EXYNOS4_VPLL_CON0); + pll_con = readl_relaxed(EXYNOS4_VPLL_CON0); if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) vpll_wait = 0; } @@ -247,9 +247,9 @@ static __init int exynos_pm_drvinit(void) /* All wakeup disable */ - tmp = __raw_readl(S5P_WAKEUP_MASK); + tmp = readl_relaxed(S5P_WAKEUP_MASK); tmp |= ((0xFF << 8) | (0x1F << 1)); - __raw_writel(tmp, S5P_WAKEUP_MASK); + writel_relaxed(tmp, S5P_WAKEUP_MASK); if (!soc_is_exynos5250()) { pll_base = clk_get(NULL, "xtal"); @@ -270,14 +270,14 @@ static int exynos_pm_suspend(void) /* Setting Central Sequence Register for power down mode */ - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION); tmp &= ~S5P_CENTRAL_LOWPWR_CFG; - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* Setting SEQ_OPTION register */ tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); - __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); + writel_relaxed(tmp, S5P_CENTRAL_SEQ_OPTION); if (!soc_is_exynos5250()) { /* Save Power control register */ @@ -304,12 +304,12 @@ static void exynos_pm_resume(void) * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* clear the wakeup state register */ - __raw_writel(0x0, S5P_WAKEUP_STAT); + writel_relaxed(0x0, S5P_WAKEUP_STAT); /* No need to perform below restore code */ goto early_wakeup; } @@ -329,13 +329,13 @@ static void exynos_pm_resume(void) /* For release retention */ - __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); - __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); - __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); - __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); - __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); - __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); - __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_GPIO_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_UART_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_MMCA_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_MMCB_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_EBIA_OPTION); + writel_relaxed((1 << 28), S5P_PAD_RET_EBIB_OPTION); if (soc_is_exynos5250()) s3c_pm_do_restore(exynos5_sys_save, @@ -354,7 +354,7 @@ static void exynos_pm_resume(void) early_wakeup: /* Clear SLEEP mode set in INFORM1 */ - __raw_writel(0x0, S5P_INFORM1); + writel_relaxed(0x0, S5P_INFORM1); return; } |