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-rw-r--r--arch/arm/include/debug/samsung.S9
-rw-r--r--arch/arm/mach-exynos/Kconfig8
-rw-r--r--arch/arm/mach-exynos/common.h4
-rw-r--r--arch/arm/mach-exynos/firmware.c2
-rw-r--r--arch/arm/mach-exynos/headsmp.S6
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c6
-rw-r--r--arch/arm/mach-exynos/platsmp.c4
-rw-r--r--arch/arm/mach-exynos/pm.c15
-rw-r--r--arch/arm/mach-exynos/pm_domains.c6
-rw-r--r--arch/arm/plat-samsung/cpu.c8
-rw-r--r--arch/arm/plat-samsung/pm-common.c8
-rw-r--r--arch/arm/plat-samsung/pm-debug.c24
-rw-r--r--arch/arm/plat-samsung/pm-gpio.c66
-rw-r--r--arch/arm/plat-samsung/wakeup-mask.c6
-rw-r--r--arch/arm/plat-samsung/watchdog-reset.c8
-rw-r--r--arch/arm64/include/asm/pmu.h1
-rw-r--r--arch/arm64/kernel/perf_event.c22
-rw-r--r--arch/x86/include/asm/io.h4
18 files changed, 130 insertions, 77 deletions
diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index 8d8d922e5e44..dc62d4ae04d0 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -9,17 +9,20 @@
* published by the Free Software Foundation.
*/
+#include <asm/assembler.h>
#include <linux/serial_s3c.h>
/* The S5PV210/S5PC110 implementations are as belows. */
.macro fifo_level_s5pv210 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
+ ARM_BE8(rev \rd, \rd)
and \rd, \rd, #S5PV210_UFSTAT_TXMASK
.endm
.macro fifo_full_s5pv210 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
+ ARM_BE8(rev \rd, \rd)
tst \rd, #S5PV210_UFSTAT_TXFULL
.endm
@@ -28,6 +31,7 @@
.macro fifo_level_s3c2440 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
+ ARM_BE8(rev \rd, \rd)
and \rd, \rd, #S3C2440_UFSTAT_TXMASK
.endm
@@ -37,6 +41,7 @@
.macro fifo_full_s3c2440 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
+ ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2440_UFSTAT_TXFULL
.endm
@@ -50,6 +55,7 @@
.macro busyuart, rd, rx
ldr \rd, [\rx, # S3C2410_UFCON]
+ ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
@@ -61,6 +67,7 @@
1001:
@ busy waiting for non fifo
ldr \rd, [\rx, # S3C2410_UTRSTAT]
+ ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
@@ -69,6 +76,7 @@
.macro waituart,rd,rx
ldr \rd, [\rx, # S3C2410_UFCON]
+ ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
@@ -80,6 +88,7 @@
1001:
@ idle waiting for non fifo
ldr \rd, [\rx, # S3C2410_UTRSTAT]
+ ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 81064cd61a0a..803c4d6eeff2 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -44,6 +44,8 @@ config ARCH_EXYNOS4
select CPU_EXYNOS4210
select GIC_NON_BANKED
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
+ select HAVE_ARM_SCU if SMP
+ select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Samsung EXYNOS4 (Cortex-A9) SoC based systems
@@ -51,6 +53,10 @@ config ARCH_EXYNOS4
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
default y
+ select ARCH_SUPPORTS_BIG_ENDIAN
+ select CLKSRC_OF
+ select HAVE_SMP
+ select USB_ARCH_HAS_XHCI
help
Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
@@ -100,6 +106,8 @@ config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
depends on ARCH_EXYNOS5
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
config SOC_EXYNOS5440
bool "SAMSUNG EXYNOS5440"
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 5f5cd562c593..52a5ccf03796 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -167,12 +167,12 @@ extern void __iomem *cpu_boot_reg_base(void);
static inline void pmu_raw_writel(u32 val, u32 offset)
{
- __raw_writel(val, pmu_base_addr + offset);
+ writel_relaxed(val, pmu_base_addr + offset);
}
static inline u32 pmu_raw_readl(u32 offset)
{
- return __raw_readl(pmu_base_addr + offset);
+ return readl_relaxed(pmu_base_addr + offset);
}
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 1bd35763f12e..46fb218d9712 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -100,7 +100,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
if (soc_is_exynos4412())
boot_reg += 4 * cpu;
- __raw_writel(boot_addr, boot_reg);
+ writel_relaxed(boot_addr, boot_reg);
return 0;
}
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index b54f9701e421..45b3006e4e58 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -11,6 +11,7 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
/*
* exynos4 specific entry point for secondary CPUs. This provides
@@ -18,6 +19,11 @@
* ready for them to initialise.
*/
ENTRY(exynos4_secondary_startup)
+ /*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it to big endian mode.
+ */
+ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 9bdf54795f05..ebdbc66a5b35 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -194,9 +194,9 @@ static void exynos_mcpm_setup_entry_point(void)
* mcpm_entry_point(). This is done during both secondary boot-up as
* well as system resume.
*/
- __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
- __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
- __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+ writel_relaxed(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
+ writel_relaxed(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
+ writel_relaxed(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
}
static struct syscore_ops exynos_mcpm_syscore_ops = {
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a825bca2a2b6..e2dcee687f1c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -321,7 +321,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
ret = PTR_ERR(boot_reg);
goto fail;
}
- __raw_writel(boot_addr, boot_reg);
+ writel_relaxed(boot_addr, boot_reg);
}
call_firmware_op(cpu_boot, core_id);
@@ -415,7 +415,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
if (IS_ERR(boot_reg))
break;
- __raw_writel(boot_addr, boot_reg);
+ writel_relaxed(boot_addr, boot_reg);
}
}
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index cc75ab448be3..f0b5cb37d9e5 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -26,6 +26,9 @@
#include <mach/map.h>
#include <plat/pm-common.h>
+#include <plat/regs-srom.h>
+
+#include <mach/map.h>
#include "common.h"
#include "exynos-pmu.h"
@@ -133,9 +136,9 @@ static void exynos_set_wakeupmask(long mask)
static void exynos_cpu_set_boot_vector(long flags)
{
- __raw_writel(virt_to_phys(exynos_cpu_resume),
+ writel_relaxed(virt_to_phys(exynos_cpu_resume),
exynos_boot_vector_addr());
- __raw_writel(flags, exynos_boot_vector_flag());
+ writel_relaxed(flags, exynos_boot_vector_flag());
}
static int exynos_aftr_finisher(unsigned long flags)
@@ -221,7 +224,7 @@ static int exynos_cpu0_enter_aftr(void)
* boot back up again, getting stuck in the
* boot rom code
*/
- if (__raw_readl(cpu_boot_reg_base()) == 0)
+ if (readl_relaxed(cpu_boot_reg_base()) == 0)
goto abort;
cpu_relax();
@@ -236,7 +239,7 @@ abort:
/*
* Set the boot vector to something non-zero
*/
- __raw_writel(virt_to_phys(exynos_cpu_resume),
+ writel_relaxed(virt_to_phys(exynos_cpu_resume),
cpu_boot_reg_base());
dsb();
@@ -251,7 +254,7 @@ abort:
/*
* Poke cpu1 out of the boot rom
*/
- __raw_writel(virt_to_phys(exynos_cpu_resume),
+ writel_relaxed(virt_to_phys(exynos_cpu_resume),
cpu_boot_reg_base());
arch_send_wakeup_ipi_mask(cpumask_of(1));
@@ -299,7 +302,7 @@ cpu1_aborted:
static void exynos_pre_enter_aftr(void)
{
- __raw_writel(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base());
+ writel_relaxed(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base());
}
static void exynos_post_enter_aftr(void)
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index a9686535f9ed..5950d0937494 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -69,12 +69,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
}
pwr = power_on ? INT_LOCAL_PWR_EN : 0;
- __raw_writel(pwr, base);
+ writel_relaxed(pwr, base);
/* Wait max 1ms */
timeout = 10;
- while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
+ while ((readl_relaxed(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
if (!timeout) {
op = (power_on) ? "enable" : "disable";
pr_err("Power domain %s %s failed\n", domain->name, op);
@@ -174,7 +174,7 @@ static __init int exynos4_pm_init_power_domain(void)
clk_put(pd->oscclk);
no_clk:
- on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
+ on = readl_relaxed(pd->base + 0x4) & INT_LOCAL_PWR_EN;
pm_genpd_init(&pd->pd, NULL, !on);
of_genpd_add_provider_simple(np, &pd->pd);
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 71333bb61013..bd12a55401e0 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -29,14 +29,14 @@ EXPORT_SYMBOL(samsung_rev);
void __init s3c64xx_init_cpu(void)
{
- samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
+ samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118);
if (!samsung_cpu_id) {
/*
* S3C6400 has the ID register in a different place,
* and needs a write before it can be read.
*/
- __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
- samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
+ writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
+ samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
}
samsung_cpu_rev = 0;
@@ -46,7 +46,7 @@ void __init s3c64xx_init_cpu(void)
void __init s5p_init_cpu(void __iomem *cpuid_addr)
{
- samsung_cpu_id = __raw_readl(cpuid_addr);
+ samsung_cpu_id = readl_relaxed(cpuid_addr);
samsung_cpu_rev = samsung_cpu_id & 0xFF;
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/plat-samsung/pm-common.c
index 515cd53372bd..6534c3ff9fe2 100644
--- a/arch/arm/plat-samsung/pm-common.c
+++ b/arch/arm/plat-samsung/pm-common.c
@@ -31,7 +31,7 @@
void s3c_pm_do_save(struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
- ptr->val = __raw_readl(ptr->reg);
+ ptr->val = readl_relaxed(ptr->reg);
S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
}
}
@@ -51,9 +51,9 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
pr_debug("restore %p (restore %08lx, was %08x)\n",
- ptr->reg, ptr->val, __raw_readl(ptr->reg));
+ ptr->reg, ptr->val, readl_relaxed(ptr->reg));
- __raw_writel(ptr->val, ptr->reg);
+ writel_relaxed(ptr->val, ptr->reg);
}
}
@@ -71,5 +71,5 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++)
- __raw_writel(ptr->val, ptr->reg);
+ writel_relaxed(ptr->val, ptr->reg);
}
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c
index 64e15da33b42..9ae05006e092 100644
--- a/arch/arm/plat-samsung/pm-debug.c
+++ b/arch/arm/plat-samsung/pm-debug.c
@@ -68,14 +68,14 @@ void s3c_pm_save_uarts(void)
void __iomem *regs = s3c_pm_uart_base();
struct pm_uart_save *save = &uart_save;
- save->ulcon = __raw_readl(regs + S3C2410_ULCON);
- save->ucon = __raw_readl(regs + S3C2410_UCON);
- save->ufcon = __raw_readl(regs + S3C2410_UFCON);
- save->umcon = __raw_readl(regs + S3C2410_UMCON);
- save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+ save->ulcon = readl_relaxed(regs + S3C2410_ULCON);
+ save->ucon = readl_relaxed(regs + S3C2410_UCON);
+ save->ufcon = readl_relaxed(regs + S3C2410_UFCON);
+ save->umcon = readl_relaxed(regs + S3C2410_UMCON);
+ save->ubrdiv = readl_relaxed(regs + S3C2410_UBRDIV);
if (!soc_is_s3c2410())
- save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+ save->udivslot = readl_relaxed(regs + S3C2443_DIVSLOT);
S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
@@ -88,12 +88,12 @@ void s3c_pm_restore_uarts(void)
s3c_pm_arch_update_uart(regs, save);
- __raw_writel(save->ulcon, regs + S3C2410_ULCON);
- __raw_writel(save->ucon, regs + S3C2410_UCON);
- __raw_writel(save->ufcon, regs + S3C2410_UFCON);
- __raw_writel(save->umcon, regs + S3C2410_UMCON);
- __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+ writel_relaxed(save->ulcon, regs + S3C2410_ULCON);
+ writel_relaxed(save->ucon, regs + S3C2410_UCON);
+ writel_relaxed(save->ufcon, regs + S3C2410_UFCON);
+ writel_relaxed(save->umcon, regs + S3C2410_UMCON);
+ writel_relaxed(save->ubrdiv, regs + S3C2410_UBRDIV);
if (!soc_is_s3c2410())
- __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+ writel_relaxed(save->udivslot, regs + S3C2443_DIVSLOT);
}
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index f9a09262f2fa..75a3d386b4d9 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -32,15 +32,15 @@
static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip)
{
- chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
- chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+ chip->pm_save[0] = readl_relaxed(chip->base + OFFS_CON);
+ chip->pm_save[1] = readl_relaxed(chip->base + OFFS_DAT);
}
static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
- u32 old_gpcon = __raw_readl(base + OFFS_CON);
- u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 old_gpcon = readl_relaxed(base + OFFS_CON);
+ u32 old_gpdat = readl_relaxed(base + OFFS_DAT);
u32 gps_gpcon = chip->pm_save[0];
u32 gps_gpdat = chip->pm_save[1];
u32 gpcon;
@@ -51,12 +51,12 @@ static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip)
/* first set all SFN bits to SFN */
gpcon = old_gpcon | gps_gpcon;
- __raw_writel(gpcon, base + OFFS_CON);
+ writel_relaxed(gpcon, base + OFFS_CON);
/* now set all the other bits */
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
+ writel_relaxed(gps_gpdat, base + OFFS_DAT);
+ writel_relaxed(gps_gpcon, base + OFFS_CON);
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
@@ -69,9 +69,9 @@ struct samsung_gpio_pm samsung_gpio_pm_1bit = {
static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip)
{
- chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
- chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
- chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+ chip->pm_save[0] = readl_relaxed(chip->base + OFFS_CON);
+ chip->pm_save[1] = readl_relaxed(chip->base + OFFS_DAT);
+ chip->pm_save[2] = readl_relaxed(chip->base + OFFS_UP);
}
/* Test whether the given masked+shifted bits of an GPIO configuration
@@ -126,8 +126,8 @@ static inline int is_out(unsigned long con)
static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
- u32 old_gpcon = __raw_readl(base + OFFS_CON);
- u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 old_gpcon = readl_relaxed(base + OFFS_CON);
+ u32 old_gpdat = readl_relaxed(base + OFFS_DAT);
u32 gps_gpcon = chip->pm_save[0];
u32 gps_gpdat = chip->pm_save[1];
u32 gpcon, old, new, mask;
@@ -135,7 +135,7 @@ static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
int nr;
/* restore GPIO pull-up settings */
- __raw_writel(chip->pm_save[2], base + OFFS_UP);
+ writel_relaxed(chip->pm_save[2], base + OFFS_UP);
/* Create a change_mask of all the items that need to have
* their CON value changed before their DAT value, so that
@@ -178,12 +178,12 @@ static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
gpcon = old_gpcon & ~change_mask;
gpcon |= gps_gpcon & change_mask;
- __raw_writel(gpcon, base + OFFS_CON);
+ writel_relaxed(gpcon, base + OFFS_CON);
/* Now change any items that require DAT,CON */
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
+ writel_relaxed(gps_gpdat, base + OFFS_DAT);
+ writel_relaxed(gps_gpcon, base + OFFS_CON);
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
@@ -197,12 +197,12 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
#if defined(CONFIG_ARCH_S3C64XX)
static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
{
- chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
- chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
- chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+ chip->pm_save[1] = readl_relaxed(chip->base + OFFS_CON);
+ chip->pm_save[2] = readl_relaxed(chip->base + OFFS_DAT);
+ chip->pm_save[3] = readl_relaxed(chip->base + OFFS_UP);
if (chip->chip.ngpio > 8)
- chip->pm_save[0] = __raw_readl(chip->base - 4);
+ chip->pm_save[0] = readl_relaxed(chip->base - 4);
}
static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
@@ -247,7 +247,7 @@ static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index)
{
void __iomem *con = chip->base + (index * 4);
- u32 old_gpcon = __raw_readl(con);
+ u32 old_gpcon = readl_relaxed(con);
u32 gps_gpcon = chip->pm_save[index + 1];
u32 gpcon, mask;
@@ -256,47 +256,47 @@ static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index)
gpcon = old_gpcon & ~mask;
gpcon |= gps_gpcon & mask;
- __raw_writel(gpcon, con);
+ writel_relaxed(gpcon, con);
}
static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
u32 old_gpcon[2];
- u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 old_gpdat = readl_relaxed(base + OFFS_DAT);
u32 gps_gpdat = chip->pm_save[2];
/* First, modify the CON settings */
old_gpcon[0] = 0;
- old_gpcon[1] = __raw_readl(base + OFFS_CON);
+ old_gpcon[1] = readl_relaxed(base + OFFS_CON);
samsung_gpio_pm_4bit_con(chip, 0);
if (chip->chip.ngpio > 8) {
- old_gpcon[0] = __raw_readl(base - 4);
+ old_gpcon[0] = readl_relaxed(base - 4);
samsung_gpio_pm_4bit_con(chip, -1);
}
/* Now change the configurations that require DAT,CON */
- __raw_writel(chip->pm_save[2], base + OFFS_DAT);
- __raw_writel(chip->pm_save[1], base + OFFS_CON);
+ writel_relaxed(chip->pm_save[2], base + OFFS_DAT);
+ writel_relaxed(chip->pm_save[1], base + OFFS_CON);
if (chip->chip.ngpio > 8)
- __raw_writel(chip->pm_save[0], base - 4);
+ writel_relaxed(chip->pm_save[0], base - 4);
- __raw_writel(chip->pm_save[2], base + OFFS_DAT);
- __raw_writel(chip->pm_save[3], base + OFFS_UP);
+ writel_relaxed(chip->pm_save[2], base + OFFS_DAT);
+ writel_relaxed(chip->pm_save[3], base + OFFS_UP);
if (chip->chip.ngpio > 8) {
S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon[0], old_gpcon[1],
- __raw_readl(base - 4),
- __raw_readl(base + OFFS_CON),
+ readl_relaxed(base - 4),
+ readl_relaxed(base + OFFS_CON),
old_gpdat, gps_gpdat);
} else
S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon[1],
- __raw_readl(base + OFFS_CON),
+ readl_relaxed(base + OFFS_CON),
old_gpdat, gps_gpdat);
}
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c
index 20c3d9117cc2..877ede44390e 100644
--- a/arch/arm/plat-samsung/wakeup-mask.c
+++ b/arch/arm/plat-samsung/wakeup-mask.c
@@ -25,7 +25,7 @@ void samsung_sync_wakemask(void __iomem *reg,
struct irq_data *data;
u32 val;
- val = __raw_readl(reg);
+ val = readl_relaxed(reg);
for (; nr_mask > 0; nr_mask--, mask++) {
if (mask->irq == NO_WAKEUP_IRQ) {
@@ -42,6 +42,6 @@ void samsung_sync_wakemask(void __iomem *reg,
val |= mask->bit;
}
- printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val);
- __raw_writel(val, reg);
+ printk(KERN_INFO "wakemask %08x => %08x\n", readl_relaxed(reg), val);
+ writel_relaxed(val, reg);
}
diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c
index 2ecb50bea044..e4d5a4ce1e19 100644
--- a/arch/arm/plat-samsung/watchdog-reset.c
+++ b/arch/arm/plat-samsung/watchdog-reset.c
@@ -44,14 +44,14 @@ void samsung_wdt_reset(void)
clk_prepare_enable(wdt_clock);
/* disable watchdog, to be safe */
- __raw_writel(0, wdt_base + S3C2410_WTCON);
+ writel_relaxed(0, wdt_base + S3C2410_WTCON);
/* put initial values into count and data */
- __raw_writel(0x80, wdt_base + S3C2410_WTCNT);
- __raw_writel(0x80, wdt_base + S3C2410_WTDAT);
+ writel_relaxed(0x80, wdt_base + S3C2410_WTCNT);
+ writel_relaxed(0x80, wdt_base + S3C2410_WTDAT);
/* set the watchdog to go and reset... */
- __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
+ writel_relaxed(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
wdt_base + S3C2410_WTCON);
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index b7710a59672c..669d385c500b 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -65,6 +65,7 @@ struct arm_pmu {
u64 max_period;
struct platform_device *plat_device;
struct pmu_hw_events *(*get_hw_events)(void);
+ int attr_rdpmc;
};
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 7778453762d8..407f9959867b 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -634,6 +634,16 @@ static void armpmu_disable(struct pmu *pmu)
armpmu->stop();
}
+static int armpmu_event_idx(struct perf_event *event)
+{
+ int idx = event->hw.idx;
+
+ if (!cpu_pmu->attr_rdpmc)
+ return 0;
+
+ return idx + 1;
+}
+
static void __init armpmu_init(struct arm_pmu *armpmu)
{
atomic_set(&armpmu->active_events, 0);
@@ -648,6 +658,7 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
.start = armpmu_start,
.stop = armpmu_stop,
.read = armpmu_read,
+ .event_idx = armpmu_event_idx,
};
}
@@ -1379,6 +1390,17 @@ static struct pmu_hw_events *armpmu_get_cpu_events(void)
return this_cpu_ptr(&cpu_hw_events);
}
+void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
+{
+ userpg->cap_user_rdpmc = cpu_pmu->attr_rdpmc;
+}
+
+void arch_perf_uspace_access(void *enable)
+{
+ cpu_pmu->attr_rdpmc = *(int *)enable;
+ asm volatile("msr pmuserenr_el0, %0" : : "r" (!!*(int *)enable));
+}
+
static void __init cpu_pmu_init(struct arm_pmu *armpmu)
{
int cpu;
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 34a5b93704d3..14aa13a72e38 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -81,6 +81,10 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
#define __raw_writew __writew
#define __raw_writel __writel
+#define writeb_relaxed __writeb
+#define writew_relaxed __writew
+#define writel_relaxed __writel
+
#define mmiowb() barrier()
#ifdef CONFIG_X86_64
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 07:25:43 +0000