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-rw-r--r--drivers/clk/samsung/clk-pll.c78
-rw-r--r--drivers/clk/samsung/clk.c4
-rw-r--r--drivers/clocksource/exynos_mct.c24
-rw-r--r--drivers/clocksource/samsung_pwm_timer.c16
-rw-r--r--drivers/cpufreq/exynos4210-cpufreq.c12
-rw-r--r--drivers/cpufreq/exynos4x12-cpufreq.c12
-rw-r--r--drivers/cpufreq/exynos5250-cpufreq.c12
-rw-r--r--drivers/cpufreq/exynos5440-cpufreq.c28
-rw-r--r--drivers/gpio/gpio-samsung.c114
-rw-r--r--drivers/irqchip/exynos-combiner.c8
-rw-r--r--drivers/mmc/host/dw_mmc.c42
-rw-r--r--drivers/mmc/host/dw_mmc.h26
-rw-r--r--drivers/thermal/samsung/exynos_tmu.c2
-rw-r--r--drivers/tty/serial/samsung.c43
-rw-r--r--drivers/tty/serial/samsung.h4
-rw-r--r--drivers/usb/misc/usb3503.c2
16 files changed, 234 insertions, 193 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 81e6d2f49aa0..cc64478f8bbc 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -80,7 +80,7 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->con_reg);
+ pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -117,19 +117,19 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
- tmp = __raw_readl(pll->con_reg);
+ tmp = readl_relaxed(pll->con_reg);
if (!(samsung_pll35xx_mp_change(rate, tmp))) {
/* If only s change, change just s value only*/
tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
- __raw_writel(tmp, pll->con_reg);
+ writel_relaxed(tmp, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
- __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR,
+ writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
pll->lock_reg);
/* Change PLL PMS values */
@@ -139,12 +139,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
(rate->pdiv << PLL35XX_PDIV_SHIFT) |
(rate->sdiv << PLL35XX_SDIV_SHIFT);
- __raw_writel(tmp, pll->con_reg);
+ writel_relaxed(tmp, pll->con_reg);
/* wait_lock_time */
do {
cpu_relax();
- tmp = __raw_readl(pll->con_reg);
+ tmp = readl_relaxed(pll->con_reg);
} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
<< PLL35XX_LOCK_STAT_SHIFT)));
return 0;
@@ -184,8 +184,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
s16 kdiv;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -225,20 +225,20 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
/* If only s change, change just s value only*/
pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
- __raw_writel(pll_con0, pll->con_reg);
+ writel_relaxed(pll_con0, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
- __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
+ writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
/* Change PLL PMS values */
pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
@@ -247,16 +247,16 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
(rate->pdiv << PLL36XX_PDIV_SHIFT) |
(rate->sdiv << PLL36XX_SDIV_SHIFT);
- __raw_writel(pll_con0, pll->con_reg);
+ writel_relaxed(pll_con0, pll->con_reg);
pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
- __raw_writel(pll_con1, pll->con_reg + 4);
+ writel_relaxed(pll_con1, pll->con_reg + 4);
/* wait_lock_time */
do {
cpu_relax();
- tmp = __raw_readl(pll->con_reg);
+ tmp = readl_relaxed(pll->con_reg);
} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
return 0;
@@ -297,7 +297,7 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->con_reg);
+ pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
@@ -340,14 +340,14 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
- con0 = __raw_readl(pll->con_reg);
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
/* If only s change, change just s value only*/
con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
- __raw_writel(con0, pll->con_reg);
+ writel_relaxed(con0, pll->con_reg);
return 0;
}
@@ -361,29 +361,29 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
(rate->sdiv << PLL45XX_SDIV_SHIFT);
/* Set PLL AFC value. */
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
/* Set PLL lock time. */
switch (pll->type) {
case pll_4502:
- __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
+ writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
break;
case pll_4508:
- __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
+ writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
break;
default:
break;
}
/* Set new configuration. */
- __raw_writel(con1, pll->con_reg + 0x4);
- __raw_writel(con0, pll->con_reg);
+ writel_relaxed(con1, pll->con_reg + 0x4);
+ writel_relaxed(con0, pll->con_reg);
/* Wait for locking. */
start = ktime_get();
- while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
+ while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) {
ktime_t delta = ktime_sub(ktime_get(), start);
if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -442,8 +442,8 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
@@ -487,14 +487,14 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
- con0 = __raw_readl(pll->con_reg);
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
/* If only s change, change just s value only*/
con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
- __raw_writel(con0, pll->con_reg);
+ writel_relaxed(con0, pll->con_reg);
return 0;
}
@@ -516,7 +516,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
(rate->vsel << PLL46XX_VSEL_SHIFT);
/* Set PLL K, MFR and MRR values. */
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
(PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
@@ -525,13 +525,13 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
(rate->mrr << PLL46XX_MRR_SHIFT);
/* Write configuration to PLL */
- __raw_writel(lock, pll->lock_reg);
- __raw_writel(con0, pll->con_reg);
- __raw_writel(con1, pll->con_reg + 0x4);
+ writel_relaxed(lock, pll->lock_reg);
+ writel_relaxed(con0, pll->con_reg);
+ writel_relaxed(con1, pll->con_reg + 0x4);
/* Wait for locking. */
start = ktime_get();
- while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) {
+ while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) {
ktime_t delta = ktime_sub(ktime_get(), start);
if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -574,7 +574,7 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->con_reg);
+ pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
@@ -609,8 +609,8 @@ static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 0x4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 0x4);
mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
@@ -655,7 +655,7 @@ static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
u32 r, p, m, s, pll_stat;
u64 fvco = parent_rate;
- pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
+ pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3);
r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
if (!r)
return 0;
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index f503f32e2f80..afad1c80f368 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -31,7 +31,7 @@ static int samsung_clk_suspend(void)
unsigned long i;
for (i = 0; i < nr_reg_dump; i++, rd++)
- rd->value = __raw_readl(reg_base + rd->offset);
+ rd->value = readl_relaxed(reg_base + rd->offset);
return 0;
}
@@ -42,7 +42,7 @@ static void samsung_clk_resume(void)
unsigned long i;
for (i = 0; i < nr_reg_dump; i++, rd++)
- __raw_writel(rd->value, reg_base + rd->offset);
+ writel_relaxed(rd->value, reg_base + rd->offset);
}
static struct syscore_ops samsung_clk_syscore_ops = {
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index e252939b9ee1..71cd1967c54f 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -95,7 +95,7 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
u32 mask;
u32 i;
- __raw_writel(value, reg_base + offset);
+ writel_relaxed(value, reg_base + offset);
if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
@@ -145,8 +145,8 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
/* Wait maximum 1 ms until written values are applied */
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
- if (__raw_readl(reg_base + stat_addr) & mask) {
- __raw_writel(mask, reg_base + stat_addr);
+ if (readl_relaxed(reg_base + stat_addr) & mask) {
+ writel_relaxed(mask, reg_base + stat_addr);
return;
}
@@ -161,7 +161,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
- reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
@@ -169,12 +169,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
unsigned int lo, hi;
- u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
do {
hi = hi2;
- lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
- hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
+ hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
return ((cycle_t)hi << 32) | lo;
@@ -206,7 +206,7 @@ static void exynos4_mct_comp0_stop(void)
{
unsigned int tcon;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -219,7 +219,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
unsigned int tcon;
cycle_t comp_cycle;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -308,7 +308,7 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
- tmp = __raw_readl(reg_base + offset);
+ tmp = readl_relaxed(reg_base + offset);
if (tmp & mask) {
tmp &= ~mask;
exynos4_mct_write(tmp, offset);
@@ -330,7 +330,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
/* enable MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
- tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
+ tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
MCT_L_TCON_INTERVAL_MODE;
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -382,7 +382,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
- if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
return 1;
} else {
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 5645cfc90c41..19aaddd247d3 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -130,9 +130,9 @@ static void samsung_time_stop(unsigned int channel)
spin_lock_irqsave(&samsung_pwm_lock, flags);
- tcon = __raw_readl(pwm.base + REG_TCON);
+ tcon = readl_relaxed(pwm.base + REG_TCON);
tcon &= ~TCON_START(channel);
- __raw_writel(tcon, pwm.base + REG_TCON);
+ writel_relaxed(tcon, pwm.base + REG_TCON);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
@@ -148,14 +148,14 @@ static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
spin_lock_irqsave(&samsung_pwm_lock, flags);
- tcon = __raw_readl(pwm.base + REG_TCON);
+ tcon = readl_relaxed(pwm.base + REG_TCON);
tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
tcon |= TCON_MANUALUPDATE(tcon_chan);
- __raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
- __raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
- __raw_writel(tcon, pwm.base + REG_TCON);
+ writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
+ writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
+ writel_relaxed(tcon, pwm.base + REG_TCON);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
@@ -170,7 +170,7 @@ static void samsung_time_start(unsigned int channel, bool periodic)
spin_lock_irqsave(&samsung_pwm_lock, flags);
- tcon = __raw_readl(pwm.base + REG_TCON);
+ tcon = readl_relaxed(pwm.base + REG_TCON);
tcon &= ~TCON_MANUALUPDATE(channel);
tcon |= TCON_START(channel);
@@ -180,7 +180,7 @@ static void samsung_time_start(unsigned int channel, bool periodic)
else
tcon &= ~TCON_AUTORELOAD(channel);
- __raw_writel(tcon, pwm.base + REG_TCON);
+ writel_relaxed(tcon, pwm.base + REG_TCON);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index 40d84c43d8f4..df4f5cfeb155 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -60,20 +60,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
tmp = apll_freq_4210[div_index].clk_div_cpu0;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU);
do {
- tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+ tmp = readl_relaxed(EXYNOS4_CLKDIV_STATCPU);
} while (tmp & 0x1111111);
/* Change Divider - CPU1 */
tmp = apll_freq_4210[div_index].clk_div_cpu1;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU1);
do {
- tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+ tmp = readl_relaxed(EXYNOS4_CLKDIV_STATCPU1);
} while (tmp & 0x11);
}
@@ -85,7 +85,7 @@ static void exynos4210_set_apll(unsigned int index)
clk_set_parent(moutcore, mout_mpll);
do {
- tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+ tmp = (readl_relaxed(EXYNOS4_CLKMUX_STATCPU)
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
tmp &= 0x7;
} while (tmp != 0x2);
@@ -96,7 +96,7 @@ static void exynos4210_set_apll(unsigned int index)
clk_set_parent(moutcore, mout_apll);
do {
- tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+ tmp = readl_relaxed(EXYNOS4_CLKMUX_STATCPU);
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 7c11ace3b3fc..972d0b1165fb 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -106,21 +106,21 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
tmp = apll_freq_4x12[div_index].clk_div_cpu0;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU);
- while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+ while (readl_relaxed(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
cpu_relax();
/* Change Divider - CPU1 */
tmp = apll_freq_4x12[div_index].clk_div_cpu1;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU1);
if (soc_is_exynos4212())
stat_cpu1 = 0x11;
else
stat_cpu1 = 0x111;
- while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
+ while (readl_relaxed(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
cpu_relax();
}
@@ -133,7 +133,7 @@ static void exynos4x12_set_apll(unsigned int index)
do {
cpu_relax();
- tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+ tmp = (readl_relaxed(EXYNOS4_CLKMUX_STATCPU)
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
tmp &= 0x7;
} while (tmp != 0x2);
@@ -145,7 +145,7 @@ static void exynos4x12_set_apll(unsigned int index)
do {
cpu_relax();
- tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+ tmp = readl_relaxed(EXYNOS4_CLKMUX_STATCPU);
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index 5f90b82a4082..d212a7262acf 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -87,17 +87,17 @@ static void set_clkdiv(unsigned int div_index)
tmp = apll_freq_5250[div_index].clk_div_cpu0;
- __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+ writel_relaxed(tmp, EXYNOS5_CLKDIV_CPU0);
- while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
+ while (readl_relaxed(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
cpu_relax();
/* Change Divider - CPU1 */
tmp = apll_freq_5250[div_index].clk_div_cpu1;
- __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+ writel_relaxed(tmp, EXYNOS5_CLKDIV_CPU1);
- while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
+ while (readl_relaxed(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
cpu_relax();
}
@@ -111,7 +111,7 @@ static void set_apll(unsigned int index)
do {
cpu_relax();
- tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
+ tmp = (readl_relaxed(EXYNOS5_CLKMUX_STATCPU) >> 16);
tmp &= 0x7;
} while (tmp != 0x2);
@@ -122,7 +122,7 @@ static void set_apll(unsigned int index)
do {
cpu_relax();
- tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+ tmp = readl_relaxed(EXYNOS5_CLKMUX_STATCPU);
tmp &= (0x7 << 16);
} while (tmp != (0x1 << 16));
}
diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c
index 49b756015316..8478ca766858 100644
--- a/drivers/cpufreq/exynos5440-cpufreq.c
+++ b/drivers/cpufreq/exynos5440-cpufreq.c
@@ -157,7 +157,7 @@ static int init_div_table(void)
tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
| ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
- __raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * i);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * i);
}
rcu_read_unlock();
@@ -169,17 +169,17 @@ static void exynos_enable_dvfs(unsigned int cur_frequency)
unsigned int tmp, i, cpu;
struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
/* Disable DVFS */
- __raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL);
+ writel_relaxed(0, dvfs_info->base + XMU_DVFS_CTRL);
/* Enable PSTATE Change Event */
- tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN);
+ tmp = readl_relaxed(dvfs_info->base + XMU_PMUEVTEN);
tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMUEVTEN);
/* Enable PSTATE Change IRQ */
- tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN);
+ tmp = readl_relaxed(dvfs_info->base + XMU_PMUIRQEN);
tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMUIRQEN);
/* Set initial performance index */
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
@@ -197,14 +197,14 @@ static void exynos_enable_dvfs(unsigned int cur_frequency)
cur_frequency);
for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
- tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
+ tmp = readl_relaxed(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
tmp |= (i << C0_3_PSTATE_NEW_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
+ writel_relaxed(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
}
/* Enable DVFS */
- __raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT,
+ writel_relaxed(1 << XMU_DVFS_CTRL_EN_SHIFT,
dvfs_info->base + XMU_DVFS_CTRL);
}
@@ -223,11 +223,11 @@ static int exynos_target(struct cpufreq_policy *policy, unsigned int index)
/* Set the target frequency in all C0_3_PSTATE register */
for_each_cpu(i, policy->cpus) {
- tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
+ tmp = readl_relaxed(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
tmp |= (index << C0_3_PSTATE_NEW_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
+ writel_relaxed(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
}
mutex_unlock(&cpufreq_lock);
return 0;
@@ -246,7 +246,7 @@ static void exynos_cpufreq_work(struct work_struct *work)
mutex_lock(&cpufreq_lock);
freqs.old = policy->cur;
- cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS);
+ cur_pstate = readl_relaxed(dvfs_info->base + XMU_P_STATUS);
if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1)
index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK;
else
@@ -270,9 +270,9 @@ static irqreturn_t exynos_cpufreq_irq(int irq, void *id)
{
unsigned int tmp;
- tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ);
+ tmp = readl_relaxed(dvfs_info->base + XMU_PMUIRQ);
if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) {
- __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMUIRQ);
disable_irq_nosync(irq);
schedule_work(&dvfs_info->irq_work);
}
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a85e00bf9834..81e6c83d5de7 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -50,10 +50,10 @@ int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
int shift = off * 2;
u32 pup;
- pup = __raw_readl(reg);
+ pup = readl_relaxed(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
- __raw_writel(pup, reg);
+ writel_relaxed(pup, reg);
return 0;
}
@@ -63,7 +63,7 @@ samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
- u32 pup = __raw_readl(reg);
+ u32 pup = readl_relaxed(reg);
pup >>= shift;
pup &= 0x3;
@@ -116,7 +116,7 @@ static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
samsung_gpio_pull_t updown)
{
void __iomem *reg = chip->base + 0x08;
- u32 pup = __raw_readl(reg);
+ u32 pup = readl_relaxed(reg);
if (pull == updown)
pup &= ~(1 << off);
@@ -125,7 +125,7 @@ static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
else
return -EINVAL;
- __raw_writel(pup, reg);
+ writel_relaxed(pup, reg);
return 0;
}
@@ -134,7 +134,7 @@ static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip
samsung_gpio_pull_t updown)
{
void __iomem *reg = chip->base + 0x08;
- u32 pup = __raw_readl(reg);
+ u32 pup = readl_relaxed(reg);
pup &= (1 << off);
return pup ? S3C_GPIO_PULL_NONE : updown;
@@ -193,10 +193,10 @@ static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0x3 << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -216,7 +216,7 @@ static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
{
u32 con;
- con = __raw_readl(chip->base);
+ con = readl_relaxed(chip->base);
con >>= off * 2;
con &= 3;
@@ -256,10 +256,10 @@ static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0xf << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -286,7 +286,7 @@ static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
if (off < 8 && chip->chip.ngpio > 8)
reg -= 4;
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con >>= shift;
con &= 0xf;
@@ -324,10 +324,10 @@ static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0x1 << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -349,7 +349,7 @@ static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
{
u32 con;
- con = __raw_readl(chip->base);
+ con = readl_relaxed(chip->base);
con >>= off;
con &= 1;
con++;
@@ -389,10 +389,10 @@ static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0xf << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -490,10 +490,10 @@ static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
samsung_gpio_lock(ourchip, flags);
- con = __raw_readl(base + 0x00);
+ con = readl_relaxed(base + 0x00);
con &= ~(3 << (offset * 2));
- __raw_writel(con, base + 0x00);
+ writel_relaxed(con, base + 0x00);
samsung_gpio_unlock(ourchip, flags);
return 0;
@@ -510,18 +510,18 @@ static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
samsung_gpio_lock(ourchip, flags);
- dat = __raw_readl(base + 0x04);
+ dat = readl_relaxed(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(dat, base + 0x04);
- con = __raw_readl(base + 0x00);
+ con = readl_relaxed(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
- __raw_writel(con, base + 0x00);
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(con, base + 0x00);
+ writel_relaxed(dat, base + 0x04);
samsung_gpio_unlock(ourchip, flags);
return 0;
@@ -550,12 +550,12 @@ static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
void __iomem *base = ourchip->base;
unsigned long con;
- con = __raw_readl(base + GPIOCON_OFF);
+ con = readl_relaxed(base + GPIOCON_OFF);
if (ourchip->bitmap_gpio_int & BIT(offset))
con |= 0xf << con_4bit_shift(offset);
else
con &= ~(0xf << con_4bit_shift(offset));
- __raw_writel(con, base + GPIOCON_OFF);
+ writel_relaxed(con, base + GPIOCON_OFF);
pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
@@ -570,20 +570,20 @@ static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
unsigned long con;
unsigned long dat;
- con = __raw_readl(base + GPIOCON_OFF);
+ con = readl_relaxed(base + GPIOCON_OFF);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
- dat = __raw_readl(base + GPIODAT_OFF);
+ dat = readl_relaxed(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
- __raw_writel(dat, base + GPIODAT_OFF);
- __raw_writel(con, base + GPIOCON_OFF);
- __raw_writel(dat, base + GPIODAT_OFF);
+ writel_relaxed(dat, base + GPIODAT_OFF);
+ writel_relaxed(con, base + GPIOCON_OFF);
+ writel_relaxed(dat, base + GPIODAT_OFF);
pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
@@ -625,9 +625,9 @@ static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
else
regcon -= 4;
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(offset));
- __raw_writel(con, regcon);
+ writel_relaxed(con, regcon);
pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
@@ -649,20 +649,20 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
else
regcon -= 4;
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(con_offset));
con |= 0x1 << con_4bit_shift(con_offset);
- dat = __raw_readl(base + GPIODAT_OFF);
+ dat = readl_relaxed(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
- __raw_writel(dat, base + GPIODAT_OFF);
- __raw_writel(con, regcon);
- __raw_writel(dat, base + GPIODAT_OFF);
+ writel_relaxed(dat, base + GPIODAT_OFF);
+ writel_relaxed(con, regcon);
+ writel_relaxed(dat, base + GPIODAT_OFF);
pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
@@ -688,19 +688,19 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
local_irq_save(flags);
- con = __raw_readl(base + 0x00);
- dat = __raw_readl(base + 0x04);
+ con = readl_relaxed(base + 0x00);
+ dat = readl_relaxed(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(dat, base + 0x04);
con &= ~(1 << offset);
- __raw_writel(con, base + 0x00);
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(con, base + 0x00);
+ writel_relaxed(dat, base + 0x04);
local_irq_restore(flags);
return 0;
@@ -736,9 +736,9 @@ static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
samsung_gpio_lock(ourchip, flags);
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(offset));
- __raw_writel(con, regcon);
+ writel_relaxed(con, regcon);
samsung_gpio_unlock(ourchip, flags);
@@ -774,18 +774,18 @@ static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
samsung_gpio_lock(ourchip, flags);
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(con_offset));
con |= 0x1 << con_4bit_shift(con_offset);
- dat = __raw_readl(base + GPIODAT_OFF);
+ dat = readl_relaxed(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
- __raw_writel(con, regcon);
- __raw_writel(dat, base + GPIODAT_OFF);
+ writel_relaxed(con, regcon);
+ writel_relaxed(dat, base + GPIODAT_OFF);
samsung_gpio_unlock(ourchip, flags);
@@ -802,11 +802,11 @@ static void samsung_gpiolib_set(struct gpio_chip *chip,
samsung_gpio_lock(ourchip, flags);
- dat = __raw_readl(base + 0x04);
+ dat = readl_relaxed(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(dat, base + 0x04);
samsung_gpio_unlock(ourchip, flags);
}
@@ -816,7 +816,7 @@ static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
unsigned long val;
- val = __raw_readl(ourchip->base + 0x04);
+ val = readl_relaxed(ourchip->base + 0x04);
val >>= offset;
val &= 1;
@@ -2289,7 +2289,7 @@ s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
shift = off * 2;
reg = chip->base + 0x0C;
- drvstr = __raw_readl(reg);
+ drvstr = readl_relaxed(reg);
drvstr = drvstr >> shift;
drvstr &= 0x3;
@@ -2312,11 +2312,11 @@ int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
shift = off * 2;
reg = chip->base + 0x0C;
- tmp = __raw_readl(reg);
+ tmp = readl_relaxed(reg);
tmp &= ~(0x3 << shift);
tmp |= drvstr << shift;
- __raw_writel(tmp, reg);
+ writel_relaxed(tmp, reg);
return 0;
}
@@ -2330,10 +2330,10 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
unsigned long misccr;
local_irq_save(flags);
- misccr = __raw_readl(S3C24XX_MISCCR);
+ misccr = readl_relaxed(S3C24XX_MISCCR);
misccr &= ~clear;
misccr ^= change;
- __raw_writel(misccr, S3C24XX_MISCCR);
+ writel_relaxed(misccr, S3C24XX_MISCCR);
local_irq_restore(flags);
return misccr;
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 40e6440348ff..73fb6993680a 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -50,14 +50,14 @@ static void combiner_mask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->hwirq % 32);
- __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+ writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->hwirq % 32);
- __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+ writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -70,7 +70,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
- status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+ status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
@@ -131,7 +131,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
combiner_data->parent_irq = irq;
/* Disable all interrupts */
- __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
+ writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
}
static int combiner_irq_domain_xlate(struct irq_domain *d,
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 55cd110a49c4..6c64dac41efd 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1448,7 +1448,7 @@ static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
buf += len;
cnt -= len;
if (host->part_buf_count == 2) {
- mci_writew(host, DATA(host->data_offset),
+ mci_writew_data(host, DATA(host->data_offset),
host->part_buf16);
host->part_buf_count = 0;
}
@@ -1466,7 +1466,7 @@ static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
cnt -= len;
/* push data from aligned buffer into fifo */
for (i = 0; i < items; ++i)
- mci_writew(host, DATA(host->data_offset),
+ mci_writew_data(host, DATA(host->data_offset),
aligned_buf[i]);
}
} else
@@ -1474,7 +1474,7 @@ static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
{
u16 *pdata = buf;
for (; cnt >= 2; cnt -= 2)
- mci_writew(host, DATA(host->data_offset), *pdata++);
+ mci_writew_data(host, DATA(host->data_offset), *pdata++);
buf = pdata;
}
/* put anything remaining in the part_buf */
@@ -1483,7 +1483,7 @@ static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
/* Push data if we have reached the expected data length */
if ((data->bytes_xfered + init_cnt) ==
(data->blksz * data->blocks))
- mci_writew(host, DATA(host->data_offset),
+ mci_writew_data(host, DATA(host->data_offset),
host->part_buf16);
}
}
@@ -1499,7 +1499,7 @@ static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
int items = len >> 1;
int i;
for (i = 0; i < items; ++i)
- aligned_buf[i] = mci_readw(host,
+ aligned_buf[i] = mci_readw_data(host,
DATA(host->data_offset));
/* memcpy from aligned buffer into output buffer */
memcpy(buf, aligned_buf, len);
@@ -1511,11 +1511,11 @@ static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
{
u16 *pdata = buf;
for (; cnt >= 2; cnt -= 2)
- *pdata++ = mci_readw(host, DATA(host->data_offset));
+ *pdata++ = mci_readw_data(host, DATA(host->data_offset));
buf = pdata;
}
if (cnt) {
- host->part_buf16 = mci_readw(host, DATA(host->data_offset));
+ host->part_buf16 = mci_readw_data(host, DATA(host->data_offset));
dw_mci_pull_final_bytes(host, buf, cnt);
}
}
@@ -1531,7 +1531,7 @@ static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
buf += len;
cnt -= len;
if (host->part_buf_count == 4) {
- mci_writel(host, DATA(host->data_offset),
+ mci_writel_data(host, DATA(host->data_offset),
host->part_buf32);
host->part_buf_count = 0;
}
@@ -1549,7 +1549,7 @@ static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
cnt -= len;
/* push data from aligned buffer into fifo */
for (i = 0; i < items; ++i)
- mci_writel(host, DATA(host->data_offset),
+ mci_writel_data(host, DATA(host->data_offset),
aligned_buf[i]);
}
} else
@@ -1557,7 +1557,7 @@ static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
{
u32 *pdata = buf;
for (; cnt >= 4; cnt -= 4)
- mci_writel(host, DATA(host->data_offset), *pdata++);
+ mci_writel_data(host, DATA(host->data_offset), *pdata++);
buf = pdata;
}
/* put anything remaining in the part_buf */
@@ -1566,7 +1566,7 @@ static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
/* Push data if we have reached the expected data length */
if ((data->bytes_xfered + init_cnt) ==
(data->blksz * data->blocks))
- mci_writel(host, DATA(host->data_offset),
+ mci_writel_data(host, DATA(host->data_offset),
host->part_buf32);
}
}
@@ -1582,7 +1582,7 @@ static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
int items = len >> 2;
int i;
for (i = 0; i < items; ++i)
- aligned_buf[i] = mci_readl(host,
+ aligned_buf[i] = mci_readl_data(host,
DATA(host->data_offset));
/* memcpy from aligned buffer into output buffer */
memcpy(buf, aligned_buf, len);
@@ -1594,11 +1594,11 @@ static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
{
u32 *pdata = buf;
for (; cnt >= 4; cnt -= 4)
- *pdata++ = mci_readl(host, DATA(host->data_offset));
+ *pdata++ = mci_readl_data(host, DATA(host->data_offset));
buf = pdata;
}
if (cnt) {
- host->part_buf32 = mci_readl(host, DATA(host->data_offset));
+ host->part_buf32 = mci_readl_data(host, DATA(host->data_offset));
dw_mci_pull_final_bytes(host, buf, cnt);
}
}
@@ -1615,7 +1615,7 @@ static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
cnt -= len;
if (host->part_buf_count == 8) {
- mci_writeq(host, DATA(host->data_offset),
+ mci_writeq_data(host, DATA(host->data_offset),
host->part_buf);
host->part_buf_count = 0;
}
@@ -1633,7 +1633,7 @@ static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
cnt -= len;
/* push data from aligned buffer into fifo */
for (i = 0; i < items; ++i)
- mci_writeq(host, DATA(host->data_offset),
+ mci_writeq_data(host, DATA(host->data_offset),
aligned_buf[i]);
}
} else
@@ -1641,7 +1641,7 @@ static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
{
u64 *pdata = buf;
for (; cnt >= 8; cnt -= 8)
- mci_writeq(host, DATA(host->data_offset), *pdata++);
+ mci_writeq_data(host, DATA(host->data_offset), *pdata++);
buf = pdata;
}
/* put anything remaining in the part_buf */
@@ -1650,7 +1650,7 @@ static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
/* Push data if we have reached the expected data length */
if ((data->bytes_xfered + init_cnt) ==
(data->blksz * data->blocks))
- mci_writeq(host, DATA(host->data_offset),
+ mci_writeq_data(host, DATA(host->data_offset),
host->part_buf);
}
}
@@ -1666,7 +1666,7 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
int items = len >> 3;
int i;
for (i = 0; i < items; ++i)
- aligned_buf[i] = mci_readq(host,
+ aligned_buf[i] = mci_readq_data(host,
DATA(host->data_offset));
/* memcpy from aligned buffer into output buffer */
memcpy(buf, aligned_buf, len);
@@ -1678,11 +1678,11 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
{
u64 *pdata = buf;
for (; cnt >= 8; cnt -= 8)
- *pdata++ = mci_readq(host, DATA(host->data_offset));
+ *pdata++ = mci_readq_data(host, DATA(host->data_offset));
buf = pdata;
}
if (cnt) {
- host->part_buf = mci_readq(host, DATA(host->data_offset));
+ host->part_buf = mci_readq_data(host, DATA(host->data_offset));
dw_mci_pull_final_bytes(host, buf, cnt);
}
}
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 6bf24ab917e6..6e3ed89b5688 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -152,21 +152,27 @@
/* Register access macros */
#define mci_readl(dev, reg) \
- __raw_readl((dev)->regs + SDMMC_##reg)
+ readl_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writel(dev, reg, value) \
- __raw_writel((value), (dev)->regs + SDMMC_##reg)
+ writel_relaxed((value), (dev)->regs + SDMMC_##reg)
/* 16-bit FIFO access macros */
-#define mci_readw(dev, reg) \
+#define mci_readw_data(dev, reg) \
__raw_readw((dev)->regs + SDMMC_##reg)
-#define mci_writew(dev, reg, value) \
+#define mci_writew_data(dev, reg, value) \
__raw_writew((value), (dev)->regs + SDMMC_##reg)
+/* 32-bit FIFO access macros */
+#define mci_readl_data(dev, reg) \
+ __raw_readl((dev)->regs + SDMMC_##reg)
+#define mci_writel_data(dev, reg, value) \
+ __raw_writel((value), (dev)->regs + SDMMC_##reg)
+
/* 64-bit FIFO access macros */
#ifdef readq
-#define mci_readq(dev, reg) \
+#define mci_readq_data(dev, reg) \
__raw_readq((dev)->regs + SDMMC_##reg)
-#define mci_writeq(dev, reg, value) \
+#define mci_writeq_data(dev, reg, value) \
__raw_writeq((value), (dev)->regs + SDMMC_##reg)
#else
/*
@@ -177,10 +183,10 @@
* executed on those machines. Defining these macros here keeps the
* rest of the code free from ifdefs.
*/
-#define mci_readq(dev, reg) \
- (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
-#define mci_writeq(dev, reg, value) \
- (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
+#define mci_readq_data(dev, reg) \
+ ({ u64 __r = le64_to_cpu(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)); __r; })
+#define mci_writeq_data(dev, reg, value) \
+ (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (cpu_to_le64(value)))
#endif
extern int dw_mci_probe(struct dw_mci *host);
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 0d96a510389f..171aee923c79 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -162,7 +162,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
}
if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
- __raw_writel(1, data->base + reg->triminfo_ctrl);
+ writel_relaxed(1, data->base + reg->triminfo_ctrl);
if (pdata->cal_mode == HW_MODE)
goto skip_calib_data;
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 9cd706df3b33..30ec44260b24 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -59,6 +59,41 @@
#define S3C24XX_SERIAL_MAJOR 204
#define S3C24XX_SERIAL_MINOR 64
+#ifndef CONFIG_CPU_BIG_ENDIAN /* little endian */
+static inline void __hw_set_bit(int nr, volatile unsigned long *addr)
+{
+ __set_bit(nr, addr);
+}
+
+static inline void __hw_clear_bit(int nr, volatile unsigned long *addr)
+{
+ __clear_bit(nr, addr);
+}
+#else
+static inline void __hw_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long val = le32_to_cpu(*p);
+
+ val |= mask;
+
+ *p = cpu_to_le32(val);
+}
+
+static inline void __hw_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ unsigned long val = le32_to_cpu(*p);
+
+ val &= ~mask;
+
+ *p = cpu_to_le32(val);
+}
+#endif
+
/* macros to change one thing to another */
#define tx_enabled(port) ((port)->unused[0])
@@ -138,7 +173,7 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
if (tx_enabled(port)) {
if (s3c24xx_serial_has_interrupt_mask(port))
- __set_bit(S3C64XX_UINTM_TXD,
+ __hw_set_bit(S3C64XX_UINTM_TXD,
portaddrl(port, S3C64XX_UINTM));
else
disable_irq_nosync(ourport->tx_irq);
@@ -157,7 +192,7 @@ static void s3c24xx_serial_start_tx(struct uart_port *port)
s3c24xx_serial_rx_disable(port);
if (s3c24xx_serial_has_interrupt_mask(port))
- __clear_bit(S3C64XX_UINTM_TXD,
+ __hw_clear_bit(S3C64XX_UINTM_TXD,
portaddrl(port, S3C64XX_UINTM));
else
enable_irq(ourport->tx_irq);
@@ -172,7 +207,7 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
if (rx_enabled(port)) {
dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
if (s3c24xx_serial_has_interrupt_mask(port))
- __set_bit(S3C64XX_UINTM_RXD,
+ __hw_set_bit(S3C64XX_UINTM_RXD,
portaddrl(port, S3C64XX_UINTM));
else
disable_irq_nosync(ourport->rx_irq);
@@ -533,7 +568,7 @@ static int s3c64xx_serial_startup(struct uart_port *port)
ourport->tx_claimed = 1;
/* Enable Rx Interrupt */
- __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
+ __hw_clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
dbg("s3c64xx_serial_startup ok\n");
return ret;
}
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 8827e5424cef..ceb11f73c777 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -72,10 +72,10 @@ struct s3c24xx_uart_port {
((unsigned long *)(unsigned long)((port)->membase + (reg)))
#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
-#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
+#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
-#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
+#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
defined(CONFIG_DEBUG_LL) && \
diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index a31641e18d19..ad8368d96665 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -339,7 +339,7 @@ static int __init usb3503_init(void)
return 0;
}
-module_init(usb3503_init);
+late_initcall(usb3503_init);
static void __exit usb3503_exit(void)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 03:55:15 +0000