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2015-12-14Merge branch 'linaro-android-3.18-lsk' of ↵lsk-v3.18-15.12-androidKevin Hilman
git://android.git.linaro.org/kernel/linaro-android into linux-linaro-lsk-v3.18-android
2015-12-14Merge branch 'linux-linaro-lsk-v3.18' into linux-linaro-lsk-v3.18-androidKevin Hilman
Conflicts: arch/arm64/Kconfig arch/arm64/include/asm/cputype.h arch/arm64/kernel/Makefile arch/arm64/kernel/armv8_deprecated.c arch/arm64/kernel/cpuinfo.c
2015-12-14arm: enable ARCH_MMAP_RND_BITS only for MMU platformsAmit Pundir
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
2015-12-10Merge branch 'linux-linaro-lsk-v3.18' into linux-linaro-lsk-v3.18-androidKevin Hilman
2015-12-08Merge branch 'pan-3.18' of ↵Kevin Hilman
https://git.linaro.org/people/david.brown/linux-lsk into linux-linaro-lsk-v3.18 * 'pan-3.18' of https://git.linaro.org/people/david.brown/linux-lsk: (27 commits) arm64: kernel: Add support for Privileged Access Never arm64: Generalise msr_s/mrs_s operations arm64: kernel: Add cpufeature 'enable' callback arm64: kernel: Add cpuid_feature_extract_field() for 4bit sign extension arm64: kernel: Add min_field_value and use '>=' for feature detection arm64: kernel: Add optional CONFIG_ parameter to ALTERNATIVE() arm64: alternative: Provide if/else/endif assembler macros arm64: alternative: Work around .inst assembler bugs arm64: alternative: Merge alternative-asm.h into alternative.h arm64: Add AArch32 instruction set condition code checks arm64: lib: use pair accessors for copy_*_user routines arm64/uaccess: fix sparse errors arm64: kernel: Move config_sctlr_el1 arm64: Emulate SETEND for AArch32 tasks arm64: kconfig: move emulation option under kernel features arm64: Consolidate hotplug notifier for instruction emulation arm64: fix return code check when changing emulation handler arm64: Trace emulation of AArch32 legacy instructions arm64: Emulate CP15 Barrier instructions arm64: Port SWP/SWPB emulation support from arm ... Conflicts: arch/arm64/kernel/Makefile
2015-12-03arm64: kernel: Add support for Privileged Access NeverJames Morse
commit 338d4f49d6f7114a017d294ccf7374df4f998edc upstream. 'Privileged Access Never' is a new arm8.1 feature which prevents privileged code from accessing any virtual address where read or write access is also permitted at EL0. This patch enables the PAN feature on all CPUs, and modifies {get,put}_user helpers temporarily to permit access. This will catch kernel bugs where user memory is accessed directly. 'Unprivileged loads and stores' using ldtrb et al are unaffected by PAN. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com> [will: use ALTERNATIVE in asm and tidy up pan_enable check] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Generalise msr_s/mrs_s operationsSuzuki K. Poulose
commit 9ded63aaf83eba76e1a54ac02581c2badc497f1a upstream. The system register encoding generated by sys_reg() works only for MRS/MSR(Register) operations, as we hardcode Bit20 to 1 in mrs_s/msr_s mask. This makes it unusable for generating instructions accessing registers with Op0 < 2(e.g, PSTATE.x with Op0=0). As per ARMv8 ARM, (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", C5.2, version:ARM DDI 0487A.f), the instruction encoding reserves bits [20-19] for Op0. This patch generalises the sys_reg, mrs_s and msr_s macros, so that we could use them to access any of the supported system register. Cc: James Morse <james.morse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: kernel: Add cpufeature 'enable' callbackJames Morse
commit 1c0763037f1e1caef739e36e09c6d41ed7b61b2d upstream. This patch adds an 'enable()' callback to cpu capability/feature detection, allowing features that require some setup or configuration to get this opportunity once the feature has been detected. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: kernel: Add cpuid_feature_extract_field() for 4bit sign extensionJames Morse
commit 79b0e09a3c9bd74ee54582efdb351179d7c00351 upstream. Based on arch/arm/include/asm/cputype.h, this function does the shifting and sign extension necessary when accessing cpu feature fields. Signed-off-by: James Morse <james.morse@arm.com> Suggested-by: Russell King <linux@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: kernel: Add min_field_value and use '>=' for feature detectionJames Morse
commit 18ffa046c509d0cd011eeea2c0418f2d014771fc upstream. When a new cpu feature is available, the cpu feature bits will have some initial value, which is incremented when the feature is updated. This patch changes 'register_value' to be 'min_field_value', and checks the feature bits value (interpreted as a signed int) is greater than this minimum. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: kernel: Add optional CONFIG_ parameter to ALTERNATIVE()James Morse
commit 91a5cefa2f98bdd3404c2fba57048c4fa225cc37 upstream. Some uses of ALTERNATIVE() may depend on a feature that is disabled at compile time by a Kconfig option. In this case the unused alternative instructions waste space, and if the original instruction is a nop, it wastes time and space. This patch adds an optional 'config' option to ALTERNATIVE() and alternative_insn that allows the compiler to remove both the original and alternative instructions if the config option is not defined. Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: alternative: Provide if/else/endif assembler macrosDaniel Thompson
commit 63e40815f02584ba8174e0f6af40924b2b335cae upstream. The existing alternative_insn macro has some limitations that make it hard to work with. In particular the fact it takes instructions from it own macro arguments means it doesn't play very nicely with C pre-processor macros because the macro arguments look like a string to the C pre-processor. Workarounds are (probably) possible but things start to look ugly. Introduce an alternative set of macros that allows instructions to be presented to the assembler as normal and switch everything over to the new macros. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: alternative: Work around .inst assembler bugsMarc Zyngier
commit eb7c11ee3c5ce6c45ac28a5015a8e60ed458b412 upstream. AArch64 toolchains suffer from the following bug: $ cat blah.S 1: .inst 0x01020304 .if ((. - 1b) != 4) .error "blah" .endif $ aarch64-linux-gnu-gcc -c blah.S blah.S: Assembler messages: blah.S:3: Error: non-constant expression in ".if" statement which precludes the use of msr_s and co as part of alternatives. We workaround this issue by not directly testing the labels themselves, but by moving the current output pointer by a value that should always be zero. If this value is not null, then we will trigger a backward move, which is expclicitely forbidden. This triggers the error we're after: AS arch/arm64/kvm/hyp.o arch/arm64/kvm/hyp.S: Assembler messages: arch/arm64/kvm/hyp.S:1377: Error: attempt to move .org backwards scripts/Makefile.build:294: recipe for target 'arch/arm64/kvm/hyp.o' failed make[1]: *** [arch/arm64/kvm/hyp.o] Error 1 Makefile:946: recipe for target 'arch/arm64/kvm' failed Not pretty, but at least works on the current toolchains. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: alternative: Merge alternative-asm.h into alternative.hMarc Zyngier
commit 8d883b23aed73cad844ba48051c7e96eddf0f51c upstream. asm/alternative-asm.h and asm/alternative.h are extremely similar, and really deserve to live in the same file (as this makes further modufications a bit easier). Fold the content of alternative-asm.h into alternative.h, and update the few users. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Add AArch32 instruction set condition code checksPunit Agrawal
commit 0be0e44c182c4f13df13903fd1377671d157d7b7 upstream. Port support for AArch32 instruction condition code checking from arm to arm64. Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: lib: use pair accessors for copy_*_user routinesWill Deacon
commit 23e94994464a7281838785675e09c8ed1055f62f upstream. The AArch64 instruction set contains load/store pair memory accessors, so use these in our copy_*_user routines to transfer 16 bytes per iteration. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64/uaccess: fix sparse errorsMichael S. Tsirkin
commit 58fff51784cb5e1bcc06a1417be26eec4288507c upstream. virtio wants to read bitwise types from userspace using get_user. At the moment this triggers sparse errors, since the value is passed through an integer. Fix that up using __force. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: kernel: Move config_sctlr_el1James Morse
commit 870828e57b141eff76a5325f20e4691dd2a599b1 upstream Later patches need config_sctlr_el1 to set/clear bits in the sctlr_el1 register. This patch moves this function into header a file. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Emulate SETEND for AArch32 tasksSuzuki K. Poulose
commit 2d888f48e056119495847a269a435d5c3d9df349 upstream. Emulate deprecated 'setend' instruction for AArch32 bit tasks. setend [le/be] - Sets the endianness of EL0 On systems with CPUs which support mixed endian at EL0, the hardware support for the instruction can be enabled by setting the SCTLR_EL1.SED bit. Like the other emulated instructions it is controlled by an entry in /proc/sys/abi/. For more information see : Documentation/arm64/legacy_instructions.txt The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which will be reflected in the PSTATE.E in AArch32 context. This patch also restores the native endianness for the execution of signal handlers, since the process could have changed the endianness. Note: All CPUs on the system must have mixed endian support at EL0. Once the handler is registered, hotplugging a CPU which doesn't support mixed endian, could lead to unexpected results/behavior in applications. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: kconfig: move emulation option under kernel featuresWill Deacon
commit 1b907f46db07405b6676addb91b32c546d772fcd upstream. Having the instruction emulation submenu underneath "platform selection" is a great way to hide options we don't want people to use, but somewhat confusing when you stumble across it there. Move the menuconfig option underneath "kernel features", where it makes a bit more sense. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Consolidate hotplug notifier for instruction emulationSuzuki K. Poulose
commit 736d474f0fafd1486f178570bc47660ee9dfdef8 upstream. As of now each insn_emulation has a cpu hotplug notifier that enables/disables the CPU feature bit for the functionality. This patch re-arranges the code, such that there is only one notifier that runs through the list of registered emulation hooks and runs their corresponding set_hw_mode. We do nothing when a CPU is dying as we will set the appropriate bits as it comes back online based on the state of the hooks. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> [catalin.marinas@arm.com: fix pr_warn compilation error] [catalin.marinas@arm.com: remove unnecessary "insn" check] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: fix return code check when changing emulation handlerWill Deacon
commit 909633957d85561dab7655d69a9d17dd16231d92 upstream. update_insn_emulation_mode() returns 0 on success, so we should be treating any non-zero values as failure, rather than the other way around. Otherwise, writes to the sysctl file controlling the emulation are ignored and immediately rolled back. Reported-by: Gene Hackmann <ghackmann@google.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Trace emulation of AArch32 legacy instructionsPunit Agrawal
commit d784e2988a3e70a6f1047e80e01465a903ea2eba upstream. Introduce an event to trace the usage of emulated instructions. The trace event is intended to help identify and encourage the migration of legacy software using the emulation features. Use this event to trace usage of swp and CP15 barrier emulation. Acked-by: Steven Rostedt <rostedt@goodmis.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Emulate CP15 Barrier instructionsPunit Agrawal
commit c852f320584600a372646055d8229e063949eee7 upstream. The CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB instructions respectively. Some implementations may provide the ability to disable the CP15 barriers by disabling the CP15BEN bit in SCTLR_EL1. If not enabled, the encodings for these instructions become undefined. To support legacy software using these instructions, this patch register hooks to - * emulate CP15 barriers and warn the user about their use * toggle CP15BEN in SCTLR_EL1 Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Port SWP/SWPB emulation support from armPunit Agrawal
commit bd35a4adc4131c530ec7d90242555eac7b3dbe3f upstream. The SWP instruction was deprecated in the ARMv6 architecture. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. With ARMv8, the option to enable these instructions through System Control Register was dropped as well. To support legacy applications using these instructions, port the emulation of the SWP and SWPB instructions from the arm port to arm64. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Add support for hooks to handle undefined instructionsPunit Agrawal
commit 9b79f52d1a702dd5b160f9d2ee0199c3122809bb upstream. Add support to register hooks for undefined instructions. The handlers will be called when the undefined instruction and the processor state (as contained in pstate) match criteria used at registration. Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Add framework for legacy instruction emulationPunit Agrawal
commit 587064b610c703f259317d00dc37bf6d40f4fc74 upstream. Typically, providing support for legacy instructions requires emulating the behaviour of instructions whose encodings have become undefined. If the instructions haven't been removed from the architecture, there maybe an option in the implementation to turn on/off the support for these instructions. Create common infrastructure to support legacy instruction emulation. In addition to emulation, also provide an option to support hardware execution when supported. The default execution mode (one of undef, emulate, hw exeuction) is dependent on the state of the instruction (deprecated or obsolete) in the architecture and can specified at the time of registering the instruction handlers. The runtime state of the emulation can be controlled by writing to individual nodes in sysctl. The expected default behaviour is documented as part of this patch. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: alternative: Introduce feature for GICv3 CPU interfaceMarc Zyngier
commit 94a9e04aa16abd1194d9b4158c618ba87f5d01e6 upstream. Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF) to indicate that we have a system register GIC CPU interface This will help KVM switching to alternative instruction patching. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Extract feature parsing code from cpu_errata.cMarc Zyngier
commit 359b706473b47da3c93bd99fd10d798fe411ab67 upstream. As we detect more architectural features at runtime, it makes sense to reuse the existing framework whilst avoiding to call a feature an erratum... This patch extract the core capability parsing, moves it into a new file (cpufeature.c), and let the CPU errata detection code use it. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> [david: trivial merge fixups] Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: alternatives: fix pr_fmt string for consistencyWill Deacon
commit c9453a3ab1a39230a18b3db1d677bbb2bd782baa upstream. Consistently use the plural form for alternatives pr_fmt strings. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Track system support for mixed endian EL0Suzuki K. Poulose
commit 04597a65c5efc207257a736d339c6f2f5b00250f upstream. This patch keeps track of the mixed endian EL0 support across the system and provides helper functions to export it. The status is a boolean indicating whether all the CPUs on the system supports mixed endian at EL0. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: David Brown <david.brown@linaro.org>
2015-12-03arm64: Provide a namespace to NCAPSFabio Estevam
commit 06f9eb884be81431d54d7d37390043e3b5b7f14a upstream Building arm64.allmodconfig leads to the following warning: usb/gadget/function/f_ncm.c:203:0: warning: "NCAPS" redefined #define NCAPS (USB_CDC_NCM_NCAP_ETH_FILTER | USB_CDC_NCM_NCAP_CRC_MODE) ^ In file included from /home/build/work/batch/arch/arm64/include/asm/io.h:32:0, from /home/build/work/batch/include/linux/clocksource.h:19, from /home/build/work/batch/include/clocksource/arm_arch_timer.h:19, from /home/build/work/batch/arch/arm64/include/asm/arch_timer.h:27, from /home/build/work/batch/arch/arm64/include/asm/timex.h:19, from /home/build/work/batch/include/linux/timex.h:65, from /home/build/work/batch/include/linux/sched.h:19, from /home/build/work/batch/arch/arm64/include/asm/compat.h:25, from /home/build/work/batch/arch/arm64/include/asm/stat.h:23, from /home/build/work/batch/include/linux/stat.h:5, from /home/build/work/batch/include/linux/module.h:10, from /home/build/work/batch/drivers/usb/gadget/function/f_ncm.c:19: arch/arm64/include/asm/cpufeature.h:27:0: note: this is the location of the previous definition #define NCAPS 2 So add a ARM64 prefix to avoid such problem. Reported-by: Olof's autobuilder <build@lixom.net> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Will Deacon <will.deacon@arm.com> [david: Resolve simple merge conflicts] Signed-off-by: David Brown <david.brown@linaro.org>
2015-11-16Merge remote-tracking branch 'origin/v3.18/topic/pcie/master' into ↵Alex Shi
linux-linaro-lsk-v3.18 Conflicts solution: /* Using the latest version dts', that is except the serial * port definition in juno.dts, others keep the pcie/master * version. */ arch/arm64/boot/dts/arm/Makefile arch/arm64/boot/dts/arm/juno-clocks.dtsi arch/arm64/boot/dts/arm/juno.dts
2015-11-13ARM: imx6: correct i.MX6 PCIe interrupt routingLucas Stach
commit 1a9fa190956f45c1e58c4d8bfa5ac051691ea590 upstream. The PCIe interrupts are also routed through the GPC. This has been missed from the conversion to stacked IRQ domains as the PCIe controller uses an explicit interrupt map and thus doesn't inherit the SoC global interrupt parent. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit cdda95937ec1f62e29f6e89c87600555594f3dec) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx6: allow booting with old DTLucas Stach
The GPC rewrite to IRQ domains has been on the premise that it may break suspend/resume for new kernels on old DT, but otherwise keep things working from a user perspective. This was an accepted compromise to be able to move the GIC cleanup forward. What actually happened was that booting a new kernel on an old DT crashes before even the console is up, so the user does not even see the warning that the DT is too old. The warning message suggests that this has been known before, which is clearly unacceptable. Fix the early crash by mapping the GPC memory space if the IRQ controller doesn't claim it. This keeps at least CPUidle and the needed CPU wakeup workarounds working. With this fixed the system is able to boot up properly minus the expected suspend/resume breakage. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 634a603760c26d163ff92751d91ac7b859e879c4) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx6: Warn when an old DT is detectedMarc Zyngier
Now that the GPC has been converted to be a full blown irqchip (and not a mole on the side of the GIC), booting a new kernel with an old DT is likely to result in a rough ride for the user. This patch makes sure such a situation is promptly detected and the user made aware that a DT update is in order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 14517564795a5cd22e2da3119037f9883383fae9) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx6: Allow GPC interrupts affinity to be changedMarc Zyngier
While converting the GPC code to a stacked irqchip, we lost the possibility to change the CPU affinity of an interrupt routed through the GPC. This patch restore the expected behaviour by forwarding the affinity setup to the underlying irqchip (GIC). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit e33b67523f556aa7ddb09f1c7fa4de5c080670c9) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx6: convert GPC to stacked domainsMarc Zyngier
IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit b923ff6af0d5a806a3996dac6d4393cd9792d0f4) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx6: gpc: Add PU power domain for GPU/VPUPhilipp Zabel
When generic pm domain support is enabled, the PGC can be used to completely gate power to the PU power domain containing GPU3D, GPU2D, and VPU cores. This code triggers the PGC powerdown sequence to disable the GPU/VPU isolation cells and gate power and then disables the PU regulator. To reenable, the reverse powerup sequence is triggered after the PU regulator is enabled again. The GPU and VPU devices in the PU power domain temporarily need to be clocked during powerup, so that the reset machinery can work. [Avoid explicit regulator enabling in probe, unless !PM] Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 00eb60a8b4f7a4aa00fd8abd68c2dc7aec55df19) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading()Sebastian Andrzej Siewior
imx6q_opp_check_speed_grading() remaps memory to the base variable and never unmaps it. I can't see how this can be of any use later so here I unmap it. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 23bec1727505de4adf3f0ed228bcb8b1a3d2e551) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx: support arm power off in cpuidle for i.mx6sxAnson Huang
This patch introduces an independent cpuidle driver for i.MX6SX, and supports arm power off in idle, totally 3 levels of cpuidle are supported as below: 1. ARM WFI; 2. SOC in WAIT mode; 3. SOC in WAIT mode + ARM power off. ARM power off can save at least 5mW power. This patch also replaces imx6q_enable_rbc with imx6_enable_rbc. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 05136f0897b526b9cd090c93b95bbd1b67c18cc5) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx6: fix bogus use of irq_get_irq_dataMarc Zyngier
The imx6 PM code seems to be quite creative in its use of irq_data, using something that is very much a hardware interrupt number where we expect a virtual one. Yes, it worked so far, but that's only luck, and it will definitely explode in 3.19. Fix it by using a pair of helper functions that deal with the actual hardware. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net> (cherry picked from commit 65bb688aab9424849e94f74d555542fa76cd3d5a) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx: irq: fix buggy usage of irq_data irq fieldMarc Zyngier
mach-imx directly references to the irq field in struct irq_data, and uses this to directly poke hardware register. But irq is the *virtual* irq number, something that has nothing to do with the actual HW irq (stored in the hwirq field). And once we put the stacked domain code in action, the whole thing explodes, as these two values are *very* different. Just replacing all instances of irq with hwirq fixes the issue. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net> (cherry picked from commit e2fd06f6be690a1a9697c0c6338843a35cbd70a3) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: imx: add enet init for i.mx6sxFugang Duan
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> (cherry picked from commit 8f0b287e0d60521052c9c4d818f670e40f4ee0e6) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: dts: imx6: phyFLEX: Add CAN supportChristian Hemp
Add CAN support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01). Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 1b61feea3f65fd401a778d705c7223e9f7da529f) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: dts: imx6: phyFLEX: Add PCIeChristian Hemp
Add PCIe support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01). Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 9924546b29f5f20d0596ebc76ab1ddc1f716cae4) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: dts: imx6: phyFLEX: Set correct interrupt for pmicChristian Hemp
The PMIC interrupt was changed from modul revision 1 to 2. Revision 1 was declared as a prototype and is not in series by any customers. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit c082fd422e66df8e2492e27219192a773ccb72e5) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: dts: imx6: phyFLEX: Enable gpmi in module fileChristian Hemp
The nand is on the module (PFL-A-02) and not on the baseboard (PBA-B-01). Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 0019d18213924a9cd10fda59e2c8b83ece54fd58) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: dts: imx6: phyFLEX: set nodes in alphabetical orderChristian Hemp
The gmpi and fec node were not in alphabatical order. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 350088320b80f2d87a29798458f9db1c3b206ca9) Signed-off-by: Alex Shi <alex.shi@linaro.org>
2015-11-13ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boardsDmitry Lavnikevich
Audio on phyFLEX boards is presented by tlv320aic3007 codec connected over SSI interface. Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 8fa91c8e55e58e673c21c809ca5d9fcb26da0141) Signed-off-by: Alex Shi <alex.shi@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-06 17:56:07 +0000