From 13b8a68a9c08410f03047fc888706299b5b75754 Mon Sep 17 00:00:00 2001 From: Mario Bambagini Date: Tue, 16 Jun 2015 22:32:30 +0200 Subject: added tabs instead of spaces Tabs have been inserted instead of spaces to indent the code correctly. Same error fixed four times. Signed-off-by: Mario Bambagini Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2-bf60x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c index 4cb59fe9be70..fcfa00821f12 100644 --- a/drivers/pinctrl/pinctrl-adi2-bf60x.c +++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c @@ -394,25 +394,25 @@ static const unsigned short ppi2_16b_mux[] = { static const unsigned short lp0_mux[] = { P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2, P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7, - 0 + 0 }; static const unsigned short lp1_mux[] = { P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2, P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7, - 0 + 0 }; static const unsigned short lp2_mux[] = { P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2, P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7, - 0 + 0 }; static const unsigned short lp3_mux[] = { P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2, P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7, - 0 + 0 }; static const struct adi_pin_group adi_pin_groups[] = { -- cgit v1.2.3 From b5599df20f1ee45cef811a7ab1c7358d9faf7bf8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 26 Jun 2015 01:42:04 +0300 Subject: sh-pfc: r8a7790: remove non-existing GPIO pins GPIO banks 1 and 2 are missing pins 30 and 31. Remove them. Signed-off-by: Laurent Pinchart Signed-off-by: Sergei Shtylyov Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index baab81ead9ff..fc344a7c2b53 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -27,10 +27,27 @@ #include "core.h" #include "sh_pfc.h" +#define PORT_GP_30(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ + PORT_GP_30(1, fn, sfx), \ + PORT_GP_30(2, fn, sfx), \ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx) -- cgit v1.2.3 From 441f77dcf8defcebb4477fea6db03624259fef42 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 26 Jun 2015 01:43:07 +0300 Subject: sh-pfc: r8a7791: remove non-existing GPIO pins GPIO banks 1 and 7 are missing pins 26 to 31. Remove them. Signed-off-by: Laurent Pinchart Signed-off-by: Sergei Shtylyov Tested-by: Geert Uytterhoeven Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 3ddf23ec9f0b..25e8117f5a1a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -14,15 +14,30 @@ #include "core.h" #include "sh_pfc.h" +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ + PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ - PORT_GP_32(7, fn, sfx) + PORT_GP_26(7, fn, sfx) enum { PINMUX_RESERVED = 0, -- cgit v1.2.3 From 9612327c1ffcdacc863b3baf0a3c8c9b0837ffd2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 19 Jun 2015 23:32:27 +0800 Subject: pinctrl: imx: add i.mx6ul subdriver Add i.MX6UL pinctrl driver support. Signed-off-by: Anson Huang Signed-off-by: Frank Li Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx6ul.c | 323 +++++++++++++++++++++++++++++ 3 files changed, 331 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6ul.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 12ef544b4894..debe1219d76d 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -87,6 +87,13 @@ config PINCTRL_IMX6SX help Say Y here to enable the imx6sx pinctrl driver +config PINCTRL_IMX6UL + bool "IMX6UL pinctrl driver" + depends on SOC_IMX6UL + select PINCTRL_IMX + help + Say Y here to enable the imx6ul pinctrl driver + config PINCTRL_IMX7D bool "IMX7D pinctrl driver" depends on SOC_IMX7D diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 343cb436ab17..d44c9e253f21 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o +obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c new file mode 100644 index 000000000000..b182be729382 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx6ul_pads { + MX6UL_PAD_RESERVE0 = 0, + MX6UL_PAD_RESERVE1 = 1, + MX6UL_PAD_RESERVE2 = 2, + MX6UL_PAD_RESERVE3 = 3, + MX6UL_PAD_RESERVE4 = 4, + MX6UL_PAD_RESERVE5 = 5, + MX6UL_PAD_RESERVE6 = 6, + MX6UL_PAD_RESERVE7 = 7, + MX6UL_PAD_RESERVE8 = 8, + MX6UL_PAD_RESERVE9 = 9, + MX6UL_PAD_RESERVE10 = 10, + MX6UL_PAD_SNVS_TAMPER4 = 11, + MX6UL_PAD_RESERVE12 = 12, + MX6UL_PAD_RESERVE13 = 13, + MX6UL_PAD_RESERVE14 = 14, + MX6UL_PAD_RESERVE15 = 15, + MX6UL_PAD_RESERVE16 = 16, + MX6UL_PAD_JTAG_MOD = 17, + MX6UL_PAD_JTAG_TMS = 18, + MX6UL_PAD_JTAG_TDO = 19, + MX6UL_PAD_JTAG_TDI = 20, + MX6UL_PAD_JTAG_TCK = 21, + MX6UL_PAD_JTAG_TRST_B = 22, + MX6UL_PAD_GPIO1_IO00 = 23, + MX6UL_PAD_GPIO1_IO01 = 24, + MX6UL_PAD_GPIO1_IO02 = 25, + MX6UL_PAD_GPIO1_IO03 = 26, + MX6UL_PAD_GPIO1_IO04 = 27, + MX6UL_PAD_GPIO1_IO05 = 28, + MX6UL_PAD_GPIO1_IO06 = 29, + MX6UL_PAD_GPIO1_IO07 = 30, + MX6UL_PAD_GPIO1_IO08 = 31, + MX6UL_PAD_GPIO1_IO09 = 32, + MX6UL_PAD_UART1_TX_DATA = 33, + MX6UL_PAD_UART1_RX_DATA = 34, + MX6UL_PAD_UART1_CTS_B = 35, + MX6UL_PAD_UART1_RTS_B = 36, + MX6UL_PAD_UART2_TX_DATA = 37, + MX6UL_PAD_UART2_RX_DATA = 38, + MX6UL_PAD_UART2_CTS_B = 39, + MX6UL_PAD_UART2_RTS_B = 40, + MX6UL_PAD_UART3_TX_DATA = 41, + MX6UL_PAD_UART3_RX_DATA = 42, + MX6UL_PAD_UART3_CTS_B = 43, + MX6UL_PAD_UART3_RTS_B = 44, + MX6UL_PAD_UART4_TX_DATA = 45, + MX6UL_PAD_UART4_RX_DATA = 46, + MX6UL_PAD_UART5_TX_DATA = 47, + MX6UL_PAD_UART5_RX_DATA = 48, + MX6UL_PAD_ENET1_RX_DATA0 = 49, + MX6UL_PAD_ENET1_RX_DATA1 = 50, + MX6UL_PAD_ENET1_RX_EN = 51, + MX6UL_PAD_ENET1_TX_DATA0 = 52, + MX6UL_PAD_ENET1_TX_DATA1 = 53, + MX6UL_PAD_ENET1_TX_EN = 54, + MX6UL_PAD_ENET1_TX_CLK = 55, + MX6UL_PAD_ENET1_RX_ER = 56, + MX6UL_PAD_ENET2_RX_DATA0 = 57, + MX6UL_PAD_ENET2_RX_DATA1 = 58, + MX6UL_PAD_ENET2_RX_EN = 59, + MX6UL_PAD_ENET2_TX_DATA0 = 60, + MX6UL_PAD_ENET2_TX_DATA1 = 61, + MX6UL_PAD_ENET2_TX_EN = 62, + MX6UL_PAD_ENET2_TX_CLK = 63, + MX6UL_PAD_ENET2_RX_ER = 64, + MX6UL_PAD_LCD_CLK = 65, + MX6UL_PAD_LCD_ENABLE = 66, + MX6UL_PAD_LCD_HSYNC = 67, + MX6UL_PAD_LCD_VSYNC = 68, + MX6UL_PAD_LCD_RESET = 69, + MX6UL_PAD_LCD_DATA00 = 70, + MX6UL_PAD_LCD_DATA01 = 71, + MX6UL_PAD_LCD_DATA02 = 72, + MX6UL_PAD_LCD_DATA03 = 73, + MX6UL_PAD_LCD_DATA04 = 74, + MX6UL_PAD_LCD_DATA05 = 75, + MX6UL_PAD_LCD_DATA06 = 76, + MX6UL_PAD_LCD_DATA07 = 77, + MX6UL_PAD_LCD_DATA08 = 78, + MX6UL_PAD_LCD_DATA09 = 79, + MX6UL_PAD_LCD_DATA10 = 80, + MX6UL_PAD_LCD_DATA11 = 81, + MX6UL_PAD_LCD_DATA12 = 82, + MX6UL_PAD_LCD_DATA13 = 83, + MX6UL_PAD_LCD_DATA14 = 84, + MX6UL_PAD_LCD_DATA15 = 85, + MX6UL_PAD_LCD_DATA16 = 86, + MX6UL_PAD_LCD_DATA17 = 87, + MX6UL_PAD_LCD_DATA18 = 88, + MX6UL_PAD_LCD_DATA19 = 89, + MX6UL_PAD_LCD_DATA20 = 90, + MX6UL_PAD_LCD_DATA21 = 91, + MX6UL_PAD_LCD_DATA22 = 92, + MX6UL_PAD_LCD_DATA23 = 93, + MX6UL_PAD_NAND_RE_B = 94, + MX6UL_PAD_NAND_WE_B = 95, + MX6UL_PAD_NAND_DATA00 = 96, + MX6UL_PAD_NAND_DATA01 = 97, + MX6UL_PAD_NAND_DATA02 = 98, + MX6UL_PAD_NAND_DATA03 = 99, + MX6UL_PAD_NAND_DATA04 = 100, + MX6UL_PAD_NAND_DATA05 = 101, + MX6UL_PAD_NAND_DATA06 = 102, + MX6UL_PAD_NAND_DATA07 = 103, + MX6UL_PAD_NAND_ALE = 104, + MX6UL_PAD_NAND_WP_B = 105, + MX6UL_PAD_NAND_READY_B = 106, + MX6UL_PAD_NAND_CE0_B = 107, + MX6UL_PAD_NAND_CE1_B = 108, + MX6UL_PAD_NAND_CLE = 109, + MX6UL_PAD_NAND_DQS = 110, + MX6UL_PAD_SD1_CMD = 111, + MX6UL_PAD_SD1_CLK = 112, + MX6UL_PAD_SD1_DATA0 = 113, + MX6UL_PAD_SD1_DATA1 = 114, + MX6UL_PAD_SD1_DATA2 = 115, + MX6UL_PAD_SD1_DATA3 = 116, + MX6UL_PAD_CSI_MCLK = 117, + MX6UL_PAD_CSI_PIXCLK = 118, + MX6UL_PAD_CSI_VSYNC = 119, + MX6UL_PAD_CSI_HSYNC = 120, + MX6UL_PAD_CSI_DATA00 = 121, + MX6UL_PAD_CSI_DATA01 = 122, + MX6UL_PAD_CSI_DATA02 = 123, + MX6UL_PAD_CSI_DATA03 = 124, + MX6UL_PAD_CSI_DATA04 = 125, + MX6UL_PAD_CSI_DATA05 = 126, + MX6UL_PAD_CSI_DATA06 = 127, + MX6UL_PAD_CSI_DATA07 = 128, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), +}; + +static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { + .pins = imx6ul_pinctrl_pads, + .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), +}; + +static struct of_device_id imx6ul_pinctrl_of_match[] = { + { .compatible = "fsl,imx6ul-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6ul_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info); +} + +static struct platform_driver imx6ul_pinctrl_driver = { + .driver = { + .name = "imx6ul-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match), + }, + .probe = imx6ul_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6ul_pinctrl_init(void) +{ + return platform_driver_register(&imx6ul_pinctrl_driver); +} +arch_initcall(imx6ul_pinctrl_init); + +static void __exit imx6ul_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6ul_pinctrl_driver); +} +module_exit(imx6ul_pinctrl_exit); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("Freescale imx6ul pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From fb00de771b0c35fc42212272596ddb07bf120b21 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 18 Jun 2015 14:42:45 +0900 Subject: pinctrl: simplify of_pinctrl_get() This commit does not change the logic at all. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/devicetree.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 0bbf7d71b281..fe04e748dfe4 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -97,13 +97,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, struct pinctrl_dev *of_pinctrl_get(struct device_node *np) { - struct pinctrl_dev *pctldev; - - pctldev = get_pinctrl_dev_from_of_node(np); - if (!pctldev) - return NULL; - - return pctldev; + return get_pinctrl_dev_from_of_node(np); } static int dt_to_map_one_config(struct pinctrl *p, const char *statename, -- cgit v1.2.3 From ba5f94cd566ac562c9374729baab156886759946 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 17 Jun 2015 23:47:25 -0700 Subject: pinctrl: qcom: spmi-mpp: Transition to generic dt binding parser Use the newly introduced extensible generic dt parser instead of rolling our own dt parsing functions. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 130 ++++---------------------------- 1 file changed, 16 insertions(+), 114 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 3121de9b6331..b247a17bc2af 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -129,15 +129,17 @@ struct pmic_mpp_state { struct gpio_chip chip; }; -struct pmic_mpp_bindings { - const char *property; - unsigned param; +static const struct pinconf_generic_params pmic_mpp_bindings[] = { + {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, + {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE, 0}, }; -static struct pmic_mpp_bindings pmic_mpp_bindings[] = { - {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE}, - {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE}, +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pmic_conf_items[] = { + PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), + PCONFDUMP(PMIC_MPP_CONF_ANALOG_MODE, "analog output", NULL, false), }; +#endif static const char *const pmic_mpp_groups[] = { "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", @@ -204,118 +206,11 @@ static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, return 0; } -static int pmic_mpp_parse_dt_config(struct device_node *np, - struct pinctrl_dev *pctldev, - unsigned long **configs, - unsigned int *nconfs) -{ - struct pmic_mpp_bindings *par; - unsigned long cfg; - int ret, i; - u32 val; - - for (i = 0; i < ARRAY_SIZE(pmic_mpp_bindings); i++) { - par = &pmic_mpp_bindings[i]; - ret = of_property_read_u32(np, par->property, &val); - - /* property not found */ - if (ret == -EINVAL) - continue; - - /* use zero as default value, when no value is specified */ - if (ret) - val = 0; - - dev_dbg(pctldev->dev, "found %s with value %u\n", - par->property, val); - - cfg = pinconf_to_config_packed(par->param, val); - - ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg); - if (ret) - return ret; - } - - return 0; -} - -static int pmic_mpp_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, - unsigned *reserv, unsigned *nmaps, - enum pinctrl_map_type type) -{ - unsigned long *configs = NULL; - unsigned nconfs = 0; - struct property *prop; - const char *group; - int ret; - - ret = pmic_mpp_parse_dt_config(np, pctldev, &configs, &nconfs); - if (ret < 0) - return ret; - - if (!nconfs) - return 0; - - ret = of_property_count_strings(np, "pins"); - if (ret < 0) - goto exit; - - ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "pins", prop, group) { - ret = pinctrl_utils_add_map_configs(pctldev, map, - reserv, nmaps, group, - configs, nconfs, type); - if (ret < 0) - break; - } -exit: - kfree(configs); - return ret; -} - -static int pmic_mpp_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *nmaps) -{ - struct device_node *np; - enum pinctrl_map_type type; - unsigned reserv; - int ret; - - ret = 0; - *map = NULL; - *nmaps = 0; - reserv = 0; - type = PIN_MAP_TYPE_CONFIGS_GROUP; - - for_each_child_of_node(np_config, np) { - ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, - &reserv, nmaps, type); - if (ret) - break; - - ret = pmic_mpp_dt_subnode_to_map(pctldev, np, map, &reserv, - nmaps, type); - if (ret) - break; - } - - if (ret < 0) - pinctrl_utils_dt_free_map(pctldev, *map, *nmaps); - - return ret; -} - static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { .get_groups_count = pmic_mpp_get_groups_count, .get_group_name = pmic_mpp_get_group_name, .get_group_pins = pmic_mpp_get_group_pins, - .dt_node_to_map = pmic_mpp_dt_node_to_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, .dt_free_map = pinctrl_utils_dt_free_map, }; @@ -594,6 +489,7 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, } static const struct pinconf_ops pmic_mpp_pinconf_ops = { + .is_generic = true, .pin_config_group_get = pmic_mpp_config_get, .pin_config_group_set = pmic_mpp_config_set, .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, @@ -866,6 +762,12 @@ static int pmic_mpp_probe(struct platform_device *pdev) pctrldesc->pins = pindesc; pctrldesc->npins = npins; + pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); + pctrldesc->custom_params = pmic_mpp_bindings; +#ifdef CONFIG_DEBUG_FS + pctrldesc->custom_conf_items = pmic_conf_items; +#endif + for (i = 0; i < npins; i++, pindesc++) { pad = &pads[i]; pindesc->drv_data = pad; -- cgit v1.2.3 From 7682b3740dd7e3039ec9885b423f7e68f0dc24d0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 17 Jun 2015 23:47:26 -0700 Subject: pinctrl: qcom: spmi-mpp: Fixes related to enable handling There's currently no way to re-enable a mpp block once you've entered a state that disables the state, this patch makes it possible to leave the bias-high-impedance state. Also read the enable state from the hardware on probe. With this in place the is_enabled variable is accurately tracking the state of the hardware and we can use that for the debug output as well. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index b247a17bc2af..6d9abeea810d 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -354,6 +354,9 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pad = pctldev->desc->pins[pin].drv_data; + /* Make it possible to enable the pin, by not setting high impedance */ + pad->is_enabled = true; + for (i = 0; i < nconfs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); @@ -445,7 +448,13 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT; val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK; - return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; + + return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); } static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, @@ -453,7 +462,7 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, { struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); struct pmic_mpp_pad *pad; - int ret, val; + int ret; static const char *const biases[] = { "0.6kOhm", "10kOhm", "30kOhm", "Disabled" @@ -464,9 +473,7 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); - val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); - - if (val < 0 || !(val >> PMIC_MPP_REG_MASTER_EN_SHIFT)) { + if (!pad->is_enabled) { seq_puts(s, " ---"); } else { @@ -706,8 +713,12 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; - /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ - pad->is_enabled = true; + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); + if (val < 0) + return val; + + pad->is_enabled = !!val; + return 0; } -- cgit v1.2.3 From eaaf5dd46457c4fa3a9e2d1be775821d4e72773c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 17 Jun 2015 23:47:27 -0700 Subject: pinctrl: qcom: spmi-mpp: Introduce defines for MODE_CTL Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 6d9abeea810d..745c37dea7d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -85,6 +85,14 @@ #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 +#define PMIC_MPP_MODE_DIGITAL_INPUT 0 +#define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 +#define PMIC_MPP_MODE_DIGITAL_BIDIR 2 +#define PMIC_MPP_MODE_ANALOG_BIDIR 3 +#define PMIC_MPP_MODE_ANALOG_INPUT 4 +#define PMIC_MPP_MODE_ANALOG_OUTPUT 5 +#define PMIC_MPP_MODE_CURRENT_SINK 6 + #define PMIC_MPP_PHYSICAL_OFFSET 1 /* Qualcomm specific pin configurations */ @@ -248,20 +256,20 @@ static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, pad->function = function; if (!pad->analog_mode) { - val = 0; /* just digital input */ + val = PMIC_MPP_MODE_DIGITAL_INPUT; if (pad->output_enabled) { if (pad->input_enabled) - val = 2; /* digital input and output */ + val = PMIC_MPP_MODE_DIGITAL_BIDIR; else - val = 1; /* just digital output */ + val = PMIC_MPP_MODE_DIGITAL_OUTPUT; } } else { - val = 4; /* just analog input */ + val = PMIC_MPP_MODE_ANALOG_INPUT; if (pad->output_enabled) { if (pad->input_enabled) - val = 3; /* analog input and output */ + val = PMIC_MPP_MODE_ANALOG_BIDIR; else - val = 5; /* just analog output */ + val = PMIC_MPP_MODE_ANALOG_OUTPUT; } } @@ -654,32 +662,32 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, dir &= PMIC_MPP_REG_MODE_DIR_MASK; switch (dir) { - case 0: + case PMIC_MPP_MODE_DIGITAL_INPUT: pad->input_enabled = true; pad->output_enabled = false; pad->analog_mode = false; break; - case 1: + case PMIC_MPP_MODE_DIGITAL_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; pad->analog_mode = false; break; - case 2: + case PMIC_MPP_MODE_DIGITAL_BIDIR: pad->input_enabled = true; pad->output_enabled = true; pad->analog_mode = false; break; - case 3: + case PMIC_MPP_MODE_ANALOG_BIDIR: pad->input_enabled = true; pad->output_enabled = true; pad->analog_mode = true; break; - case 4: + case PMIC_MPP_MODE_ANALOG_INPUT: pad->input_enabled = true; pad->output_enabled = false; pad->analog_mode = true; break; - case 5: + case PMIC_MPP_MODE_ANALOG_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; pad->analog_mode = true; -- cgit v1.2.3 From 0e948042c4203b97e44370993ef042c945308282 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 17 Jun 2015 23:47:28 -0700 Subject: pinctrl: qcom: spmi-mpp: Implement support for sink mode The MPP supports three modes; digital, analog and sink mode. This patch implements support for the latter. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 5 + drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 115 +++++++++++++-------- 2 files changed, 76 insertions(+), 44 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index ed19991aad35..d29fb96a57d3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -134,6 +134,11 @@ to specify in a pin configuration subnode: and/or output-high, output-low MPP could operate as Bidirectional Logic, Analog Input, Analog Output. +- qcom,sink-mode: + Usage: optional + Value type: or + Definition: Selects sink mode of operation + - qcom,amux-route: Usage: optional Value type: diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 745c37dea7d0..9dde023640ba 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -62,6 +62,7 @@ #define PMIC_MPP_REG_DIG_IN_CTL 0x43 #define PMIC_MPP_REG_EN_CTL 0x46 #define PMIC_MPP_REG_AIN_CTL 0x4a +#define PMIC_MPP_REG_SINK_CTL 0x4c /* PMIC_MPP_REG_MODE_CTL */ #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 @@ -98,6 +99,7 @@ /* Qualcomm specific pin configurations */ #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) #define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2) +#define PMIC_MPP_CONF_SINK_MODE (PIN_CONFIG_END + 3) /** * struct pmic_mpp_pad - keep current MPP settings @@ -109,11 +111,13 @@ * @input_enabled: Set to true if MPP input buffer logic is enabled. * @analog_mode: Set to true when MPP should operate in Analog Input, Analog * Output or Bidirectional Analog mode. + * @sink_mode: Boolean indicating if ink mode is slected * @num_sources: Number of power-sources supported by this MPP. * @power_source: Current power-source used. * @amux_input: Set the source for analog input. * @pullup: Pullup resistor value. Valid in Bidirectional mode only. * @function: See pmic_mpp_functions[]. + * @drive_strength: Amount of current in sink mode */ struct pmic_mpp_pad { u16 base; @@ -123,11 +127,13 @@ struct pmic_mpp_pad { bool output_enabled; bool input_enabled; bool analog_mode; + bool sink_mode; unsigned int num_sources; unsigned int power_source; unsigned int amux_input; unsigned int pullup; unsigned int function; + unsigned int drive_strength; }; struct pmic_mpp_state { @@ -140,12 +146,14 @@ struct pmic_mpp_state { static const struct pinconf_generic_params pmic_mpp_bindings[] = { {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE, 0}, + {"qcom,sink-mode", PMIC_MPP_CONF_SINK_MODE, 0}, }; #ifdef CONFIG_DEBUG_FS static const struct pin_config_item pmic_conf_items[] = { PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), PCONFDUMP(PMIC_MPP_CONF_ANALOG_MODE, "analog output", NULL, false), + PCONFDUMP(PMIC_MPP_CONF_SINK_MODE, "sink mode", NULL, false), }; #endif @@ -243,33 +251,28 @@ static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, return 0; } -static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, - unsigned pin) +static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, + struct pmic_mpp_pad *pad) { - struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); - struct pmic_mpp_pad *pad; unsigned int val; - int ret; - - pad = pctldev->desc->pins[pin].drv_data; - - pad->function = function; - if (!pad->analog_mode) { - val = PMIC_MPP_MODE_DIGITAL_INPUT; + if (pad->analog_mode) { + val = PMIC_MPP_MODE_ANALOG_INPUT; if (pad->output_enabled) { if (pad->input_enabled) - val = PMIC_MPP_MODE_DIGITAL_BIDIR; + val = PMIC_MPP_MODE_ANALOG_BIDIR; else - val = PMIC_MPP_MODE_DIGITAL_OUTPUT; + val = PMIC_MPP_MODE_ANALOG_OUTPUT; } + } else if (pad->sink_mode) { + val = PMIC_MPP_MODE_CURRENT_SINK; } else { - val = PMIC_MPP_MODE_ANALOG_INPUT; + val = PMIC_MPP_MODE_DIGITAL_INPUT; if (pad->output_enabled) { if (pad->input_enabled) - val = PMIC_MPP_MODE_ANALOG_BIDIR; + val = PMIC_MPP_MODE_DIGITAL_BIDIR; else - val = PMIC_MPP_MODE_ANALOG_OUTPUT; + val = PMIC_MPP_MODE_DIGITAL_OUTPUT; } } @@ -277,9 +280,22 @@ static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT; val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK; - ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); - if (ret < 0) - return ret; + return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); +} + +static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, + unsigned pin) +{ + struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_mpp_pad *pad; + unsigned int val; + int ret; + + pad = pctldev->desc->pins[pin].drv_data; + + pad->function = function; + + ret = pmic_mpp_write_mode_ctl(state, pad); val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; @@ -339,9 +355,15 @@ static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, case PMIC_MPP_CONF_AMUX_ROUTE: arg = pad->amux_input; break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pad->drive_strength; + break; case PMIC_MPP_CONF_ANALOG_MODE: arg = pad->analog_mode; break; + case PMIC_MPP_CONF_SINK_MODE: + arg = pad->sink_mode; + break; default: return -EINVAL; } @@ -403,13 +425,19 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pad->output_enabled = true; pad->out_value = arg; break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pad->drive_strength; + break; case PMIC_MPP_CONF_AMUX_ROUTE: if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) return -EINVAL; pad->amux_input = arg; break; case PMIC_MPP_CONF_ANALOG_MODE: - pad->analog_mode = true; + pad->analog_mode = !!arg; + break; + case PMIC_MPP_CONF_SINK_MODE: + pad->sink_mode = !!arg; break; default: return -EINVAL; @@ -434,29 +462,7 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, if (ret < 0) return ret; - if (!pad->analog_mode) { - val = 0; /* just digital input */ - if (pad->output_enabled) { - if (pad->input_enabled) - val = 2; /* digital input and output */ - else - val = 1; /* just digital output */ - } - } else { - val = 4; /* just analog input */ - if (pad->output_enabled) { - if (pad->input_enabled) - val = 3; /* analog input and output */ - else - val = 5; /* just analog output */ - } - } - - val = val << PMIC_MPP_REG_MODE_DIR_SHIFT; - val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT; - val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK; - - ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); + ret = pmic_mpp_write_mode_ctl(state, pad); if (ret < 0) return ret; @@ -476,6 +482,9 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, "0.6kOhm", "10kOhm", "30kOhm", "Disabled" }; + static const char *const modes[] = { + "digital", "analog", "sink" + }; pad = pctldev->desc->pins[pin].drv_data; @@ -495,7 +504,7 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, } seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); - seq_printf(s, " %-4s", pad->analog_mode ? "ana" : "dig"); + seq_printf(s, " %-7s", modes[pad->analog_mode ? 1 : (pad->sink_mode ? 2 : 0)]); seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); seq_printf(s, " vin-%d", pad->power_source); seq_printf(s, " %-8s", biases[pad->pullup]); @@ -666,31 +675,43 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, pad->input_enabled = true; pad->output_enabled = false; pad->analog_mode = false; + pad->sink_mode = false; break; case PMIC_MPP_MODE_DIGITAL_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; pad->analog_mode = false; + pad->sink_mode = false; break; case PMIC_MPP_MODE_DIGITAL_BIDIR: pad->input_enabled = true; pad->output_enabled = true; pad->analog_mode = false; + pad->sink_mode = false; break; case PMIC_MPP_MODE_ANALOG_BIDIR: pad->input_enabled = true; pad->output_enabled = true; pad->analog_mode = true; + pad->sink_mode = false; break; case PMIC_MPP_MODE_ANALOG_INPUT: pad->input_enabled = true; pad->output_enabled = false; pad->analog_mode = true; + pad->sink_mode = false; break; case PMIC_MPP_MODE_ANALOG_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; pad->analog_mode = true; + pad->sink_mode = false; + break; + case PMIC_MPP_MODE_CURRENT_SINK: + pad->input_enabled = false; + pad->output_enabled = true; + pad->analog_mode = false; + pad->sink_mode = true; break; default: dev_err(state->dev, "unknown MPP direction\n"); @@ -721,6 +742,12 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); + if (val < 0) + return val; + + pad->drive_strength = val; + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); if (val < 0) return val; -- cgit v1.2.3 From 6e908892025885b07e804dc6c05aab6ce1e06832 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:01 +0900 Subject: pinctrl: UniPhier: add UniPhier pinctrl core support The core support for the pinctrl drivers for all the UniPhier SoCs. Changes in v2: - drop vogus THIS_MODULE because this file is always built-in - drop vogus "include because this file is always built-in Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/uniphier/Kconfig | 8 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 684 +++++++++++++++++++++++ drivers/pinctrl/uniphier/pinctrl-uniphier.h | 217 +++++++ 6 files changed, 912 insertions(+) create mode 100644 drivers/pinctrl/uniphier/Kconfig create mode 100644 drivers/pinctrl/uniphier/Makefile create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 100d9ac2ae1f..e6362c61b560 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -240,6 +240,7 @@ source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" +source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f4216d9347e2..f6710a8a1503 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,5 +51,6 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ +obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig new file mode 100644 index 000000000000..37e39c8dd030 --- /dev/null +++ b/drivers/pinctrl/uniphier/Kconfig @@ -0,0 +1,8 @@ +if ARCH_UNIPHIER + +config PINCTRL_UNIPHIER_CORE + bool + select PINMUX + select GENERIC_PINCONF + +endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile new file mode 100644 index 000000000000..748aa1b4e420 --- /dev/null +++ b/drivers/pinctrl/uniphier/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c new file mode 100644 index 000000000000..918f3b643f1b --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -0,0 +1,684 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-uniphier.h" + +struct uniphier_pinctrl_priv { + struct pinctrl_dev *pctldev; + struct regmap *regmap; + struct uniphier_pinctrl_socdata *socdata; +}; + +static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->socdata->groups_count; +} + +static const char *uniphier_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->socdata->groups[selector].name; +} + +static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + + *pins = priv->socdata->groups[selector].pins; + *num_pins = priv->socdata->groups[selector].num_pins; + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) +{ + const struct pinctrl_pin_desc *pin = &pctldev->desc->pins[offset]; + const char *pull_dir, *drv_str; + + switch (uniphier_pin_get_pull_dir(pin->drv_data)) { + case UNIPHIER_PIN_PULL_UP: + pull_dir = "UP"; + break; + case UNIPHIER_PIN_PULL_DOWN: + pull_dir = "DOWN"; + break; + case UNIPHIER_PIN_PULL_NONE: + pull_dir = "NONE"; + break; + default: + BUG(); + } + + switch (uniphier_pin_get_drv_str(pin->drv_data)) { + case UNIPHIER_PIN_DRV_4_8: + drv_str = "4/8(mA)"; + break; + case UNIPHIER_PIN_DRV_8_12_16_20: + drv_str = "8/12/16/20(mA)"; + break; + case UNIPHIER_PIN_DRV_FIXED_4: + drv_str = "4(mA)"; + break; + case UNIPHIER_PIN_DRV_FIXED_5: + drv_str = "5(mA)"; + break; + case UNIPHIER_PIN_DRV_FIXED_8: + drv_str = "8(mA)"; + break; + case UNIPHIER_PIN_DRV_NONE: + drv_str = "NONE"; + break; + default: + BUG(); + } + + seq_printf(s, " PULL_DIR=%s DRV_STR=%s", pull_dir, drv_str); +} +#endif + +static const struct pinctrl_ops uniphier_pctlops = { + .get_groups_count = uniphier_pctl_get_groups_count, + .get_group_name = uniphier_pctl_get_group_name, + .get_group_pins = uniphier_pctl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = uniphier_pctl_pin_dbg_show, +#endif + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, + const struct pinctrl_pin_desc *pin, + enum pin_config_param param) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + enum uniphier_pin_pull_dir pull_dir = + uniphier_pin_get_pull_dir(pin->drv_data); + unsigned int pupdctrl, reg, shift, val; + unsigned int expected = 1; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull_dir == UNIPHIER_PIN_PULL_NONE) + return 0; + if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED || + pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) + return -EINVAL; + expected = 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED) + return 0; + if (pull_dir != UNIPHIER_PIN_PULL_UP) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) + return 0; + if (pull_dir != UNIPHIER_PIN_PULL_DOWN) + return -EINVAL; + break; + default: + BUG(); + } + + pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data); + + reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; + shift = pupdctrl % 32; + + ret = regmap_read(priv->regmap, reg, &val); + if (ret) + return ret; + + val = (val >> shift) & 1; + + return (val == expected) ? 0 : -EINVAL; +} + +static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, + const struct pinctrl_pin_desc *pin, + u16 *strength) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + enum uniphier_pin_drv_str drv_str = + uniphier_pin_get_drv_str(pin->drv_data); + const unsigned int strength_4_8[] = {4, 8}; + const unsigned int strength_8_12_16_20[] = {8, 12, 16, 20}; + const unsigned int *supported_strength; + unsigned int drvctrl, reg, shift, mask, width, val; + int ret; + + switch (drv_str) { + case UNIPHIER_PIN_DRV_4_8: + supported_strength = strength_4_8; + width = 1; + break; + case UNIPHIER_PIN_DRV_8_12_16_20: + supported_strength = strength_8_12_16_20; + width = 2; + break; + case UNIPHIER_PIN_DRV_FIXED_4: + *strength = 4; + return 0; + case UNIPHIER_PIN_DRV_FIXED_5: + *strength = 5; + return 0; + case UNIPHIER_PIN_DRV_FIXED_8: + *strength = 8; + return 0; + default: + /* drive strength control is not supported for this pin */ + return -EINVAL; + } + + drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); + drvctrl *= width; + + reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE : + UNIPHIER_PINCTRL_DRVCTRL_BASE; + + reg += drvctrl / 32 * 4; + shift = drvctrl % 32; + mask = (1U << width) - 1; + + ret = regmap_read(priv->regmap, reg, &val); + if (ret) + return ret; + + *strength = supported_strength[(val >> shift) & mask]; + + return 0; +} + +static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, + const struct pinctrl_pin_desc *pin) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data); + unsigned int val; + int ret; + + if (iectrl == UNIPHIER_PIN_IECTRL_NONE) + /* This pin is always input-enabled. */ + return 0; + + ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val); + if (ret) + return ret; + + return val & BIT(iectrl) ? 0 : -EINVAL; +} + +static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs) +{ + const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin]; + enum pin_config_param param = pinconf_to_config_param(*configs); + bool has_arg = false; + u16 arg; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = uniphier_conf_pin_bias_get(pctldev, pin_desc, param); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ret = uniphier_conf_pin_drive_get(pctldev, pin_desc, &arg); + has_arg = true; + break; + case PIN_CONFIG_INPUT_ENABLE: + ret = uniphier_conf_pin_input_enable_get(pctldev, pin_desc); + break; + default: + /* unsupported parameter */ + ret = -EINVAL; + break; + } + + if (ret == 0 && has_arg) + *configs = pinconf_to_config_packed(param, arg); + + return ret; +} + +static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev, + const struct pinctrl_pin_desc *pin, + enum pin_config_param param, + u16 arg) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + enum uniphier_pin_pull_dir pull_dir = + uniphier_pin_get_pull_dir(pin->drv_data); + unsigned int pupdctrl, reg, shift; + unsigned int val = 1; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull_dir == UNIPHIER_PIN_PULL_NONE) + return 0; + if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED || + pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) { + dev_err(pctldev->dev, + "can not disable pull register for pin %u (%s)\n", + pin->number, pin->name); + return -EINVAL; + } + val = 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED && arg != 0) + return 0; + if (pull_dir != UNIPHIER_PIN_PULL_UP) { + dev_err(pctldev->dev, + "pull-up is unsupported for pin %u (%s)\n", + pin->number, pin->name); + return -EINVAL; + } + if (arg == 0) { + dev_err(pctldev->dev, "pull-up can not be total\n"); + return -EINVAL; + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED && arg != 0) + return 0; + if (pull_dir != UNIPHIER_PIN_PULL_DOWN) { + dev_err(pctldev->dev, + "pull-down is unsupported for pin %u (%s)\n", + pin->number, pin->name); + return -EINVAL; + } + if (arg == 0) { + dev_err(pctldev->dev, "pull-down can not be total\n"); + return -EINVAL; + } + break; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (pull_dir == UNIPHIER_PIN_PULL_NONE) { + dev_err(pctldev->dev, + "pull-up/down is unsupported for pin %u (%s)\n", + pin->number, pin->name); + return -EINVAL; + } + + if (arg == 0) + return 0; /* configuration ingored */ + break; + default: + BUG(); + } + + pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data); + + reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; + shift = pupdctrl % 32; + + return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift); +} + +static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, + const struct pinctrl_pin_desc *pin, + u16 strength) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + enum uniphier_pin_drv_str drv_str = + uniphier_pin_get_drv_str(pin->drv_data); + const unsigned int strength_4_8[] = {4, 8, -1}; + const unsigned int strength_8_12_16_20[] = {8, 12, 16, 20, -1}; + const unsigned int *supported_strength; + unsigned int drvctrl, reg, shift, mask, width, val; + + switch (drv_str) { + case UNIPHIER_PIN_DRV_4_8: + supported_strength = strength_4_8; + width = 1; + break; + case UNIPHIER_PIN_DRV_8_12_16_20: + supported_strength = strength_8_12_16_20; + width = 2; + break; + default: + dev_err(pctldev->dev, + "cannot change drive strength for pin %u (%s)\n", + pin->number, pin->name); + return -EINVAL; + } + + for (val = 0; supported_strength[val] > 0; val++) { + if (supported_strength[val] > strength) + break; + } + + if (val == 0) { + dev_err(pctldev->dev, + "unsupported drive strength %u mA for pin %u (%s)\n", + strength, pin->number, pin->name); + return -EINVAL; + } + + val--; + + drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); + drvctrl *= width; + + reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE : + UNIPHIER_PINCTRL_DRVCTRL_BASE; + + reg += drvctrl / 32 * 4; + shift = drvctrl % 32; + mask = (1U << width) - 1; + + return regmap_update_bits(priv->regmap, reg, + mask << shift, val << shift); +} + +static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, + const struct pinctrl_pin_desc *pin, + u16 enable) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data); + + if (enable == 0) { + /* + * Multiple pins share one input enable, so per-pin disabling + * is impossible. + */ + dev_err(pctldev->dev, "unable to disable input\n"); + return -EINVAL; + } + + if (iectrl == UNIPHIER_PIN_IECTRL_NONE) + /* This pin is always input-enabled. nothing to do. */ + return 0; + + return regmap_update_bits(priv->regmap, UNIPHIER_PINCTRL_IECTRL, + BIT(iectrl), BIT(iectrl)); +} + +static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin]; + int i, ret; + + for (i = 0; i < num_configs; i++) { + enum pin_config_param param = + pinconf_to_config_param(configs[i]); + u16 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + ret = uniphier_conf_pin_bias_set(pctldev, pin_desc, + param, arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ret = uniphier_conf_pin_drive_set(pctldev, pin_desc, + arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + ret = uniphier_conf_pin_input_enable(pctldev, + pin_desc, arg); + break; + default: + dev_err(pctldev->dev, + "unsupported configuration parameter %u\n", + param); + return -EINVAL; + } + + if (ret) + return ret; + } + + return 0; +} + +static int uniphier_conf_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long *configs, + unsigned num_configs) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const unsigned *pins = priv->socdata->groups[selector].pins; + unsigned num_pins = priv->socdata->groups[selector].num_pins; + int i, ret; + + for (i = 0; i < num_pins; i++) { + ret = uniphier_conf_pin_config_set(pctldev, pins[i], + configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops uniphier_confops = { + .is_generic = true, + .pin_config_get = uniphier_conf_pin_config_get, + .pin_config_set = uniphier_conf_pin_config_set, + .pin_config_group_set = uniphier_conf_pin_config_group_set, +}; + +static int uniphier_pmx_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->socdata->functions_count; +} + +static const char *uniphier_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->socdata->functions[selector].name; +} + +static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned *num_groups) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + + *groups = priv->socdata->functions[selector].groups; + *num_groups = priv->socdata->functions[selector].num_groups; + + return 0; +} + +static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, + unsigned muxval) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned mux_bits = priv->socdata->mux_bits; + unsigned reg_stride = priv->socdata->reg_stride; + unsigned reg, reg_end, shift, mask; + int ret; + + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; + reg_end = reg + reg_stride; + shift = pin * mux_bits % 32; + mask = (1U << mux_bits) - 1; + + /* + * If reg_stride is greater than 4, the MSB of each pinsel shall be + * stored in the offset+4. + */ + for (; reg < reg_end; reg += 4) { + ret = regmap_update_bits(priv->regmap, reg, + mask << shift, muxval << shift); + if (ret) + return ret; + muxval >>= mux_bits; + } + + if (priv->socdata->load_pinctrl) { + ret = regmap_write(priv->regmap, + UNIPHIER_PINCTRL_LOAD_PINMUX, 1); + if (ret) + return ret; + } + + /* some pins need input-enabling */ + return uniphier_conf_pin_input_enable(pctldev, + &pctldev->desc->pins[pin], 1); +} + +static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned func_selector, + unsigned group_selector) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct uniphier_pinctrl_group *grp = + &priv->socdata->groups[group_selector]; + int i; + int ret; + + for (i = 0; i < grp->num_pins; i++) { + ret = uniphier_pmx_set_one_mux(pctldev, grp->pins[i], + grp->muxvals[i]); + if (ret) + return ret; + } + + return 0; +} + +static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct uniphier_pinctrl_group *groups = priv->socdata->groups; + int groups_count = priv->socdata->groups_count; + enum uniphier_pinmux_gpio_range_type range_type; + int i, j; + + if (strstr(range->name, "irq")) + range_type = UNIPHIER_PINMUX_GPIO_RANGE_IRQ; + else + range_type = UNIPHIER_PINMUX_GPIO_RANGE_PORT; + + for (i = 0; i < groups_count; i++) { + if (groups[i].range_type != range_type) + continue; + + for (j = 0; j < groups[i].num_pins; j++) + if (groups[i].pins[j] == offset) + goto found; + } + + dev_err(pctldev->dev, "pin %u does not support GPIO\n", offset); + return -EINVAL; + +found: + return uniphier_pmx_set_one_mux(pctldev, offset, groups[i].muxvals[j]); +} + +static const struct pinmux_ops uniphier_pmxops = { + .get_functions_count = uniphier_pmx_get_functions_count, + .get_function_name = uniphier_pmx_get_function_name, + .get_function_groups = uniphier_pmx_get_function_groups, + .set_mux = uniphier_pmx_set_mux, + .gpio_request_enable = uniphier_pmx_gpio_request_enable, + .strict = true, +}; + +int uniphier_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *desc, + struct uniphier_pinctrl_socdata *socdata) +{ + struct device *dev = &pdev->dev; + struct uniphier_pinctrl_priv *priv; + + if (!socdata || + !socdata->groups || + !socdata->groups_count || + !socdata->functions || + !socdata->functions_count || + !socdata->mux_bits || + !socdata->reg_stride) { + dev_err(dev, "pinctrl socdata lacks necessary members\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(priv->regmap)) { + dev_err(dev, "failed to get regmap\n"); + return PTR_ERR(priv->regmap); + } + + priv->socdata = socdata; + desc->pctlops = &uniphier_pctlops; + desc->pmxops = &uniphier_pmxops; + desc->confops = &uniphier_confops; + + priv->pctldev = pinctrl_register(desc, dev, priv); + if (IS_ERR(priv->pctldev)) { + dev_err(dev, "failed to register UniPhier pinctrl driver\n"); + return PTR_ERR(priv->pctldev); + } + + platform_set_drvdata(pdev, priv); + + return 0; +} +EXPORT_SYMBOL_GPL(uniphier_pinctrl_probe); + +int uniphier_pinctrl_remove(struct platform_device *pdev) +{ + struct uniphier_pinctrl_priv *priv = platform_get_drvdata(pdev); + + pinctrl_unregister(priv->pctldev); + + return 0; +} +EXPORT_SYMBOL_GPL(uniphier_pinctrl_remove); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h new file mode 100644 index 000000000000..e1e98b868be5 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCTRL_UNIPHIER_H__ +#define __PINCTRL_UNIPHIER_H__ + +#include +#include +#include + +#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0 +#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700 +#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800 +#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900 +#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00 +#define UNIPHIER_PINCTRL_IECTRL 0xd00 + +/* input enable control register bit */ +#define UNIPHIER_PIN_IECTRL_SHIFT 0 +#define UNIPHIER_PIN_IECTRL_BITS 8 +#define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \ + - 1) + +/* drive strength control register number */ +#define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \ + (UNIPHIER_PIN_IECTRL_BITS)) +#define UNIPHIER_PIN_DRVCTRL_BITS 9 +#define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \ + - 1) + +/* supported drive strength (mA) */ +#define UNIPHIER_PIN_DRV_STR_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \ + (UNIPHIER_PIN_DRVCTRL_BITS)) +#define UNIPHIER_PIN_DRV_STR_BITS 3 +#define UNIPHIER_PIN_DRV_STR_MASK ((1UL << (UNIPHIER_PIN_DRV_STR_BITS)) \ + - 1) + +/* pull-up / pull-down register number */ +#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_STR_SHIFT) + \ + (UNIPHIER_PIN_DRV_STR_BITS)) +#define UNIPHIER_PIN_PUPDCTRL_BITS 9 +#define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\ + - 1) + +/* direction of pull register */ +#define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \ + (UNIPHIER_PIN_PUPDCTRL_BITS)) +#define UNIPHIER_PIN_PULL_DIR_BITS 3 +#define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\ + - 1) + +#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG +#error "unable to pack pin attributes." +#endif + +#define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK) + +/* selectable drive strength */ +enum uniphier_pin_drv_str { + UNIPHIER_PIN_DRV_4_8, /* 2 level control: 4/8 mA */ + UNIPHIER_PIN_DRV_8_12_16_20, /* 4 level control: 8/12/16/20 mA */ + UNIPHIER_PIN_DRV_FIXED_4, /* fixed to 4mA */ + UNIPHIER_PIN_DRV_FIXED_5, /* fixed to 5mA */ + UNIPHIER_PIN_DRV_FIXED_8, /* fixed to 8mA */ + UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */ +}; + +/* direction of pull register (no pin supports bi-directional pull biasing) */ +enum uniphier_pin_pull_dir { + UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */ + UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */ + UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */ + UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */ + UNIPHIER_PIN_PULL_NONE, /* no pull register */ +}; + +#define UNIPHIER_PIN_IECTRL(x) \ + (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT)) +#define UNIPHIER_PIN_DRVCTRL(x) \ + (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT)) +#define UNIPHIER_PIN_DRV_STR(x) \ + (((x) & (UNIPHIER_PIN_DRV_STR_MASK)) << (UNIPHIER_PIN_DRV_STR_SHIFT)) +#define UNIPHIER_PIN_PUPDCTRL(x) \ + (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT)) +#define UNIPHIER_PIN_PULL_DIR(x) \ + (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT)) + +#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_str, pupdctrl, pull_dir)\ + (UNIPHIER_PIN_IECTRL(iectrl) | \ + UNIPHIER_PIN_DRVCTRL(drvctrl) | \ + UNIPHIER_PIN_DRV_STR(drv_str) | \ + UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \ + UNIPHIER_PIN_PULL_DIR(pull_dir)) + +static inline unsigned int uniphier_pin_get_iectrl(void *drv_data) +{ + return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) & + UNIPHIER_PIN_IECTRL_MASK; +} + +static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data) +{ + return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & + UNIPHIER_PIN_DRVCTRL_MASK; +} + +static inline unsigned int uniphier_pin_get_drv_str(void *drv_data) +{ + return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_STR_SHIFT) & + UNIPHIER_PIN_DRV_STR_MASK; +} + +static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data) +{ + return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) & + UNIPHIER_PIN_PUPDCTRL_MASK; +} + +static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data) +{ + return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) & + UNIPHIER_PIN_PULL_DIR_MASK; +} + +enum uniphier_pinmux_gpio_range_type { + UNIPHIER_PINMUX_GPIO_RANGE_PORT, + UNIPHIER_PINMUX_GPIO_RANGE_IRQ, + UNIPHIER_PINMUX_GPIO_RANGE_NONE, +}; + +struct uniphier_pinctrl_group { + const char *name; + const unsigned *pins; + unsigned num_pins; + const unsigned *muxvals; + enum uniphier_pinmux_gpio_range_type range_type; +}; + +struct uniphier_pinmux_function { + const char *name; + const char * const *groups; + unsigned num_groups; +}; + +struct uniphier_pinctrl_socdata { + const struct uniphier_pinctrl_group *groups; + int groups_count; + const struct uniphier_pinmux_function *functions; + int functions_count; + unsigned mux_bits; + unsigned reg_stride; + bool load_pinctrl; +}; + +#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \ +{ \ + .number = a, \ + .name = b, \ + .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \ +} + +#define __UNIPHIER_PINCTRL_GROUP(grp, type) \ + { \ + .name = #grp, \ + .pins = grp##_pins, \ + .num_pins = ARRAY_SIZE(grp##_pins), \ + .muxvals = grp##_muxvals + \ + BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ + ARRAY_SIZE(grp##_muxvals)), \ + .range_type = type, \ + } + +#define UNIPHIER_PINCTRL_GROUP(grp) \ + __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE) + +#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \ + __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT) + +#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \ + __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ) + +#define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \ + { \ + .name = #grp, \ + .pins = array##_pins + ofst, \ + .num_pins = 1, \ + .muxvals = array##_muxvals + ofst, \ + } + +#define UNIPHIER_PINMUX_FUNCTION(func) \ + { \ + .name = #func, \ + .groups = func##_groups, \ + .num_groups = ARRAY_SIZE(func##_groups), \ + } + +struct platform_device; +struct pinctrl_desc; + +int uniphier_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *desc, + struct uniphier_pinctrl_socdata *socdata); + +int uniphier_pinctrl_remove(struct platform_device *pdev); + +#endif /* __PINCTRL_UNIPHIER_H__ */ -- cgit v1.2.3 From edd95a4a95f32c701e291e06016c6ca110ef65b7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:02 +0900 Subject: pinctrl: UniPhier: add UniPhier PH1-LD4 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Changes in v2: - sort groups and funcs alphabetically - add missing "emmc_dat8" group - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/uniphier/Kconfig | 4 + drivers/pinctrl/uniphier/Makefile | 2 + drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c | 886 +++++++++++++++++++++++++++++ 3 files changed, 892 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 37e39c8dd030..78d25df6d0fd 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -5,4 +5,8 @@ config PINCTRL_UNIPHIER_CORE select PINMUX select GENERIC_PINCONF +config PINCTRL_UNIPHIER_PH1_LD4 + tristate "UniPhier PH1-LD4 SoC pinctrl driver" + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 748aa1b4e420..b4bd042ac4f6 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o + +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c new file mode 100644 index 000000000000..7beb87e8f499 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c @@ -0,0 +1,886 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +#define DRIVER_NAME "ph1-ld4-pinctrl" + +static const struct pinctrl_pin_desc ph1_ld4_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "EA1", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_4_8, + 8, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "EA2", UNIPHIER_PIN_IECTRL_NONE, + 9, UNIPHIER_PIN_DRV_4_8, + 9, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "EA3", UNIPHIER_PIN_IECTRL_NONE, + 10, UNIPHIER_PIN_DRV_4_8, + 10, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "EA4", UNIPHIER_PIN_IECTRL_NONE, + 11, UNIPHIER_PIN_DRV_4_8, + 11, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "EA5", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_4_8, + 12, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(5, "EA6", UNIPHIER_PIN_IECTRL_NONE, + 13, UNIPHIER_PIN_DRV_4_8, + 13, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "EA7", UNIPHIER_PIN_IECTRL_NONE, + 14, UNIPHIER_PIN_DRV_4_8, + 14, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "EA8", 0, + 15, UNIPHIER_PIN_DRV_4_8, + 15, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "EA9", 0, + 16, UNIPHIER_PIN_DRV_4_8, + 16, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "EA10", 0, + 17, UNIPHIER_PIN_DRV_4_8, + 17, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "EA11", 0, + 18, UNIPHIER_PIN_DRV_4_8, + 18, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "EA12", 0, + 19, UNIPHIER_PIN_DRV_4_8, + 19, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(12, "EA13", 0, + 20, UNIPHIER_PIN_DRV_4_8, + 20, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(13, "EA14", 0, + 21, UNIPHIER_PIN_DRV_4_8, + 21, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(14, "EA15", 0, + 22, UNIPHIER_PIN_DRV_4_8, + 22, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(15, "ECLK", UNIPHIER_PIN_IECTRL_NONE, + 23, UNIPHIER_PIN_DRV_4_8, + 23, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(16, "XERWE0", UNIPHIER_PIN_IECTRL_NONE, + 24, UNIPHIER_PIN_DRV_4_8, + 24, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(17, "XERWE1", UNIPHIER_PIN_IECTRL_NONE, + 25, UNIPHIER_PIN_DRV_4_8, + 25, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(18, "ES0", UNIPHIER_PIN_IECTRL_NONE, + 27, UNIPHIER_PIN_DRV_4_8, + 27, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(19, "ES1", UNIPHIER_PIN_IECTRL_NONE, + 28, UNIPHIER_PIN_DRV_4_8, + 28, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(20, "ES2", UNIPHIER_PIN_IECTRL_NONE, + 29, UNIPHIER_PIN_DRV_4_8, + 29, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(21, "XERST", UNIPHIER_PIN_IECTRL_NONE, + 38, UNIPHIER_PIN_DRV_4_8, + 38, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(22, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_8_12_16_20, + 146, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(23, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_8_12_16_20, + 147, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(24, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_8_12_16_20, + 148, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(25, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_8_12_16_20, + 149, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(26, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_8_12_16_20, + 150, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(27, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_8_12_16_20, + 151, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(28, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE, + 24, UNIPHIER_PIN_DRV_8_12_16_20, + 152, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(29, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE, + 28, UNIPHIER_PIN_DRV_8_12_16_20, + 153, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(30, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_8_12_16_20, + 154, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(31, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_8_12_16_20, + 155, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(32, "RMII_RXD0", 6, + 39, UNIPHIER_PIN_DRV_4_8, + 39, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(33, "RMII_RXD1", 6, + 40, UNIPHIER_PIN_DRV_4_8, + 40, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(34, "RMII_CRS_DV", 6, + 41, UNIPHIER_PIN_DRV_4_8, + 41, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(35, "RMII_RXER", 6, + 42, UNIPHIER_PIN_DRV_4_8, + 42, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(36, "RMII_REFCLK", 6, + 43, UNIPHIER_PIN_DRV_4_8, + 43, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(37, "RMII_TXD0", 6, + 44, UNIPHIER_PIN_DRV_4_8, + 44, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(38, "RMII_TXD1", 6, + 45, UNIPHIER_PIN_DRV_4_8, + 45, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(39, "RMII_TXEN", 6, + 46, UNIPHIER_PIN_DRV_4_8, + 46, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(40, "MDC", 6, + 47, UNIPHIER_PIN_DRV_4_8, + 47, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(41, "MDIO", 6, + 48, UNIPHIER_PIN_DRV_4_8, + 48, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(42, "MDIO_INTL", 6, + 49, UNIPHIER_PIN_DRV_4_8, + 49, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(43, "PHYRSTL", 6, + 50, UNIPHIER_PIN_DRV_4_8, + 50, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_8_12_16_20, + 156, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(45, "SDCMD", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_8_12_16_20, + 157, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(46, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE, + 48, UNIPHIER_PIN_DRV_8_12_16_20, + 158, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(47, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_8_12_16_20, + 159, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(48, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE, + 56, UNIPHIER_PIN_DRV_8_12_16_20, + 160, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(49, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE, + 60, UNIPHIER_PIN_DRV_8_12_16_20, + 161, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(50, "SDCD", UNIPHIER_PIN_IECTRL_NONE, + 51, UNIPHIER_PIN_DRV_4_8, + 51, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(51, "SDWP", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_4_8, + 52, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(52, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE, + 53, UNIPHIER_PIN_DRV_4_8, + 53, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(53, "USB0VBUS", 0, + 54, UNIPHIER_PIN_DRV_4_8, + 54, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(54, "USB0OD", 0, + 55, UNIPHIER_PIN_DRV_4_8, + 55, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(55, "USB1VBUS", 0, + 56, UNIPHIER_PIN_DRV_4_8, + 56, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(56, "USB1OD", 0, + 57, UNIPHIER_PIN_DRV_4_8, + 57, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(57, "PCRESET", 0, + 58, UNIPHIER_PIN_DRV_4_8, + 58, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(58, "PCREG", 0, + 59, UNIPHIER_PIN_DRV_4_8, + 59, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(59, "PCCE2", 0, + 60, UNIPHIER_PIN_DRV_4_8, + 60, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(60, "PCVS1", 0, + 61, UNIPHIER_PIN_DRV_4_8, + 61, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(61, "PCCD2", 0, + 62, UNIPHIER_PIN_DRV_4_8, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(62, "PCCD1", 0, + 63, UNIPHIER_PIN_DRV_4_8, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(63, "PCREADY", 0, + 64, UNIPHIER_PIN_DRV_4_8, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(64, "PCDOE", 0, + 65, UNIPHIER_PIN_DRV_4_8, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "PCCE1", 0, + 66, UNIPHIER_PIN_DRV_4_8, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "PCWE", 0, + 67, UNIPHIER_PIN_DRV_4_8, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "PCOE", 0, + 68, UNIPHIER_PIN_DRV_4_8, + 68, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "PCWAIT", 0, + 69, UNIPHIER_PIN_DRV_4_8, + 69, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(69, "PCIOWR", 0, + 70, UNIPHIER_PIN_DRV_4_8, + 70, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(70, "PCIORD", 0, + 71, UNIPHIER_PIN_DRV_4_8, + 71, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(71, "HS0DIN0", 0, + 72, UNIPHIER_PIN_DRV_4_8, + 72, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(72, "HS0DIN1", 0, + 73, UNIPHIER_PIN_DRV_4_8, + 73, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(73, "HS0DIN2", 0, + 74, UNIPHIER_PIN_DRV_4_8, + 74, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(74, "HS0DIN3", 0, + 75, UNIPHIER_PIN_DRV_4_8, + 75, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(75, "HS0DIN4", 0, + 76, UNIPHIER_PIN_DRV_4_8, + 76, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(76, "HS0DIN5", 0, + 77, UNIPHIER_PIN_DRV_4_8, + 77, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(77, "HS0DIN6", 0, + 78, UNIPHIER_PIN_DRV_4_8, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(78, "HS0DIN7", 0, + 79, UNIPHIER_PIN_DRV_4_8, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "HS0BCLKIN", 0, + 80, UNIPHIER_PIN_DRV_4_8, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "HS0VALIN", 0, + 81, UNIPHIER_PIN_DRV_4_8, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "HS0SYNCIN", 0, + 82, UNIPHIER_PIN_DRV_4_8, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "HSDOUT0", 0, + 83, UNIPHIER_PIN_DRV_4_8, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "HSDOUT1", 0, + 84, UNIPHIER_PIN_DRV_4_8, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "HSDOUT2", 0, + 85, UNIPHIER_PIN_DRV_4_8, + 85, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "HSDOUT3", 0, + 86, UNIPHIER_PIN_DRV_4_8, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(86, "HSDOUT4", 0, + 87, UNIPHIER_PIN_DRV_4_8, + 87, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "HSDOUT5", 0, + 88, UNIPHIER_PIN_DRV_4_8, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(88, "HSDOUT6", 0, + 89, UNIPHIER_PIN_DRV_4_8, + 89, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "HSDOUT7", 0, + 90, UNIPHIER_PIN_DRV_4_8, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(90, "HSBCLKOUT", 0, + 91, UNIPHIER_PIN_DRV_4_8, + 91, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "HSVALOUT", 0, + 92, UNIPHIER_PIN_DRV_4_8, + 92, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(92, "HSSYNCOUT", 0, + 93, UNIPHIER_PIN_DRV_4_8, + 93, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(93, "AGCI", 3, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 162, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(94, "AGCR", 4, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 163, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(95, "AGCBS", 5, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 164, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(96, "IECOUT", 0, + 94, UNIPHIER_PIN_DRV_4_8, + 94, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(97, "ASMCK", 0, + 95, UNIPHIER_PIN_DRV_4_8, + 95, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(98, "ABCKO", UNIPHIER_PIN_IECTRL_NONE, + 96, UNIPHIER_PIN_DRV_4_8, + 96, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(99, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE, + 97, UNIPHIER_PIN_DRV_4_8, + 97, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(100, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE, + 98, UNIPHIER_PIN_DRV_4_8, + 98, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0, + 99, UNIPHIER_PIN_DRV_4_8, + 99, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE, + 100, UNIPHIER_PIN_DRV_4_8, + 100, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE, + 101, UNIPHIER_PIN_DRV_4_8, + 101, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(112, "HIN", 1, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(113, "VIN", 2, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(114, "TCON0", UNIPHIER_PIN_IECTRL_NONE, + 102, UNIPHIER_PIN_DRV_4_8, + 102, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(115, "TCON1", UNIPHIER_PIN_IECTRL_NONE, + 103, UNIPHIER_PIN_DRV_4_8, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(116, "TCON2", UNIPHIER_PIN_IECTRL_NONE, + 104, UNIPHIER_PIN_DRV_4_8, + 104, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(117, "TCON3", UNIPHIER_PIN_IECTRL_NONE, + 105, UNIPHIER_PIN_DRV_4_8, + 105, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(118, "TCON4", UNIPHIER_PIN_IECTRL_NONE, + 106, UNIPHIER_PIN_DRV_4_8, + 106, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(119, "TCON5", UNIPHIER_PIN_IECTRL_NONE, + 107, UNIPHIER_PIN_DRV_4_8, + 107, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(120, "TCON6", 0, + 108, UNIPHIER_PIN_DRV_4_8, + 108, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(121, "TCON7", 0, + 109, UNIPHIER_PIN_DRV_4_8, + 109, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "PWMA", 0, + 110, UNIPHIER_PIN_DRV_4_8, + 110, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(123, "XIRQ1", 0, + 111, UNIPHIER_PIN_DRV_4_8, + 111, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "XIRQ2", 0, + 112, UNIPHIER_PIN_DRV_4_8, + 112, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(125, "XIRQ3", 0, + 113, UNIPHIER_PIN_DRV_4_8, + 113, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(126, "XIRQ4", 0, + 114, UNIPHIER_PIN_DRV_4_8, + 114, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(127, "XIRQ5", 0, + 115, UNIPHIER_PIN_DRV_4_8, + 115, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(128, "XIRQ6", 0, + 116, UNIPHIER_PIN_DRV_4_8, + 116, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(129, "XIRQ7", 0, + 117, UNIPHIER_PIN_DRV_4_8, + 117, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(130, "XIRQ8", 0, + 118, UNIPHIER_PIN_DRV_4_8, + 118, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(131, "XIRQ9", 0, + 119, UNIPHIER_PIN_DRV_4_8, + 119, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(132, "XIRQ10", 0, + 120, UNIPHIER_PIN_DRV_4_8, + 120, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(133, "XIRQ11", 0, + 121, UNIPHIER_PIN_DRV_4_8, + 121, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(134, "XIRQ14", 0, + 122, UNIPHIER_PIN_DRV_4_8, + 122, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(135, "PORT00", 0, + 123, UNIPHIER_PIN_DRV_4_8, + 123, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(136, "PORT01", 0, + 124, UNIPHIER_PIN_DRV_4_8, + 124, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(137, "PORT02", 0, + 125, UNIPHIER_PIN_DRV_4_8, + 125, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(138, "PORT03", 0, + 126, UNIPHIER_PIN_DRV_4_8, + 126, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(139, "PORT04", 0, + 127, UNIPHIER_PIN_DRV_4_8, + 127, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(140, "PORT05", 0, + 128, UNIPHIER_PIN_DRV_4_8, + 128, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(141, "PORT06", 0, + 129, UNIPHIER_PIN_DRV_4_8, + 129, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(142, "PORT07", 0, + 130, UNIPHIER_PIN_DRV_4_8, + 130, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(143, "PORT10", 0, + 131, UNIPHIER_PIN_DRV_4_8, + 131, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(144, "PORT11", 0, + 132, UNIPHIER_PIN_DRV_4_8, + 132, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(145, "PORT12", 0, + 133, UNIPHIER_PIN_DRV_4_8, + 133, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(146, "PORT13", 0, + 134, UNIPHIER_PIN_DRV_4_8, + 134, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(147, "PORT14", 0, + 135, UNIPHIER_PIN_DRV_4_8, + 135, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(148, "PORT15", 0, + 136, UNIPHIER_PIN_DRV_4_8, + 136, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(149, "PORT16", 0, + 137, UNIPHIER_PIN_DRV_4_8, + 137, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(150, "PORT17", UNIPHIER_PIN_IECTRL_NONE, + 138, UNIPHIER_PIN_DRV_4_8, + 138, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(151, "PORT20", 0, + 139, UNIPHIER_PIN_DRV_4_8, + 139, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(152, "PORT21", 0, + 140, UNIPHIER_PIN_DRV_4_8, + 140, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(153, "PORT22", 0, + 141, UNIPHIER_PIN_DRV_4_8, + 141, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(154, "PORT23", 0, + 142, UNIPHIER_PIN_DRV_4_8, + 142, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(155, "PORT24", UNIPHIER_PIN_IECTRL_NONE, + 143, UNIPHIER_PIN_DRV_4_8, + 143, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(156, "PORT25", 0, + 144, UNIPHIER_PIN_DRV_4_8, + 144, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(157, "PORT26", 0, + 145, UNIPHIER_PIN_DRV_4_8, + 145, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(158, "XNFRE", UNIPHIER_PIN_IECTRL_NONE, + 31, UNIPHIER_PIN_DRV_4_8, + 31, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(159, "XNFWE", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_4_8, + 32, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(160, "NFALE", UNIPHIER_PIN_IECTRL_NONE, + 33, UNIPHIER_PIN_DRV_4_8, + 33, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(161, "NFCLE", UNIPHIER_PIN_IECTRL_NONE, + 34, UNIPHIER_PIN_DRV_4_8, + 34, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(162, "XNFWP", UNIPHIER_PIN_IECTRL_NONE, + 35, UNIPHIER_PIN_DRV_4_8, + 35, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(163, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_4_8, + 36, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(164, "NANDRYBY0", UNIPHIER_PIN_IECTRL_NONE, + 37, UNIPHIER_PIN_DRV_4_8, + 37, UNIPHIER_PIN_PULL_UP), +}; + +static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; +static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {102, 103}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {104, 105}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {108, 109}; +static const unsigned i2c2_muxvals[] = {2, 2}; +static const unsigned i2c3_pins[] = {108, 109}; +static const unsigned i2c3_muxvals[] = {3, 3}; +static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159, + 160, 161, 162, 163, 164}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {22, 23}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned uart0_pins[] = {85, 88}; +static const unsigned uart0_muxvals[] = {1, 1}; +static const unsigned uart1_pins[] = {155, 156}; +static const unsigned uart1_muxvals[] = {13, 13}; +static const unsigned uart1b_pins[] = {69, 70}; +static const unsigned uart1b_muxvals[] = {23, 23}; +static const unsigned uart2_pins[] = {128, 129}; +static const unsigned uart2_muxvals[] = {13, 13}; +static const unsigned uart3_pins[] = {110, 111}; +static const unsigned uart3_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {53, 54}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {55, 56}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {155, 156}; +static const unsigned usb2_muxvals[] = {4, 4}; +static const unsigned usb2b_pins[] = {67, 68}; +static const unsigned usb2b_muxvals[] = {23, 23}; +static const unsigned port_range0_pins[] = { + 135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */ + 143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */ + 151, 152, 153, 154, 155, 156, 157, 0, /* PORT2x */ + 1, 2, 3, 4, 5, 120, 121, 122, /* PORT3x */ + 24, 25, 26, 27, 28, 29, 30, 31, /* PORT4x */ + 40, 41, 42, 43, 44, 45, 46, 47, /* PORT5x */ + 48, 49, 50, 51, 52, 53, 54, 55, /* PORT6x */ + 56, 85, 84, 59, 82, 61, 64, 65, /* PORT7x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT8x */ + 66, 67, 68, 69, 70, 71, 72, 73, /* PORT9x */ + 74, 75, 89, 86, 78, 79, 80, 81, /* PORT10x */ + 60, 83, 58, 57, 88, 87, 77, 76, /* PORT11x */ + 90, 91, 92, 93, 94, 95, 96, 97, /* PORT12x */ + 98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */ + 103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */ +}; +static const unsigned port_range0_muxvals[] = { + 0, 0, 0, 0, 0, 0, 0, 0, /* PORT0x */ + 0, 0, 0, 0, 0, 0, 0, 0, /* PORT1x */ + 0, 0, 0, 0, 0, 0, 0, 15, /* PORT2x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ +}; +static const unsigned port_range1_pins[] = { + 7, /* PORT166 */ +}; +static const unsigned port_range1_muxvals[] = { + 15, /* PORT166 */ +}; +static const unsigned xirq_range0_pins[] = { + 151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */ + 130, 131, 132, 133, 62, /* XIRQ8-12 */ +}; +static const unsigned xirq_range0_muxvals[] = { + 14, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */ + 0, 0, 0, 0, 14, /* XIRQ8-12 */ +}; +static const unsigned xirq_range1_pins[] = { + 134, 63, /* XIRQ14-15 */ +}; +static const unsigned xirq_range1_muxvals[] = { + 0, 14, /* XIRQ14-15 */ +}; + +static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart1b), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb2b), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119), + UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1), +}; + +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const uart0_groups[] = {"uart0"}; +static const char * const uart1_groups[] = {"uart1", "uart1b"}; +static const char * const uart2_groups[] = {"uart2"}; +static const char * const uart3_groups[] = {"uart3"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2", "usb2b"}; +static const char * const port_groups[] = { + "port00", "port01", "port02", "port03", + "port04", "port05", "port06", "port07", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port20", "port21", "port22", "port23", + "port24", "port25", "port26", "port27", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port40", "port41", "port42", "port43", + "port44", "port45", "port46", "port47", + "port50", "port51", "port52", "port53", + "port54", "port55", "port56", "port57", + "port60", "port61", "port62", "port63", + "port64", "port65", "port66", "port67", + "port70", "port71", "port72", "port73", + "port74", "port75", "port76", "port77", + "port80", "port81", "port82", "port83", + "port84", "port85", "port86", "port87", + "port90", "port91", "port92", "port93", + "port94", "port95", "port96", "port97", + "port100", "port101", "port102", "port103", + "port104", "port105", "port106", "port107", + "port110", "port111", "port112", "port113", + "port114", "port115", "port116", "port117", + "port120", "port121", "port122", "port123", + "port124", "port125", "port126", "port127", + "port130", "port131", "port132", "port133", + "port134", "port135", "port136", "port137", + "port140", "port141", "port142", "port143", + "port144", "port145", "port146", "port147", + /* port150-164 missing */ + /* none */ "port165", +}; +static const char * const xirq_groups[] = { + "xirq0", "xirq1", "xirq2", "xirq3", + "xirq4", "xirq5", "xirq6", "xirq7", + "xirq8", "xirq9", "xirq10", "xirq11", + "xirq12", /* none*/ "xirq14", "xirq15", +}; + +static const struct uniphier_pinmux_function ph1_ld4_functions[] = { + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(port), + UNIPHIER_PINMUX_FUNCTION(xirq), +}; + +static struct uniphier_pinctrl_socdata ph1_ld4_pindata = { + .groups = ph1_ld4_groups, + .groups_count = ARRAY_SIZE(ph1_ld4_groups), + .functions = ph1_ld4_functions, + .functions_count = ARRAY_SIZE(ph1_ld4_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static struct pinctrl_desc ph1_ld4_pinctrl_desc = { + .name = DRIVER_NAME, + .pins = ph1_ld4_pins, + .npins = ARRAY_SIZE(ph1_ld4_pins), + .owner = THIS_MODULE, +}; + +static int ph1_ld4_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &ph1_ld4_pinctrl_desc, + &ph1_ld4_pindata); +} + +static const struct of_device_id ph1_ld4_pinctrl_match[] = { + { .compatible = "socionext,ph1-ld4-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ph1_ld4_pinctrl_match); + +static struct platform_driver ph1_ld4_pinctrl_driver = { + .probe = ph1_ld4_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = ph1_ld4_pinctrl_match, + }, +}; +module_platform_driver(ph1_ld4_pinctrl_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier PH1-LD4 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From b5cf4161ca8a54c79a05beaaf5d18c2c67193105 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:03 +0900 Subject: pinctrl: UniPhier: add UniPhier PH1-Pro4 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/uniphier/Kconfig | 4 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c | 1554 +++++++++++++++++++++++++++ 3 files changed, 1559 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 78d25df6d0fd..944803ffb5cc 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -9,4 +9,8 @@ config PINCTRL_UNIPHIER_PH1_LD4 tristate "UniPhier PH1-LD4 SoC pinctrl driver" select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_PRO4 + tristate "UniPhier PH1-Pro4 SoC pinctrl driver" + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b4bd042ac4f6..b1b597e0dccb 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c new file mode 100644 index 000000000000..96921e40da5f --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c @@ -0,0 +1,1554 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program5 is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +#define DRIVER_NAME "ph1-pro4-pinctrl" + +static const struct pinctrl_pin_desc ph1_pro4_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "CK24O", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_4_8, + 0, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "VC27A", UNIPHIER_PIN_IECTRL_NONE, + 1, UNIPHIER_PIN_DRV_4_8, + 1, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "CK27AI", UNIPHIER_PIN_IECTRL_NONE, + 2, UNIPHIER_PIN_DRV_4_8, + 2, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "CK27AO", UNIPHIER_PIN_IECTRL_NONE, + 3, UNIPHIER_PIN_DRV_4_8, + 3, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "CKSEL", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_4_8, + 4, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(5, "CK27AV", UNIPHIER_PIN_IECTRL_NONE, + 5, UNIPHIER_PIN_DRV_4_8, + 5, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "AEXCKA", UNIPHIER_PIN_IECTRL_NONE, + 6, UNIPHIER_PIN_DRV_4_8, + 6, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "ASEL", UNIPHIER_PIN_IECTRL_NONE, + 7, UNIPHIER_PIN_DRV_4_8, + 7, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "ARCRESET", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_4_8, + 8, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "ARCUNLOCK", UNIPHIER_PIN_IECTRL_NONE, + 9, UNIPHIER_PIN_DRV_4_8, + 9, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "XSRST", UNIPHIER_PIN_IECTRL_NONE, + 10, UNIPHIER_PIN_DRV_4_8, + 10, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "XNMIRQ", UNIPHIER_PIN_IECTRL_NONE, + 11, UNIPHIER_PIN_DRV_4_8, + 11, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(12, "XSCIRQ", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_4_8, + 12, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(13, "EXTRG", UNIPHIER_PIN_IECTRL_NONE, + 13, UNIPHIER_PIN_DRV_4_8, + 13, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(14, "TRCCLK", UNIPHIER_PIN_IECTRL_NONE, + 14, UNIPHIER_PIN_DRV_4_8, + 14, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(15, "TRCCTL", UNIPHIER_PIN_IECTRL_NONE, + 15, UNIPHIER_PIN_DRV_4_8, + 15, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(16, "TRCD0", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_4_8, + 16, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(17, "TRCD1", UNIPHIER_PIN_IECTRL_NONE, + 17, UNIPHIER_PIN_DRV_4_8, + 17, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(18, "TRCD2", UNIPHIER_PIN_IECTRL_NONE, + 18, UNIPHIER_PIN_DRV_4_8, + 18, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(19, "TRCD3", UNIPHIER_PIN_IECTRL_NONE, + 19, UNIPHIER_PIN_DRV_4_8, + 19, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(20, "TRCD4", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_4_8, + 20, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(21, "TRCD5", UNIPHIER_PIN_IECTRL_NONE, + 21, UNIPHIER_PIN_DRV_4_8, + 21, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(22, "TRCD6", UNIPHIER_PIN_IECTRL_NONE, + 22, UNIPHIER_PIN_DRV_4_8, + 22, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(23, "TRCD7", UNIPHIER_PIN_IECTRL_NONE, + 23, UNIPHIER_PIN_DRV_4_8, + 23, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(24, "XECS1", UNIPHIER_PIN_IECTRL_NONE, + 24, UNIPHIER_PIN_DRV_4_8, + 24, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(25, "ERXW", UNIPHIER_PIN_IECTRL_NONE, + 25, UNIPHIER_PIN_DRV_4_8, + 25, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(26, "XERWE0", UNIPHIER_PIN_IECTRL_NONE, + 26, UNIPHIER_PIN_DRV_4_8, + 26, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(27, "XERWE1", UNIPHIER_PIN_IECTRL_NONE, + 27, UNIPHIER_PIN_DRV_4_8, + 27, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(28, "ES0", UNIPHIER_PIN_IECTRL_NONE, + 28, UNIPHIER_PIN_DRV_4_8, + 28, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(29, "ES1", UNIPHIER_PIN_IECTRL_NONE, + 29, UNIPHIER_PIN_DRV_4_8, + 29, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(30, "ES2", UNIPHIER_PIN_IECTRL_NONE, + 30, UNIPHIER_PIN_DRV_4_8, + 30, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(31, "ED0", UNIPHIER_PIN_IECTRL_NONE, + 31, UNIPHIER_PIN_DRV_4_8, + 31, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(32, "ED1", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_4_8, + 32, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(33, "ED2", UNIPHIER_PIN_IECTRL_NONE, + 33, UNIPHIER_PIN_DRV_4_8, + 33, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(34, "ED3", UNIPHIER_PIN_IECTRL_NONE, + 34, UNIPHIER_PIN_DRV_4_8, + 34, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(35, "ED4", UNIPHIER_PIN_IECTRL_NONE, + 35, UNIPHIER_PIN_DRV_4_8, + 35, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(36, "ED5", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_4_8, + 36, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(37, "ED6", UNIPHIER_PIN_IECTRL_NONE, + 37, UNIPHIER_PIN_DRV_4_8, + 37, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(38, "ED7", UNIPHIER_PIN_IECTRL_NONE, + 38, UNIPHIER_PIN_DRV_4_8, + 38, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(39, "BOOTSWAP", UNIPHIER_PIN_IECTRL_NONE, + 39, UNIPHIER_PIN_DRV_NONE, + 39, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(40, "NFD0", UNIPHIER_PIN_IECTRL_NONE, + 2, UNIPHIER_PIN_DRV_8_12_16_20, + 40, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(41, "NFD1", UNIPHIER_PIN_IECTRL_NONE, + 3, UNIPHIER_PIN_DRV_8_12_16_20, + 41, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(42, "NFD2", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_8_12_16_20, + 42, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(43, "NFD3", UNIPHIER_PIN_IECTRL_NONE, + 5, UNIPHIER_PIN_DRV_8_12_16_20, + 43, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(44, "NFD4", UNIPHIER_PIN_IECTRL_NONE, + 6, UNIPHIER_PIN_DRV_8_12_16_20, + 44, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(45, "NFD5", UNIPHIER_PIN_IECTRL_NONE, + 7, UNIPHIER_PIN_DRV_8_12_16_20, + 45, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(46, "NFD6", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_8_12_16_20, + 46, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(47, "NFD7", UNIPHIER_PIN_IECTRL_NONE, + 9, UNIPHIER_PIN_DRV_8_12_16_20, + 47, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(48, "NFALE", UNIPHIER_PIN_IECTRL_NONE, + 48, UNIPHIER_PIN_DRV_4_8, + 48, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(49, "NFCLE", UNIPHIER_PIN_IECTRL_NONE, + 49, UNIPHIER_PIN_DRV_4_8, + 49, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(50, "XNFRE", UNIPHIER_PIN_IECTRL_NONE, + 50, UNIPHIER_PIN_DRV_4_8, + 50, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(51, "XNFWE", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_8_12_16_20, + 51, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(52, "XNFWP", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_4_8, + 52, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(53, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE, + 1, UNIPHIER_PIN_DRV_8_12_16_20, + 53, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(54, "NRYBY0", UNIPHIER_PIN_IECTRL_NONE, + 54, UNIPHIER_PIN_DRV_4_8, + 54, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(55, "DMDSCLTST", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_NONE, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(56, "DMDSDATST", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(57, "AGCI0", 3, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 55, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(58, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(59, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(60, "AGCBS0", 5, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 56, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(61, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(62, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(63, "ANTSHORT", UNIPHIER_PIN_IECTRL_NONE, + 57, UNIPHIER_PIN_DRV_4_8, + 57, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE, + 58, UNIPHIER_PIN_DRV_4_8, + 58, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE, + 59, UNIPHIER_PIN_DRV_4_8, + 59, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 60, UNIPHIER_PIN_DRV_4_8, + 60, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE, + 61, UNIPHIER_PIN_DRV_4_8, + 61, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE, + 62, UNIPHIER_PIN_DRV_4_8, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(69, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE, + 63, UNIPHIER_PIN_DRV_4_8, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(70, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 64, UNIPHIER_PIN_DRV_4_8, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE, + 65, UNIPHIER_PIN_DRV_4_8, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(72, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE, + 66, UNIPHIER_PIN_DRV_4_8, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(73, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE, + 67, UNIPHIER_PIN_DRV_4_8, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(74, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 68, UNIPHIER_PIN_DRV_4_8, + 68, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(75, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE, + 69, UNIPHIER_PIN_DRV_4_8, + 69, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(76, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE, + 70, UNIPHIER_PIN_DRV_4_8, + 70, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(77, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE, + 71, UNIPHIER_PIN_DRV_4_8, + 71, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(78, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 72, UNIPHIER_PIN_DRV_4_8, + 72, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE, + 73, UNIPHIER_PIN_DRV_4_8, + 73, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE, + 74, UNIPHIER_PIN_DRV_4_8, + 74, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE, + 75, UNIPHIER_PIN_DRV_4_8, + 75, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 76, UNIPHIER_PIN_DRV_4_8, + 76, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE, + 77, UNIPHIER_PIN_DRV_4_8, + 77, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE, + 78, UNIPHIER_PIN_DRV_4_8, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE, + 79, UNIPHIER_PIN_DRV_4_8, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(86, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 80, UNIPHIER_PIN_DRV_4_8, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE, + 81, UNIPHIER_PIN_DRV_4_8, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(88, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE, + 82, UNIPHIER_PIN_DRV_4_8, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE, + 83, UNIPHIER_PIN_DRV_4_8, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(90, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE, + 84, UNIPHIER_PIN_DRV_4_8, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE, + 85, UNIPHIER_PIN_DRV_4_8, + 85, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(92, "CKFEO", UNIPHIER_PIN_IECTRL_NONE, + 86, UNIPHIER_PIN_DRV_4_8, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(93, "XFERST", UNIPHIER_PIN_IECTRL_NONE, + 87, UNIPHIER_PIN_DRV_4_8, + 87, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(94, "P_FE_ON", UNIPHIER_PIN_IECTRL_NONE, + 88, UNIPHIER_PIN_DRV_4_8, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(95, "P_TU0_ON", UNIPHIER_PIN_IECTRL_NONE, + 89, UNIPHIER_PIN_DRV_4_8, + 89, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(96, "XFEIRQ0", UNIPHIER_PIN_IECTRL_NONE, + 90, UNIPHIER_PIN_DRV_4_8, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(97, "XFEIRQ1", UNIPHIER_PIN_IECTRL_NONE, + 91, UNIPHIER_PIN_DRV_4_8, + 91, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(98, "XFEIRQ2", UNIPHIER_PIN_IECTRL_NONE, + 92, UNIPHIER_PIN_DRV_4_8, + 92, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(99, "XFEIRQ3", UNIPHIER_PIN_IECTRL_NONE, + 93, UNIPHIER_PIN_DRV_4_8, + 93, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(100, "XFEIRQ4", UNIPHIER_PIN_IECTRL_NONE, + 94, UNIPHIER_PIN_DRV_4_8, + 94, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(101, "XFEIRQ5", UNIPHIER_PIN_IECTRL_NONE, + 95, UNIPHIER_PIN_DRV_4_8, + 95, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "XFEIRQ6", UNIPHIER_PIN_IECTRL_NONE, + 96, UNIPHIER_PIN_DRV_4_8, + 96, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(103, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE, + 97, UNIPHIER_PIN_DRV_4_8, + 97, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(104, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE, + 98, UNIPHIER_PIN_DRV_4_8, + 98, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(105, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE, + 99, UNIPHIER_PIN_DRV_4_8, + 99, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(106, "SMTD0", UNIPHIER_PIN_IECTRL_NONE, + 100, UNIPHIER_PIN_DRV_4_8, + 100, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(107, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE, + 101, UNIPHIER_PIN_DRV_4_8, + 101, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(108, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE, + 102, UNIPHIER_PIN_DRV_4_8, + 102, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(109, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE, + 103, UNIPHIER_PIN_DRV_4_8, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(110, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE, + 104, UNIPHIER_PIN_DRV_4_8, + 104, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(111, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE, + 105, UNIPHIER_PIN_DRV_4_8, + 105, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(112, "SMTD1", UNIPHIER_PIN_IECTRL_NONE, + 106, UNIPHIER_PIN_DRV_4_8, + 106, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(113, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE, + 107, UNIPHIER_PIN_DRV_4_8, + 107, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(114, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE, + 108, UNIPHIER_PIN_DRV_4_8, + 108, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(115, "XINTM", UNIPHIER_PIN_IECTRL_NONE, + 109, UNIPHIER_PIN_DRV_4_8, + 109, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(116, "SCLKM", UNIPHIER_PIN_IECTRL_NONE, + 110, UNIPHIER_PIN_DRV_4_8, + 110, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(117, "SBMTP", UNIPHIER_PIN_IECTRL_NONE, + 111, UNIPHIER_PIN_DRV_4_8, + 111, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(118, "SBPTM", UNIPHIER_PIN_IECTRL_NONE, + 112, UNIPHIER_PIN_DRV_4_8, + 112, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(119, "XMPREQ", UNIPHIER_PIN_IECTRL_NONE, + 113, UNIPHIER_PIN_DRV_4_8, + 113, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(120, "XINTP", UNIPHIER_PIN_IECTRL_NONE, + 114, UNIPHIER_PIN_DRV_4_8, + 114, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(121, "LPST", UNIPHIER_PIN_IECTRL_NONE, + 115, UNIPHIER_PIN_DRV_4_8, + 115, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "SDBOOT", UNIPHIER_PIN_IECTRL_NONE, + 116, UNIPHIER_PIN_DRV_4_8, + 116, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(123, "BFAIL", UNIPHIER_PIN_IECTRL_NONE, + 117, UNIPHIER_PIN_DRV_4_8, + 117, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "XFWE", UNIPHIER_PIN_IECTRL_NONE, + 118, UNIPHIER_PIN_DRV_4_8, + 118, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(125, "RF_COM_RDY", UNIPHIER_PIN_IECTRL_NONE, + 119, UNIPHIER_PIN_DRV_4_8, + 119, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(126, "XDIAG0", UNIPHIER_PIN_IECTRL_NONE, + 120, UNIPHIER_PIN_DRV_4_8, + 120, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(127, "RXD0", UNIPHIER_PIN_IECTRL_NONE, + 121, UNIPHIER_PIN_DRV_4_8, + 121, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(128, "TXD0", UNIPHIER_PIN_IECTRL_NONE, + 122, UNIPHIER_PIN_DRV_4_8, + 122, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(129, "RXD1", UNIPHIER_PIN_IECTRL_NONE, + 123, UNIPHIER_PIN_DRV_4_8, + 123, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(130, "TXD1", UNIPHIER_PIN_IECTRL_NONE, + 124, UNIPHIER_PIN_DRV_4_8, + 124, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(131, "RXD2", UNIPHIER_PIN_IECTRL_NONE, + 125, UNIPHIER_PIN_DRV_4_8, + 125, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(132, "TXD2", UNIPHIER_PIN_IECTRL_NONE, + 126, UNIPHIER_PIN_DRV_4_8, + 126, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(133, "SS0CS", UNIPHIER_PIN_IECTRL_NONE, + 127, UNIPHIER_PIN_DRV_4_8, + 127, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(134, "SS0CLK", UNIPHIER_PIN_IECTRL_NONE, + 128, UNIPHIER_PIN_DRV_4_8, + 128, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(135, "SS0DO", UNIPHIER_PIN_IECTRL_NONE, + 129, UNIPHIER_PIN_DRV_4_8, + 129, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(136, "SS0DI", UNIPHIER_PIN_IECTRL_NONE, + 130, UNIPHIER_PIN_DRV_4_8, + 130, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(137, "MS0CS0", UNIPHIER_PIN_IECTRL_NONE, + 131, UNIPHIER_PIN_DRV_4_8, + 131, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(138, "MS0CLK", UNIPHIER_PIN_IECTRL_NONE, + 132, UNIPHIER_PIN_DRV_4_8, + 132, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(139, "MS0DI", UNIPHIER_PIN_IECTRL_NONE, + 133, UNIPHIER_PIN_DRV_4_8, + 133, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(140, "MS0DO", UNIPHIER_PIN_IECTRL_NONE, + 134, UNIPHIER_PIN_DRV_4_8, + 134, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(141, "XMDMRST", UNIPHIER_PIN_IECTRL_NONE, + 135, UNIPHIER_PIN_DRV_4_8, + 135, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(142, "SCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(143, "SDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(144, "SCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(145, "SDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(146, "SCL2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(147, "SDA2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(148, "SCL3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(149, "SDA3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(150, "SD0DAT0", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_8_12_16_20, + 136, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(151, "SD0DAT1", UNIPHIER_PIN_IECTRL_NONE, + 13, UNIPHIER_PIN_DRV_8_12_16_20, + 137, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(152, "SD0DAT2", UNIPHIER_PIN_IECTRL_NONE, + 14, UNIPHIER_PIN_DRV_8_12_16_20, + 138, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(153, "SD0DAT3", UNIPHIER_PIN_IECTRL_NONE, + 15, UNIPHIER_PIN_DRV_8_12_16_20, + 139, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(154, "SD0CMD", UNIPHIER_PIN_IECTRL_NONE, + 11, UNIPHIER_PIN_DRV_8_12_16_20, + 141, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(155, "SD0CLK", UNIPHIER_PIN_IECTRL_NONE, + 10, UNIPHIER_PIN_DRV_8_12_16_20, + 140, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(156, "SD0CD", UNIPHIER_PIN_IECTRL_NONE, + 142, UNIPHIER_PIN_DRV_4_8, + 142, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(157, "SD0WP", UNIPHIER_PIN_IECTRL_NONE, + 143, UNIPHIER_PIN_DRV_4_8, + 143, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(158, "SD0VTCG", UNIPHIER_PIN_IECTRL_NONE, + 144, UNIPHIER_PIN_DRV_4_8, + 144, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(159, "CK25O", UNIPHIER_PIN_IECTRL_NONE, + 145, UNIPHIER_PIN_DRV_4_8, + 145, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(160, "RGMII_TXCLK", 6, + 146, UNIPHIER_PIN_DRV_4_8, + 146, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(161, "RGMII_TXD0", 6, + 147, UNIPHIER_PIN_DRV_4_8, + 147, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(162, "RGMII_TXD1", 6, + 148, UNIPHIER_PIN_DRV_4_8, + 148, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(163, "RGMII_TXD2", 6, + 149, UNIPHIER_PIN_DRV_4_8, + 149, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(164, "RGMII_TXD3", 6, + 150, UNIPHIER_PIN_DRV_4_8, + 150, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(165, "RGMII_TXCTL", 6, + 151, UNIPHIER_PIN_DRV_4_8, + 151, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(166, "MII_TXER", UNIPHIER_PIN_IECTRL_NONE, + 152, UNIPHIER_PIN_DRV_4_8, + 152, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(167, "RGMII_RXCLK", 6, + 153, UNIPHIER_PIN_DRV_4_8, + 153, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(168, "RGMII_RXD0", 6, + 154, UNIPHIER_PIN_DRV_4_8, + 154, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(169, "RGMII_RXD1", 6, + 155, UNIPHIER_PIN_DRV_4_8, + 155, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(170, "RGMII_RXD2", 6, + 156, UNIPHIER_PIN_DRV_4_8, + 156, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(171, "RGMII_RXD3", 6, + 157, UNIPHIER_PIN_DRV_4_8, + 157, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(172, "RGMII_RXCTL", 6, + 158, UNIPHIER_PIN_DRV_4_8, + 158, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(173, "MII_RXER", 6, + 159, UNIPHIER_PIN_DRV_4_8, + 159, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(174, "MII_CRS", 6, + 160, UNIPHIER_PIN_DRV_4_8, + 160, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(175, "MII_COL", 6, + 161, UNIPHIER_PIN_DRV_4_8, + 161, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(176, "MDC", 6, + 162, UNIPHIER_PIN_DRV_4_8, + 162, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(177, "MDIO", 6, + 163, UNIPHIER_PIN_DRV_4_8, + 163, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(178, "MDIO_INTL", 6, + 164, UNIPHIER_PIN_DRV_4_8, + 164, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(179, "XETH_RST", 6, + 165, UNIPHIER_PIN_DRV_4_8, + 165, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(180, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE, + 166, UNIPHIER_PIN_DRV_4_8, + 166, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(181, "USB0OD", UNIPHIER_PIN_IECTRL_NONE, + 167, UNIPHIER_PIN_DRV_4_8, + 167, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(182, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE, + 168, UNIPHIER_PIN_DRV_4_8, + 168, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(183, "USB1OD", UNIPHIER_PIN_IECTRL_NONE, + 169, UNIPHIER_PIN_DRV_4_8, + 169, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(184, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE, + 170, UNIPHIER_PIN_DRV_4_8, + 170, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(185, "USB2OD", UNIPHIER_PIN_IECTRL_NONE, + 171, UNIPHIER_PIN_DRV_4_8, + 171, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(186, "USB2ID", UNIPHIER_PIN_IECTRL_NONE, + 172, UNIPHIER_PIN_DRV_4_8, + 172, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(187, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE, + 173, UNIPHIER_PIN_DRV_4_8, + 173, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(188, "USB3OD", UNIPHIER_PIN_IECTRL_NONE, + 174, UNIPHIER_PIN_DRV_4_8, + 174, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(189, "LINKCLK", UNIPHIER_PIN_IECTRL_NONE, + 175, UNIPHIER_PIN_DRV_4_8, + 175, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(190, "LINKREQ", UNIPHIER_PIN_IECTRL_NONE, + 176, UNIPHIER_PIN_DRV_4_8, + 176, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(191, "LINKCTL0", UNIPHIER_PIN_IECTRL_NONE, + 177, UNIPHIER_PIN_DRV_4_8, + 177, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(192, "LINKCTL1", UNIPHIER_PIN_IECTRL_NONE, + 178, UNIPHIER_PIN_DRV_4_8, + 178, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(193, "LINKDT0", UNIPHIER_PIN_IECTRL_NONE, + 179, UNIPHIER_PIN_DRV_4_8, + 179, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(194, "LINKDT1", UNIPHIER_PIN_IECTRL_NONE, + 180, UNIPHIER_PIN_DRV_4_8, + 180, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(195, "LINKDT2", UNIPHIER_PIN_IECTRL_NONE, + 181, UNIPHIER_PIN_DRV_4_8, + 181, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(196, "LINKDT3", UNIPHIER_PIN_IECTRL_NONE, + 182, UNIPHIER_PIN_DRV_4_8, + 182, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(197, "LINKDT4", UNIPHIER_PIN_IECTRL_NONE, + 183, UNIPHIER_PIN_DRV_4_8, + 183, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(198, "LINKDT5", UNIPHIER_PIN_IECTRL_NONE, + 184, UNIPHIER_PIN_DRV_4_8, + 184, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(199, "LINKDT6", UNIPHIER_PIN_IECTRL_NONE, + 185, UNIPHIER_PIN_DRV_4_8, + 185, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(200, "LINKDT7", UNIPHIER_PIN_IECTRL_NONE, + 186, UNIPHIER_PIN_DRV_4_8, + 186, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(201, "CKDVO", UNIPHIER_PIN_IECTRL_NONE, + 187, UNIPHIER_PIN_DRV_4_8, + 187, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(202, "PHY_PD", UNIPHIER_PIN_IECTRL_NONE, + 188, UNIPHIER_PIN_DRV_4_8, + 188, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(203, "X1394_RST", UNIPHIER_PIN_IECTRL_NONE, + 189, UNIPHIER_PIN_DRV_4_8, + 189, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(204, "VOUT_MUTE_L", UNIPHIER_PIN_IECTRL_NONE, + 190, UNIPHIER_PIN_DRV_4_8, + 190, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(205, "CLK54O", UNIPHIER_PIN_IECTRL_NONE, + 191, UNIPHIER_PIN_DRV_4_8, + 191, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(206, "CLK54I", UNIPHIER_PIN_IECTRL_NONE, + 192, UNIPHIER_PIN_DRV_NONE, + 192, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(207, "YIN0", UNIPHIER_PIN_IECTRL_NONE, + 193, UNIPHIER_PIN_DRV_4_8, + 193, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(208, "YIN1", UNIPHIER_PIN_IECTRL_NONE, + 194, UNIPHIER_PIN_DRV_4_8, + 194, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(209, "YIN2", UNIPHIER_PIN_IECTRL_NONE, + 195, UNIPHIER_PIN_DRV_4_8, + 195, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(210, "YIN3", UNIPHIER_PIN_IECTRL_NONE, + 196, UNIPHIER_PIN_DRV_4_8, + 196, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(211, "YIN4", UNIPHIER_PIN_IECTRL_NONE, + 197, UNIPHIER_PIN_DRV_4_8, + 197, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(212, "YIN5", UNIPHIER_PIN_IECTRL_NONE, + 198, UNIPHIER_PIN_DRV_4_8, + 198, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(213, "CIN0", UNIPHIER_PIN_IECTRL_NONE, + 199, UNIPHIER_PIN_DRV_4_8, + 199, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(214, "CIN1", UNIPHIER_PIN_IECTRL_NONE, + 200, UNIPHIER_PIN_DRV_4_8, + 200, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(215, "CIN2", UNIPHIER_PIN_IECTRL_NONE, + 201, UNIPHIER_PIN_DRV_4_8, + 201, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(216, "CIN3", UNIPHIER_PIN_IECTRL_NONE, + 202, UNIPHIER_PIN_DRV_4_8, + 202, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(217, "CIN4", UNIPHIER_PIN_IECTRL_NONE, + 203, UNIPHIER_PIN_DRV_4_8, + 203, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(218, "CIN5", UNIPHIER_PIN_IECTRL_NONE, + 204, UNIPHIER_PIN_DRV_4_8, + 204, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(219, "GCP", UNIPHIER_PIN_IECTRL_NONE, + 205, UNIPHIER_PIN_DRV_4_8, + 205, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(220, "ADFLG", UNIPHIER_PIN_IECTRL_NONE, + 206, UNIPHIER_PIN_DRV_4_8, + 206, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(221, "CK27AIOF", UNIPHIER_PIN_IECTRL_NONE, + 207, UNIPHIER_PIN_DRV_4_8, + 207, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(222, "DACOUT", UNIPHIER_PIN_IECTRL_NONE, + 208, UNIPHIER_PIN_DRV_4_8, + 208, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(223, "DAFLG", UNIPHIER_PIN_IECTRL_NONE, + 209, UNIPHIER_PIN_DRV_4_8, + 209, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(224, "VBIH", UNIPHIER_PIN_IECTRL_NONE, + 210, UNIPHIER_PIN_DRV_4_8, + 210, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(225, "VBIL", UNIPHIER_PIN_IECTRL_NONE, + 211, UNIPHIER_PIN_DRV_4_8, + 211, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(226, "XSUB_RST", UNIPHIER_PIN_IECTRL_NONE, + 212, UNIPHIER_PIN_DRV_4_8, + 212, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(227, "XADC_PD", UNIPHIER_PIN_IECTRL_NONE, + 213, UNIPHIER_PIN_DRV_4_8, + 213, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(228, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE, + 214, UNIPHIER_PIN_DRV_4_8, + 214, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(229, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE, + 215, UNIPHIER_PIN_DRV_4_8, + 215, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(230, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE, + 216, UNIPHIER_PIN_DRV_4_8, + 216, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(231, "AI1DMIX", UNIPHIER_PIN_IECTRL_NONE, + 217, UNIPHIER_PIN_DRV_4_8, + 217, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(232, "CK27HD", UNIPHIER_PIN_IECTRL_NONE, + 218, UNIPHIER_PIN_DRV_4_8, + 218, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(233, "XHD_RST", UNIPHIER_PIN_IECTRL_NONE, + 219, UNIPHIER_PIN_DRV_4_8, + 219, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(234, "INTHD", UNIPHIER_PIN_IECTRL_NONE, + 220, UNIPHIER_PIN_DRV_4_8, + 220, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(235, "VO1HDCK", UNIPHIER_PIN_IECTRL_NONE, + 221, UNIPHIER_PIN_DRV_4_8, + 221, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(236, "VO1HSYNC", UNIPHIER_PIN_IECTRL_NONE, + 222, UNIPHIER_PIN_DRV_4_8, + 222, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(237, "VO1VSYNC", UNIPHIER_PIN_IECTRL_NONE, + 223, UNIPHIER_PIN_DRV_4_8, + 223, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(238, "VO1DE", UNIPHIER_PIN_IECTRL_NONE, + 224, UNIPHIER_PIN_DRV_4_8, + 224, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(239, "VO1Y0", UNIPHIER_PIN_IECTRL_NONE, + 225, UNIPHIER_PIN_DRV_4_8, + 225, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(240, "VO1Y1", UNIPHIER_PIN_IECTRL_NONE, + 226, UNIPHIER_PIN_DRV_4_8, + 226, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(241, "VO1Y2", UNIPHIER_PIN_IECTRL_NONE, + 227, UNIPHIER_PIN_DRV_4_8, + 227, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(242, "VO1Y3", UNIPHIER_PIN_IECTRL_NONE, + 228, UNIPHIER_PIN_DRV_4_8, + 228, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(243, "VO1Y4", UNIPHIER_PIN_IECTRL_NONE, + 229, UNIPHIER_PIN_DRV_4_8, + 229, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(244, "VO1Y5", UNIPHIER_PIN_IECTRL_NONE, + 230, UNIPHIER_PIN_DRV_4_8, + 230, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(245, "VO1Y6", UNIPHIER_PIN_IECTRL_NONE, + 231, UNIPHIER_PIN_DRV_4_8, + 231, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(246, "VO1Y7", UNIPHIER_PIN_IECTRL_NONE, + 232, UNIPHIER_PIN_DRV_4_8, + 232, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(247, "VO1Y8", UNIPHIER_PIN_IECTRL_NONE, + 233, UNIPHIER_PIN_DRV_4_8, + 233, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(248, "VO1Y9", UNIPHIER_PIN_IECTRL_NONE, + 234, UNIPHIER_PIN_DRV_4_8, + 234, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(249, "VO1Y10", UNIPHIER_PIN_IECTRL_NONE, + 235, UNIPHIER_PIN_DRV_4_8, + 235, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(250, "VO1Y11", UNIPHIER_PIN_IECTRL_NONE, + 236, UNIPHIER_PIN_DRV_4_8, + 236, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(251, "VO1CB0", UNIPHIER_PIN_IECTRL_NONE, + 237, UNIPHIER_PIN_DRV_4_8, + 237, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(252, "VO1CB1", UNIPHIER_PIN_IECTRL_NONE, + 238, UNIPHIER_PIN_DRV_4_8, + 238, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(253, "VO1CB2", UNIPHIER_PIN_IECTRL_NONE, + 239, UNIPHIER_PIN_DRV_4_8, + 239, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(254, "VO1CB3", UNIPHIER_PIN_IECTRL_NONE, + 240, UNIPHIER_PIN_DRV_4_8, + 240, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(255, "VO1CB4", UNIPHIER_PIN_IECTRL_NONE, + 241, UNIPHIER_PIN_DRV_4_8, + 241, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(256, "VO1CB5", UNIPHIER_PIN_IECTRL_NONE, + 242, UNIPHIER_PIN_DRV_4_8, + 242, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(257, "VO1CB6", UNIPHIER_PIN_IECTRL_NONE, + 243, UNIPHIER_PIN_DRV_4_8, + 243, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(258, "VO1CB7", UNIPHIER_PIN_IECTRL_NONE, + 244, UNIPHIER_PIN_DRV_4_8, + 244, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(259, "VO1CB8", UNIPHIER_PIN_IECTRL_NONE, + 245, UNIPHIER_PIN_DRV_4_8, + 245, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(260, "VO1CB9", UNIPHIER_PIN_IECTRL_NONE, + 246, UNIPHIER_PIN_DRV_4_8, + 246, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(261, "VO1CB10", UNIPHIER_PIN_IECTRL_NONE, + 247, UNIPHIER_PIN_DRV_4_8, + 247, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(262, "VO1CB11", UNIPHIER_PIN_IECTRL_NONE, + 248, UNIPHIER_PIN_DRV_4_8, + 248, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(263, "VO1CR0", UNIPHIER_PIN_IECTRL_NONE, + 249, UNIPHIER_PIN_DRV_4_8, + 249, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(264, "VO1CR1", UNIPHIER_PIN_IECTRL_NONE, + 250, UNIPHIER_PIN_DRV_4_8, + 250, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(265, "VO1CR2", UNIPHIER_PIN_IECTRL_NONE, + 251, UNIPHIER_PIN_DRV_4_8, + 251, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(266, "VO1CR3", UNIPHIER_PIN_IECTRL_NONE, + 252, UNIPHIER_PIN_DRV_4_8, + 252, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(267, "VO1CR4", UNIPHIER_PIN_IECTRL_NONE, + 253, UNIPHIER_PIN_DRV_4_8, + 253, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(268, "VO1CR5", UNIPHIER_PIN_IECTRL_NONE, + 254, UNIPHIER_PIN_DRV_4_8, + 254, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(269, "VO1CR6", UNIPHIER_PIN_IECTRL_NONE, + 255, UNIPHIER_PIN_DRV_4_8, + 255, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(270, "VO1CR7", UNIPHIER_PIN_IECTRL_NONE, + 256, UNIPHIER_PIN_DRV_4_8, + 256, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(271, "VO1CR8", UNIPHIER_PIN_IECTRL_NONE, + 257, UNIPHIER_PIN_DRV_4_8, + 257, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(272, "VO1CR9", UNIPHIER_PIN_IECTRL_NONE, + 258, UNIPHIER_PIN_DRV_4_8, + 258, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(273, "VO1CR10", UNIPHIER_PIN_IECTRL_NONE, + 259, UNIPHIER_PIN_DRV_4_8, + 259, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(274, "VO1CR11", UNIPHIER_PIN_IECTRL_NONE, + 260, UNIPHIER_PIN_DRV_4_8, + 260, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(275, "VO1EX0", UNIPHIER_PIN_IECTRL_NONE, + 261, UNIPHIER_PIN_DRV_4_8, + 261, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(276, "VO1EX1", UNIPHIER_PIN_IECTRL_NONE, + 262, UNIPHIER_PIN_DRV_4_8, + 262, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(277, "VO1EX2", UNIPHIER_PIN_IECTRL_NONE, + 263, UNIPHIER_PIN_DRV_4_8, + 263, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(278, "VO1EX3", UNIPHIER_PIN_IECTRL_NONE, + 264, UNIPHIER_PIN_DRV_4_8, + 264, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(279, "VEXCKA", UNIPHIER_PIN_IECTRL_NONE, + 265, UNIPHIER_PIN_DRV_4_8, + 265, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(280, "VSEL0", UNIPHIER_PIN_IECTRL_NONE, + 266, UNIPHIER_PIN_DRV_4_8, + 266, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(281, "VSEL1", UNIPHIER_PIN_IECTRL_NONE, + 267, UNIPHIER_PIN_DRV_4_8, + 267, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(282, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE, + 268, UNIPHIER_PIN_DRV_4_8, + 268, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(283, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE, + 269, UNIPHIER_PIN_DRV_4_8, + 269, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(284, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE, + 270, UNIPHIER_PIN_DRV_4_8, + 270, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(285, "AO1D0", UNIPHIER_PIN_IECTRL_NONE, + 271, UNIPHIER_PIN_DRV_4_8, + 271, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(286, "AO1D1", UNIPHIER_PIN_IECTRL_NONE, + 272, UNIPHIER_PIN_DRV_4_8, + 272, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(287, "AO1D2", UNIPHIER_PIN_IECTRL_NONE, + 273, UNIPHIER_PIN_DRV_4_8, + 273, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(288, "AO1D3", UNIPHIER_PIN_IECTRL_NONE, + 274, UNIPHIER_PIN_DRV_4_8, + 274, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(289, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE, + 275, UNIPHIER_PIN_DRV_4_8, + 275, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(290, "XDAC_PD", UNIPHIER_PIN_IECTRL_NONE, + 276, UNIPHIER_PIN_DRV_4_8, + 276, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(291, "EX_A_MUTE", UNIPHIER_PIN_IECTRL_NONE, + 277, UNIPHIER_PIN_DRV_4_8, + 277, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(292, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE, + 278, UNIPHIER_PIN_DRV_4_8, + 278, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(293, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE, + 279, UNIPHIER_PIN_DRV_4_8, + 279, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(294, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE, + 280, UNIPHIER_PIN_DRV_4_8, + 280, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(295, "AO2DMIX", UNIPHIER_PIN_IECTRL_NONE, + 281, UNIPHIER_PIN_DRV_4_8, + 281, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(296, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE, + 282, UNIPHIER_PIN_DRV_4_8, + 282, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(297, "HTHPD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(298, "HTSCL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(299, "HTSDA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(300, "PORT00", UNIPHIER_PIN_IECTRL_NONE, + 284, UNIPHIER_PIN_DRV_4_8, + 284, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(301, "PORT01", UNIPHIER_PIN_IECTRL_NONE, + 285, UNIPHIER_PIN_DRV_4_8, + 285, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(302, "PORT02", UNIPHIER_PIN_IECTRL_NONE, + 286, UNIPHIER_PIN_DRV_4_8, + 286, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(303, "PORT03", UNIPHIER_PIN_IECTRL_NONE, + 287, UNIPHIER_PIN_DRV_4_8, + 287, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(304, "PORT04", UNIPHIER_PIN_IECTRL_NONE, + 288, UNIPHIER_PIN_DRV_4_8, + 288, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(305, "PORT05", UNIPHIER_PIN_IECTRL_NONE, + 289, UNIPHIER_PIN_DRV_4_8, + 289, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(306, "PORT06", UNIPHIER_PIN_IECTRL_NONE, + 290, UNIPHIER_PIN_DRV_4_8, + 290, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(307, "PORT07", UNIPHIER_PIN_IECTRL_NONE, + 291, UNIPHIER_PIN_DRV_4_8, + 291, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(308, "PORT10", UNIPHIER_PIN_IECTRL_NONE, + 292, UNIPHIER_PIN_DRV_4_8, + 292, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(309, "PORT11", UNIPHIER_PIN_IECTRL_NONE, + 293, UNIPHIER_PIN_DRV_4_8, + 293, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(310, "PORT12", UNIPHIER_PIN_IECTRL_NONE, + 294, UNIPHIER_PIN_DRV_4_8, + 294, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(311, "PORT13", UNIPHIER_PIN_IECTRL_NONE, + 295, UNIPHIER_PIN_DRV_4_8, + 295, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(312, "PORT14", UNIPHIER_PIN_IECTRL_NONE, + 296, UNIPHIER_PIN_DRV_4_8, + 296, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(313, "PORT15", UNIPHIER_PIN_IECTRL_NONE, + 297, UNIPHIER_PIN_DRV_4_8, + 297, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(314, "PORT16", UNIPHIER_PIN_IECTRL_NONE, + 298, UNIPHIER_PIN_DRV_4_8, + 298, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(315, "PORT17", UNIPHIER_PIN_IECTRL_NONE, + 299, UNIPHIER_PIN_DRV_4_8, + 299, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(316, "PORT20", UNIPHIER_PIN_IECTRL_NONE, + 300, UNIPHIER_PIN_DRV_4_8, + 300, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(317, "PORT21", UNIPHIER_PIN_IECTRL_NONE, + 301, UNIPHIER_PIN_DRV_4_8, + 301, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(318, "PORT22", UNIPHIER_PIN_IECTRL_NONE, + 302, UNIPHIER_PIN_DRV_4_8, + 302, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(319, "SD1DAT0", UNIPHIER_PIN_IECTRL_NONE, + 303, UNIPHIER_PIN_DRV_4_8, + 303, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(320, "SD1DAT1", UNIPHIER_PIN_IECTRL_NONE, + 304, UNIPHIER_PIN_DRV_4_8, + 304, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(321, "SD1DAT2", UNIPHIER_PIN_IECTRL_NONE, + 305, UNIPHIER_PIN_DRV_4_8, + 305, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(322, "SD1DAT3", UNIPHIER_PIN_IECTRL_NONE, + 306, UNIPHIER_PIN_DRV_4_8, + 306, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(323, "SD1CMD", UNIPHIER_PIN_IECTRL_NONE, + 307, UNIPHIER_PIN_DRV_4_8, + 307, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(324, "SD1CLK", UNIPHIER_PIN_IECTRL_NONE, + 308, UNIPHIER_PIN_DRV_4_8, + 308, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(325, "SD1CD", UNIPHIER_PIN_IECTRL_NONE, + 309, UNIPHIER_PIN_DRV_4_8, + 309, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(326, "SD1WP", UNIPHIER_PIN_IECTRL_NONE, + 310, UNIPHIER_PIN_DRV_4_8, + 310, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(327, "SD1VTCG", UNIPHIER_PIN_IECTRL_NONE, + 311, UNIPHIER_PIN_DRV_4_8, + 311, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(328, "DMDISO", UNIPHIER_PIN_IECTRL_NONE, + 312, UNIPHIER_PIN_DRV_NONE, + 312, UNIPHIER_PIN_PULL_DOWN), +}; + +static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {142, 143}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {144, 145}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {146, 147}; +static const unsigned i2c2_muxvals[] = {0, 0}; +static const unsigned i2c3_pins[] = {148, 149}; +static const unsigned i2c3_muxvals[] = {0, 0}; +static const unsigned i2c6_pins[] = {308, 309}; +static const unsigned i2c6_muxvals[] = {6, 6}; +static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49, + 50, 51, 52, 53, 54}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {131, 132}; +static const unsigned nand_cs1_muxvals[] = {1, 1}; +static const unsigned uart0_pins[] = {127, 128}; +static const unsigned uart0_muxvals[] = {0, 0}; +static const unsigned uart1_pins[] = {129, 130}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {131, 132}; +static const unsigned uart2_muxvals[] = {0, 0}; +static const unsigned uart3_pins[] = {88, 89}; +static const unsigned uart3_muxvals[] = {2, 2}; +static const unsigned usb0_pins[] = {180, 181}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {182, 183}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {184, 185}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned usb3_pins[] = {186, 187}; +static const unsigned usb3_muxvals[] = {0, 0}; +static const unsigned port_range0_pins[] = { + 300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */ + 308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */ + 316, 317, 318, 16, 17, 18, 19, 20, /* PORT2x */ + 21, 22, 23, 4, 93, 94, 95, 63, /* PORT3x */ + 123, 122, 124, 125, 126, 141, 202, 203, /* PORT4x */ + 204, 226, 227, 290, 291, 233, 280, 281, /* PORT5x */ + 8, 7, 10, 29, 30, 48, 49, 50, /* PORT6x */ + 40, 41, 42, 43, 44, 45, 46, 47, /* PORT7x */ + 54, 51, 52, 53, 127, 128, 129, 130, /* PORT8x */ + 131, 132, 57, 60, 134, 133, 135, 136, /* PORT9x */ + 138, 137, 140, 139, 64, 65, 66, 67, /* PORT10x */ + 107, 106, 105, 104, 113, 112, 111, 110, /* PORT11x */ + 68, 69, 70, 71, 72, 73, 74, 75, /* PORT12x */ + 76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */ + 84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */ +}; +static const unsigned port_range0_muxvals[] = { + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT0x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT1x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT2x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT3x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT4x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT5x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT6x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT7x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT8x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT9x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT10x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT11x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT12x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT13x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT14x */ +}; +static const unsigned port_range1_pins[] = { + 13, 14, 15, /* PORT175-177 */ + 157, 158, 156, 154, 150, 151, 152, 153, /* PORT18x */ + 326, 327, 325, 323, 319, 320, 321, 322, /* PORT19x */ + 160, 161, 162, 163, 164, 165, 166, 167, /* PORT20x */ + 168, 169, 170, 171, 172, 173, 174, 175, /* PORT21x */ + 180, 181, 182, 183, 184, 185, 187, 188, /* PORT22x */ + 193, 194, 195, 196, 197, 198, 199, 200, /* PORT23x */ + 191, 192, 215, 216, 217, 218, 219, 220, /* PORT24x */ + 222, 223, 224, 225, 228, 229, 230, 231, /* PORT25x */ + 282, 283, 284, 285, 286, 287, 288, 289, /* PORT26x */ + 292, 293, 294, 295, 296, 236, 237, 238, /* PORT27x */ + 275, 276, 277, 278, 239, 240, 249, 250, /* PORT28x */ + 251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */ + 31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */ +}; +static const unsigned port_range1_muxvals[] = { + 7, 7, 7, /* PORT175-177 */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT18x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT19x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT20x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT21x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT22x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT23x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT24x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT25x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT26x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT27x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT28x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT29x */ + 7, 7, 7, 7, 7, 7, 7, 7, /* PORT30x */ +}; +static const unsigned xirq_pins[] = { + 11, 9, 12, 96, 97, 98, 108, 114, /* XIRQ0-7 */ + 234, 186, 99, 100, 101, 102, 184, 301, /* XIRQ8-15 */ + 302, 303, 304, 305, 306, /* XIRQ16-20 */ +}; +static const unsigned xirq_muxvals[] = { + 7, 7, 7, 7, 7, 7, 7, 7, /* XIRQ0-7 */ + 7, 7, 7, 7, 7, 7, 2, 2, /* XIRQ8-15 */ + 2, 2, 2, 2, 2, /* XIRQ16-20 */ +}; +static const unsigned xirq_alternatives_pins[] = { + 184, 310, 316, +}; +static const unsigned xirq_alternatives_muxvals[] = { + 2, 2, 2, +}; + +static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119), + UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 2), +}; + +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const i2c6_groups[] = {"i2c6"}; +static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const uart0_groups[] = {"uart0"}; +static const char * const uart1_groups[] = {"uart1"}; +static const char * const uart2_groups[] = {"uart2"}; +static const char * const uart3_groups[] = {"uart3"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2"}; +static const char * const usb3_groups[] = {"usb3"}; +static const char * const port_groups[] = { + "port00", "port01", "port02", "port03", + "port04", "port05", "port06", "port07", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port20", "port21", "port22", "port23", + "port24", "port25", "port26", "port27", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port40", "port41", "port42", "port43", + "port44", "port45", "port46", "port47", + "port50", "port51", "port52", "port53", + "port54", "port55", "port56", "port57", + "port60", "port61", "port62", "port63", + "port64", "port65", "port66", "port67", + "port70", "port71", "port72", "port73", + "port74", "port75", "port76", "port77", + "port80", "port81", "port82", "port83", + "port84", "port85", "port86", "port87", + "port90", "port91", "port92", "port93", + "port94", "port95", "port96", "port97", + "port100", "port101", "port102", "port103", + "port104", "port105", "port106", "port107", + "port110", "port111", "port112", "port113", + "port114", "port115", "port116", "port117", + "port120", "port121", "port122", "port123", + "port124", "port125", "port126", "port127", + "port130", "port131", "port132", "port133", + "port134", "port135", "port136", "port137", + "port140", "port141", "port142", "port143", + "port144", "port145", "port146", "port147", + /* port150-174 missing */ + /* none */ "port175", "port176", "port177", + "port180", "port181", "port182", "port183", + "port184", "port185", "port186", "port187", + "port190", "port191", "port192", "port193", + "port194", "port195", "port196", "port197", + "port200", "port201", "port202", "port203", + "port204", "port205", "port206", "port207", + "port210", "port211", "port212", "port213", + "port214", "port215", "port216", "port217", + "port220", "port221", "port222", "port223", + "port224", "port225", "port226", "port227", + "port230", "port231", "port232", "port233", + "port234", "port235", "port236", "port237", + "port240", "port241", "port242", "port243", + "port244", "port245", "port246", "port247", + "port250", "port251", "port252", "port253", + "port254", "port255", "port256", "port257", + "port260", "port261", "port262", "port263", + "port264", "port265", "port266", "port267", + "port270", "port271", "port272", "port273", + "port274", "port275", "port276", "port277", + "port280", "port281", "port282", "port283", + "port284", "port285", "port286", "port287", + "port290", "port291", "port292", "port293", + "port294", "port295", "port296", "port297", + "port300", "port301", "port302", "port303", + "port304", "port305", "port306", "port307", +}; +static const char * const xirq_groups[] = { + "xirq0", "xirq1", "xirq2", "xirq3", + "xirq4", "xirq5", "xirq6", "xirq7", + "xirq8", "xirq9", "xirq10", "xirq11", + "xirq12", "xirq13", "xirq14", "xirq15", + "xirq16", "xirq17", "xirq18", "xirq19", + "xirq20", + "xirq14b", "xirq17b", "xirq18b", +}; + +static const struct uniphier_pinmux_function ph1_pro4_functions[] = { + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(i2c6), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(usb3), + UNIPHIER_PINMUX_FUNCTION(port), + UNIPHIER_PINMUX_FUNCTION(xirq), +}; + +static struct uniphier_pinctrl_socdata ph1_pro4_pindata = { + .groups = ph1_pro4_groups, + .groups_count = ARRAY_SIZE(ph1_pro4_groups), + .functions = ph1_pro4_functions, + .functions_count = ARRAY_SIZE(ph1_pro4_functions), + .mux_bits = 4, + .reg_stride = 8, + .load_pinctrl = true, +}; + +static struct pinctrl_desc ph1_pro4_pinctrl_desc = { + .name = DRIVER_NAME, + .pins = ph1_pro4_pins, + .npins = ARRAY_SIZE(ph1_pro4_pins), + .owner = THIS_MODULE, +}; + +static int ph1_pro4_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &ph1_pro4_pinctrl_desc, + &ph1_pro4_pindata); +} + +static const struct of_device_id ph1_pro4_pinctrl_match[] = { + { .compatible = "socionext,ph1-pro4-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ph1_pro4_pinctrl_match); + +static struct platform_driver ph1_pro4_pinctrl_driver = { + .probe = ph1_pro4_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = ph1_pro4_pinctrl_match, + }, +}; +module_platform_driver(ph1_pro4_pinctrl_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier PH1-Pro4 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 95372f9dc892a79bce1e81b8862bb4ad15cf4f76 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:04 +0900 Subject: pinctrl: UniPhier: add UniPhier PH1-sLD8 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/uniphier/Kconfig | 4 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c | 794 ++++++++++++++++++++++++++++ 3 files changed, 799 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 944803ffb5cc..f4a21feeff61 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -13,4 +13,8 @@ config PINCTRL_UNIPHIER_PH1_PRO4 tristate "UniPhier PH1-Pro4 SoC pinctrl driver" select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_SLD8 + tristate "UniPhier PH1-sLD8 SoC pinctrl driver" + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b1b597e0dccb..3349fff80aa9 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c new file mode 100644 index 000000000000..7e9dae54fcb2 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c @@ -0,0 +1,794 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +#define DRIVER_NAME "ph1-sld8-pinctrl" + +static const struct pinctrl_pin_desc ph1_sld8_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "PCA00", UNIPHIER_PIN_IECTRL_NONE, + 15, UNIPHIER_PIN_DRV_4_8, + 15, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "PCA01", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_4_8, + 16, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "PCA02", UNIPHIER_PIN_IECTRL_NONE, + 17, UNIPHIER_PIN_DRV_4_8, + 17, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "PCA03", UNIPHIER_PIN_IECTRL_NONE, + 18, UNIPHIER_PIN_DRV_4_8, + 18, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "PCA04", UNIPHIER_PIN_IECTRL_NONE, + 19, UNIPHIER_PIN_DRV_4_8, + 19, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(5, "PCA05", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_4_8, + 20, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "PCA06", UNIPHIER_PIN_IECTRL_NONE, + 21, UNIPHIER_PIN_DRV_4_8, + 21, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "PCA07", UNIPHIER_PIN_IECTRL_NONE, + 22, UNIPHIER_PIN_DRV_4_8, + 22, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "PCA08", UNIPHIER_PIN_IECTRL_NONE, + 23, UNIPHIER_PIN_DRV_4_8, + 23, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "PCA09", UNIPHIER_PIN_IECTRL_NONE, + 24, UNIPHIER_PIN_DRV_4_8, + 24, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "PCA10", UNIPHIER_PIN_IECTRL_NONE, + 25, UNIPHIER_PIN_DRV_4_8, + 25, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "PCA11", UNIPHIER_PIN_IECTRL_NONE, + 26, UNIPHIER_PIN_DRV_4_8, + 26, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(12, "PCA12", UNIPHIER_PIN_IECTRL_NONE, + 27, UNIPHIER_PIN_DRV_4_8, + 27, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(13, "PCA13", UNIPHIER_PIN_IECTRL_NONE, + 28, UNIPHIER_PIN_DRV_4_8, + 28, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(14, "PCA14", UNIPHIER_PIN_IECTRL_NONE, + 29, UNIPHIER_PIN_DRV_4_8, + 29, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(15, "XNFRE_GB", UNIPHIER_PIN_IECTRL_NONE, + 30, UNIPHIER_PIN_DRV_4_8, + 30, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(16, "XNFWE_GB", UNIPHIER_PIN_IECTRL_NONE, + 31, UNIPHIER_PIN_DRV_4_8, + 31, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(17, "NFALE_GB", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_4_8, + 32, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(18, "NFCLE_GB", UNIPHIER_PIN_IECTRL_NONE, + 33, UNIPHIER_PIN_DRV_4_8, + 33, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(19, "XNFWP_GB", UNIPHIER_PIN_IECTRL_NONE, + 34, UNIPHIER_PIN_DRV_4_8, + 34, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(20, "XNFCE0_GB", UNIPHIER_PIN_IECTRL_NONE, + 35, UNIPHIER_PIN_DRV_4_8, + 35, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(21, "NANDRYBY0_GB", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_4_8, + 36, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(22, "XNFCE1_GB", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_8_12_16_20, + 119, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(23, "NANDRYBY1_GB", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_8_12_16_20, + 120, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(24, "NFD0_GB", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_8_12_16_20, + 121, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(25, "NFD1_GB", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_8_12_16_20, + 122, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(26, "NFD2_GB", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_8_12_16_20, + 123, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(27, "NFD3_GB", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_8_12_16_20, + 124, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(28, "NFD4_GB", UNIPHIER_PIN_IECTRL_NONE, + 24, UNIPHIER_PIN_DRV_8_12_16_20, + 125, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(29, "NFD5_GB", UNIPHIER_PIN_IECTRL_NONE, + 28, UNIPHIER_PIN_DRV_8_12_16_20, + 126, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(30, "NFD6_GB", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_8_12_16_20, + 127, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(31, "NFD7_GB", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_8_12_16_20, + 128, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(32, "SDCLK", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(33, "SDCMD", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(34, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE, + 48, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(35, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(36, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE, + 56, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(37, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE, + 60, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(38, "SDCD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 129, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(39, "SDWP", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 130, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(40, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 131, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(41, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE, + 37, UNIPHIER_PIN_DRV_4_8, + 37, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(42, "USB0OD", UNIPHIER_PIN_IECTRL_NONE, + 38, UNIPHIER_PIN_DRV_4_8, + 38, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(43, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE, + 39, UNIPHIER_PIN_DRV_4_8, + 39, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(44, "USB1OD", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_4_8, + 40, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(45, "PCRESET", UNIPHIER_PIN_IECTRL_NONE, + 41, UNIPHIER_PIN_DRV_4_8, + 41, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(46, "PCREG", UNIPHIER_PIN_IECTRL_NONE, + 42, UNIPHIER_PIN_DRV_4_8, + 42, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(47, "PCCE2", UNIPHIER_PIN_IECTRL_NONE, + 43, UNIPHIER_PIN_DRV_4_8, + 43, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(48, "PCVS1", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_4_8, + 44, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(49, "PCCD2", UNIPHIER_PIN_IECTRL_NONE, + 45, UNIPHIER_PIN_DRV_4_8, + 45, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(50, "PCCD1", UNIPHIER_PIN_IECTRL_NONE, + 46, UNIPHIER_PIN_DRV_4_8, + 46, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(51, "PCREADY", UNIPHIER_PIN_IECTRL_NONE, + 47, UNIPHIER_PIN_DRV_4_8, + 47, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(52, "PCDOE", UNIPHIER_PIN_IECTRL_NONE, + 48, UNIPHIER_PIN_DRV_4_8, + 48, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(53, "PCCE1", UNIPHIER_PIN_IECTRL_NONE, + 49, UNIPHIER_PIN_DRV_4_8, + 49, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(54, "PCWE", UNIPHIER_PIN_IECTRL_NONE, + 50, UNIPHIER_PIN_DRV_4_8, + 50, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(55, "PCOE", UNIPHIER_PIN_IECTRL_NONE, + 51, UNIPHIER_PIN_DRV_4_8, + 51, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(56, "PCWAIT", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_4_8, + 52, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(57, "PCIOWR", UNIPHIER_PIN_IECTRL_NONE, + 53, UNIPHIER_PIN_DRV_4_8, + 53, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(58, "PCIORD", UNIPHIER_PIN_IECTRL_NONE, + 54, UNIPHIER_PIN_DRV_4_8, + 54, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(59, "HS0DIN0", UNIPHIER_PIN_IECTRL_NONE, + 55, UNIPHIER_PIN_DRV_4_8, + 55, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(60, "HS0DIN1", UNIPHIER_PIN_IECTRL_NONE, + 56, UNIPHIER_PIN_DRV_4_8, + 56, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(61, "HS0DIN2", UNIPHIER_PIN_IECTRL_NONE, + 57, UNIPHIER_PIN_DRV_4_8, + 57, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(62, "HS0DIN3", UNIPHIER_PIN_IECTRL_NONE, + 58, UNIPHIER_PIN_DRV_4_8, + 58, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(63, "HS0DIN4", UNIPHIER_PIN_IECTRL_NONE, + 59, UNIPHIER_PIN_DRV_4_8, + 59, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(64, "HS0DIN5", UNIPHIER_PIN_IECTRL_NONE, + 60, UNIPHIER_PIN_DRV_4_8, + 60, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "HS0DIN6", UNIPHIER_PIN_IECTRL_NONE, + 61, UNIPHIER_PIN_DRV_4_8, + 61, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "HS0DIN7", UNIPHIER_PIN_IECTRL_NONE, + 62, UNIPHIER_PIN_DRV_4_8, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "HS0BCLKIN", UNIPHIER_PIN_IECTRL_NONE, + 63, UNIPHIER_PIN_DRV_4_8, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "HS0VALIN", UNIPHIER_PIN_IECTRL_NONE, + 64, UNIPHIER_PIN_DRV_4_8, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(69, "HS0SYNCIN", UNIPHIER_PIN_IECTRL_NONE, + 65, UNIPHIER_PIN_DRV_4_8, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(70, "HSDOUT0", UNIPHIER_PIN_IECTRL_NONE, + 66, UNIPHIER_PIN_DRV_4_8, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(71, "HSDOUT1", UNIPHIER_PIN_IECTRL_NONE, + 67, UNIPHIER_PIN_DRV_4_8, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(72, "HSDOUT2", UNIPHIER_PIN_IECTRL_NONE, + 68, UNIPHIER_PIN_DRV_4_8, + 68, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(73, "HSDOUT3", UNIPHIER_PIN_IECTRL_NONE, + 69, UNIPHIER_PIN_DRV_4_8, + 69, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(74, "HSDOUT4", UNIPHIER_PIN_IECTRL_NONE, + 70, UNIPHIER_PIN_DRV_4_8, + 70, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(75, "HSDOUT5", UNIPHIER_PIN_IECTRL_NONE, + 71, UNIPHIER_PIN_DRV_4_8, + 71, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(76, "HSDOUT6", UNIPHIER_PIN_IECTRL_NONE, + 72, UNIPHIER_PIN_DRV_4_8, + 72, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(77, "HSDOUT7", UNIPHIER_PIN_IECTRL_NONE, + 73, UNIPHIER_PIN_DRV_4_8, + 73, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(78, "HSBCLKOUT", UNIPHIER_PIN_IECTRL_NONE, + 74, UNIPHIER_PIN_DRV_4_8, + 74, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "HSVALOUT", UNIPHIER_PIN_IECTRL_NONE, + 75, UNIPHIER_PIN_DRV_4_8, + 75, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "HSSYNCOUT", UNIPHIER_PIN_IECTRL_NONE, + 76, UNIPHIER_PIN_DRV_4_8, + 76, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE, + 77, UNIPHIER_PIN_DRV_4_8, + 77, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE, + 78, UNIPHIER_PIN_DRV_4_8, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE, + 79, UNIPHIER_PIN_DRV_4_8, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE, + 80, UNIPHIER_PIN_DRV_4_8, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE, + 81, UNIPHIER_PIN_DRV_4_8, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(86, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE, + 82, UNIPHIER_PIN_DRV_4_8, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE, + 83, UNIPHIER_PIN_DRV_4_8, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(88, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE, + 84, UNIPHIER_PIN_DRV_4_8, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE, + 85, UNIPHIER_PIN_DRV_4_8, + 85, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(90, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE, + 86, UNIPHIER_PIN_DRV_4_8, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE, + 87, UNIPHIER_PIN_DRV_4_8, + 87, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(92, "AGCI", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 132, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(93, "AGCR", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 133, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(94, "AGCBS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 134, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(95, "IECOUT", UNIPHIER_PIN_IECTRL_NONE, + 88, UNIPHIER_PIN_DRV_4_8, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(96, "ASMCK", UNIPHIER_PIN_IECTRL_NONE, + 89, UNIPHIER_PIN_DRV_4_8, + 89, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(97, "ABCKO", UNIPHIER_PIN_IECTRL_NONE, + 90, UNIPHIER_PIN_DRV_4_8, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(98, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE, + 91, UNIPHIER_PIN_DRV_4_8, + 91, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(99, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE, + 92, UNIPHIER_PIN_DRV_4_8, + 92, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(100, "ASDOUT1", UNIPHIER_PIN_IECTRL_NONE, + 93, UNIPHIER_PIN_DRV_4_8, + 93, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(101, "ARCOUT", UNIPHIER_PIN_IECTRL_NONE, + 94, UNIPHIER_PIN_DRV_4_8, + 94, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE, + 95, UNIPHIER_PIN_DRV_4_8, + 95, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE, + 96, UNIPHIER_PIN_DRV_4_8, + 96, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(112, "SBO1", UNIPHIER_PIN_IECTRL_NONE, + 97, UNIPHIER_PIN_DRV_4_8, + 97, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(113, "SBI1", UNIPHIER_PIN_IECTRL_NONE, + 98, UNIPHIER_PIN_DRV_4_8, + 98, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(114, "TXD1", UNIPHIER_PIN_IECTRL_NONE, + 99, UNIPHIER_PIN_DRV_4_8, + 99, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(115, "RXD1", UNIPHIER_PIN_IECTRL_NONE, + 100, UNIPHIER_PIN_DRV_4_8, + 100, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(116, "HIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(117, "VIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_5, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(118, "TCON0", UNIPHIER_PIN_IECTRL_NONE, + 101, UNIPHIER_PIN_DRV_4_8, + 101, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(119, "TCON1", UNIPHIER_PIN_IECTRL_NONE, + 102, UNIPHIER_PIN_DRV_4_8, + 102, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(120, "TCON2", UNIPHIER_PIN_IECTRL_NONE, + 103, UNIPHIER_PIN_DRV_4_8, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(121, "TCON3", UNIPHIER_PIN_IECTRL_NONE, + 104, UNIPHIER_PIN_DRV_4_8, + 104, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "TCON4", UNIPHIER_PIN_IECTRL_NONE, + 105, UNIPHIER_PIN_DRV_4_8, + 105, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(123, "TCON5", UNIPHIER_PIN_IECTRL_NONE, + 106, UNIPHIER_PIN_DRV_4_8, + 106, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "TCON6", UNIPHIER_PIN_IECTRL_NONE, + 107, UNIPHIER_PIN_DRV_4_8, + 107, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(125, "TCON7", UNIPHIER_PIN_IECTRL_NONE, + 108, UNIPHIER_PIN_DRV_4_8, + 108, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(126, "TCON8", UNIPHIER_PIN_IECTRL_NONE, + 109, UNIPHIER_PIN_DRV_4_8, + 109, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(127, "PWMA", UNIPHIER_PIN_IECTRL_NONE, + 110, UNIPHIER_PIN_DRV_4_8, + 110, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(128, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE, + 111, UNIPHIER_PIN_DRV_4_8, + 111, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(129, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE, + 112, UNIPHIER_PIN_DRV_4_8, + 112, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(130, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE, + 113, UNIPHIER_PIN_DRV_4_8, + 113, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(131, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE, + 114, UNIPHIER_PIN_DRV_4_8, + 114, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(132, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE, + 115, UNIPHIER_PIN_DRV_4_8, + 115, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(133, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE, + 116, UNIPHIER_PIN_DRV_4_8, + 116, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(134, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE, + 117, UNIPHIER_PIN_DRV_4_8, + 117, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(135, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE, + 118, UNIPHIER_PIN_DRV_4_8, + 118, UNIPHIER_PIN_PULL_DOWN), +}; + +static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {102, 103}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {104, 105}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {108, 109}; +static const unsigned i2c2_muxvals[] = {2, 2}; +static const unsigned i2c3_pins[] = {108, 109}; +static const unsigned i2c3_muxvals[] = {3, 3}; +static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26, + 27, 28, 29, 30, 31}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {22, 23}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned uart0_pins[] = {70, 71}; +static const unsigned uart0_muxvals[] = {3, 3}; +static const unsigned uart1_pins[] = {114, 115}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {112, 113}; +static const unsigned uart2_muxvals[] = {1, 1}; +static const unsigned uart3_pins[] = {110, 111}; +static const unsigned uart3_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {41, 42}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {43, 44}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {114, 115}; +static const unsigned usb2_muxvals[] = {1, 1}; +static const unsigned port_range0_pins[] = { + 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */ + 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */ + 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */ + 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */ + 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */ + 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */ + 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */ + 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */ + 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */ + 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */ + 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */ + 47, 127, 20, 56, 22, /* PORT120-124 */ +}; +static const unsigned port_range0_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */ + 15, 15, 15, 15, 15, /* PORT120-124 */ +}; +static const unsigned port_range1_pins[] = { + 116, 117, /* PORT130-131 */ +}; +static const unsigned port_range1_muxvals[] = { + 15, 15, /* PORT130-131 */ +}; +static const unsigned port_range2_pins[] = { + 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */ +}; +static const unsigned port_range2_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ +}; +static const unsigned port_range3_pins[] = { + 23, /* PORT166 */ +}; +static const unsigned port_range3_muxvals[] = { + 15, /* PORT166 */ +}; +static const unsigned xirq_range0_pins[] = { + 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */ + 82, 87, 88, 50, 51, /* XIRQ8-12 */ +}; +static const unsigned xirq_range0_muxvals[] = { + 0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */ + 14, 14, 14, 14, 14, /* XIRQ8-12 */ +}; +static const unsigned xirq_range1_pins[] = { + 52, 58, /* XIRQ14-15 */ +}; +static const unsigned xirq_range1_muxvals[] = { + 14, 14, /* XIRQ14-15 */ +}; + +static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range2, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range2, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range2, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range2, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range2, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range2, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range2, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range2, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range3, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1), +}; + +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const uart0_groups[] = {"uart0"}; +static const char * const uart1_groups[] = {"uart1"}; +static const char * const uart2_groups[] = {"uart2"}; +static const char * const uart3_groups[] = {"uart3"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2"}; +static const char * const port_groups[] = { + "port00", "port01", "port02", "port03", + "port04", "port05", "port06", "port07", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port20", "port21", "port22", "port23", + "port24", "port25", "port26", "port27", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port40", "port41", "port42", "port43", + "port44", "port45", "port46", "port47", + "port50", "port51", "port52", "port53", + "port54", "port55", "port56", "port57", + "port60", "port61", "port62", "port63", + "port64", "port65", "port66", "port67", + "port70", "port71", "port72", "port73", + "port74", "port75", "port76", "port77", + "port80", "port81", "port82", "port83", + "port84", "port85", "port86", "port87", + "port90", "port91", "port92", "port93", + "port94", "port95", "port96", "port97", + "port100", "port101", "port102", "port103", + "port104", "port105", "port106", "port107", + "port110", "port111", "port112", "port113", + "port114", "port115", "port116", "port117", + "port120", "port121", "port122", "port123", + "port124", "port125", "port126", "port127", + "port130", "port131", "port132", "port133", + "port134", "port135", "port136", "port137", + "port140", "port141", "port142", "port143", + "port144", "port145", "port146", "port147", + /* port150-164 missing */ + /* none */ "port165", +}; +static const char * const xirq_groups[] = { + "xirq0", "xirq1", "xirq2", "xirq3", + "xirq4", "xirq5", "xirq6", "xirq7", + "xirq8", "xirq9", "xirq10", "xirq11", + "xirq12", /* none*/ "xirq14", "xirq15", +}; + +static const struct uniphier_pinmux_function ph1_sld8_functions[] = { + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(port), + UNIPHIER_PINMUX_FUNCTION(xirq), +}; + +static struct uniphier_pinctrl_socdata ph1_sld8_pindata = { + .groups = ph1_sld8_groups, + .groups_count = ARRAY_SIZE(ph1_sld8_groups), + .functions = ph1_sld8_functions, + .functions_count = ARRAY_SIZE(ph1_sld8_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static struct pinctrl_desc ph1_sld8_pinctrl_desc = { + .name = DRIVER_NAME, + .pins = ph1_sld8_pins, + .npins = ARRAY_SIZE(ph1_sld8_pins), + .owner = THIS_MODULE, +}; + +static int ph1_sld8_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &ph1_sld8_pinctrl_desc, + &ph1_sld8_pindata); +} + +static const struct of_device_id ph1_sld8_pinctrl_match[] = { + { .compatible = "socionext,ph1-sld8-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ph1_sld8_pinctrl_match); + +static struct platform_driver ph1_sld8_pinctrl_driver = { + .probe = ph1_sld8_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = ph1_sld8_pinctrl_match, + }, +}; +module_platform_driver(ph1_sld8_pinctrl_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier PH1-sLD8 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 1950b0488780d0d93481e17c56bc7a97a6037459 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:05 +0900 Subject: pinctrl: UniPhier: add UniPhier PH1-Pro5 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/uniphier/Kconfig | 4 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c | 1346 +++++++++++++++++++++++++++ 3 files changed, 1351 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index f4a21feeff61..89bda60066bd 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -17,4 +17,8 @@ config PINCTRL_UNIPHIER_PH1_SLD8 tristate "UniPhier PH1-sLD8 SoC pinctrl driver" select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_PRO5 + tristate "UniPhier PH1-Pro5 SoC pinctrl driver" + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 3349fff80aa9..b0cd3e86bc94 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c new file mode 100644 index 000000000000..b35cf4a24bb7 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c @@ -0,0 +1,1346 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program5 is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +#define DRIVER_NAME "ph1-pro5-pinctrl" + +static const struct pinctrl_pin_desc ph1_pro5_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "AEXCKA1", 0, + 0, UNIPHIER_PIN_DRV_4_8, + 0, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "AEXCKA2", 0, + 1, UNIPHIER_PIN_DRV_4_8, + 1, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "CK27EXI", 0, + 2, UNIPHIER_PIN_DRV_4_8, + 2, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "CK54EXI", 0, + 3, UNIPHIER_PIN_DRV_4_8, + 3, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "ED0", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_4_8, + 4, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(5, "ED1", UNIPHIER_PIN_IECTRL_NONE, + 5, UNIPHIER_PIN_DRV_4_8, + 5, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "ED2", UNIPHIER_PIN_IECTRL_NONE, + 6, UNIPHIER_PIN_DRV_4_8, + 6, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "ED3", UNIPHIER_PIN_IECTRL_NONE, + 7, UNIPHIER_PIN_DRV_4_8, + 7, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "ED4", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_4_8, + 8, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "ED5", UNIPHIER_PIN_IECTRL_NONE, + 9, UNIPHIER_PIN_DRV_4_8, + 9, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "ED6", UNIPHIER_PIN_IECTRL_NONE, + 10, UNIPHIER_PIN_DRV_4_8, + 10, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "ED7", UNIPHIER_PIN_IECTRL_NONE, + 11, UNIPHIER_PIN_DRV_4_8, + 11, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(12, "XERWE0", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_4_8, + 12, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(13, "XERWE1", UNIPHIER_PIN_IECTRL_NONE, + 13, UNIPHIER_PIN_DRV_4_8, + 13, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(14, "ERXW", UNIPHIER_PIN_IECTRL_NONE, + 14, UNIPHIER_PIN_DRV_4_8, + 14, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(15, "ES0", UNIPHIER_PIN_IECTRL_NONE, + 15, UNIPHIER_PIN_DRV_4_8, + 15, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(16, "ES1", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_4_8, + 16, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(17, "ES2", UNIPHIER_PIN_IECTRL_NONE, + 17, UNIPHIER_PIN_DRV_4_8, + 17, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(18, "XECS1", UNIPHIER_PIN_IECTRL_NONE, + 18, UNIPHIER_PIN_DRV_4_8, + 18, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(19, "XNFRE", UNIPHIER_PIN_IECTRL_NONE, + 19, UNIPHIER_PIN_DRV_4_8, + 19, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(20, "XNFWE", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_4_8, + 20, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(21, "NFALE", UNIPHIER_PIN_IECTRL_NONE, + 21, UNIPHIER_PIN_DRV_4_8, + 21, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(22, "NFCLE", UNIPHIER_PIN_IECTRL_NONE, + 22, UNIPHIER_PIN_DRV_4_8, + 22, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(23, "XNFWP", UNIPHIER_PIN_IECTRL_NONE, + 23, UNIPHIER_PIN_DRV_4_8, + 23, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(24, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE, + 24, UNIPHIER_PIN_DRV_4_8, + 24, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(25, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE, + 25, UNIPHIER_PIN_DRV_4_8, + 25, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(26, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE, + 26, UNIPHIER_PIN_DRV_4_8, + 26, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(27, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE, + 27, UNIPHIER_PIN_DRV_4_8, + 27, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(28, "NFD0", UNIPHIER_PIN_IECTRL_NONE, + 28, UNIPHIER_PIN_DRV_4_8, + 28, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(29, "NFD1", UNIPHIER_PIN_IECTRL_NONE, + 29, UNIPHIER_PIN_DRV_4_8, + 29, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(30, "NFD2", UNIPHIER_PIN_IECTRL_NONE, + 30, UNIPHIER_PIN_DRV_4_8, + 30, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(31, "NFD3", UNIPHIER_PIN_IECTRL_NONE, + 31, UNIPHIER_PIN_DRV_4_8, + 31, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(32, "NFD4", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_4_8, + 32, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(33, "NFD5", UNIPHIER_PIN_IECTRL_NONE, + 33, UNIPHIER_PIN_DRV_4_8, + 33, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(34, "NFD6", UNIPHIER_PIN_IECTRL_NONE, + 34, UNIPHIER_PIN_DRV_4_8, + 34, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(35, "NFD7", UNIPHIER_PIN_IECTRL_NONE, + 35, UNIPHIER_PIN_DRV_4_8, + 35, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(36, "XERST", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_4_8, + 36, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(37, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE, + 37, UNIPHIER_PIN_DRV_4_8, + 37, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(38, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE, + 38, UNIPHIER_PIN_DRV_4_8, + 38, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(39, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE, + 39, UNIPHIER_PIN_DRV_4_8, + 39, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(40, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_4_8, + 40, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(41, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE, + 41, UNIPHIER_PIN_DRV_4_8, + 41, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(42, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE, + 42, UNIPHIER_PIN_DRV_4_8, + 42, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(43, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE, + 43, UNIPHIER_PIN_DRV_4_8, + 43, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(44, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_4_8, + 44, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(45, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE, + 45, UNIPHIER_PIN_DRV_4_8, + 45, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(46, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE, + 46, UNIPHIER_PIN_DRV_4_8, + 46, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(47, "TXD0", 0, + 47, UNIPHIER_PIN_DRV_4_8, + 47, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(48, "RXD0", 0, + 48, UNIPHIER_PIN_DRV_4_8, + 48, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(49, "TXD1", 0, + 49, UNIPHIER_PIN_DRV_4_8, + 49, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(50, "RXD1", 0, + 50, UNIPHIER_PIN_DRV_4_8, + 50, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(51, "TXD2", UNIPHIER_PIN_IECTRL_NONE, + 51, UNIPHIER_PIN_DRV_4_8, + 51, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(52, "RXD2", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_4_8, + 52, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(53, "TXD3", 0, + 53, UNIPHIER_PIN_DRV_4_8, + 53, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(54, "RXD3", 0, + 54, UNIPHIER_PIN_DRV_4_8, + 54, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(55, "MS0CS0", 0, + 55, UNIPHIER_PIN_DRV_4_8, + 55, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(56, "MS0DO", 0, + 56, UNIPHIER_PIN_DRV_4_8, + 56, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(57, "MS0DI", 0, + 57, UNIPHIER_PIN_DRV_4_8, + 57, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(58, "MS0CLK", 0, + 58, UNIPHIER_PIN_DRV_4_8, + 58, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(59, "CSCLK", 0, + 59, UNIPHIER_PIN_DRV_4_8, + 59, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(60, "CSBPTM", 0, + 60, UNIPHIER_PIN_DRV_4_8, + 60, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(61, "CSBMTP", 0, + 61, UNIPHIER_PIN_DRV_4_8, + 61, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(62, "XCINTP", 0, + 62, UNIPHIER_PIN_DRV_4_8, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(63, "XCINTM", 0, + 63, UNIPHIER_PIN_DRV_4_8, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(64, "XCMPREQ", 0, + 64, UNIPHIER_PIN_DRV_4_8, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "XSRST", 0, + 65, UNIPHIER_PIN_DRV_4_8, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "LPST", UNIPHIER_PIN_IECTRL_NONE, + 66, UNIPHIER_PIN_DRV_4_8, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "PWMA", 0, + 67, UNIPHIER_PIN_DRV_4_8, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "XIRQ0", 0, + 68, UNIPHIER_PIN_DRV_4_8, + 68, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(69, "XIRQ1", 0, + 69, UNIPHIER_PIN_DRV_4_8, + 69, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(70, "XIRQ2", 0, + 70, UNIPHIER_PIN_DRV_4_8, + 70, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(71, "XIRQ3", 0, + 71, UNIPHIER_PIN_DRV_4_8, + 71, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(72, "XIRQ4", 0, + 72, UNIPHIER_PIN_DRV_4_8, + 72, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(73, "XIRQ5", 0, + 73, UNIPHIER_PIN_DRV_4_8, + 73, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(74, "XIRQ6", 0, + 74, UNIPHIER_PIN_DRV_4_8, + 74, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(75, "XIRQ7", 0, + 75, UNIPHIER_PIN_DRV_4_8, + 75, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(76, "XIRQ8", 0, + 76, UNIPHIER_PIN_DRV_4_8, + 76, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(77, "XIRQ9", 0, + 77, UNIPHIER_PIN_DRV_4_8, + 77, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(78, "XIRQ10", 0, + 78, UNIPHIER_PIN_DRV_4_8, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "XIRQ11", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "XIRQ12", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "XIRQ13", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "XIRQ14", 0, + 82, UNIPHIER_PIN_DRV_4_8, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "XIRQ15", 0, + 83, UNIPHIER_PIN_DRV_4_8, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "XIRQ16", 0, + 84, UNIPHIER_PIN_DRV_4_8, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 85, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(86, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "XIRQ19", 0, + 87, UNIPHIER_PIN_DRV_4_8, + 87, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(88, "XIRQ20", 0, + 88, UNIPHIER_PIN_DRV_4_8, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "PORT00", 0, + 89, UNIPHIER_PIN_DRV_4_8, + 89, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(90, "PORT01", 0, + 90, UNIPHIER_PIN_DRV_4_8, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "PORT02", 0, + 91, UNIPHIER_PIN_DRV_4_8, + 91, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(92, "PORT03", 0, + 92, UNIPHIER_PIN_DRV_4_8, + 92, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(93, "PORT04", 0, + 93, UNIPHIER_PIN_DRV_4_8, + 93, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(94, "PORT05", 0, + 94, UNIPHIER_PIN_DRV_4_8, + 94, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(95, "PORT06", 0, + 95, UNIPHIER_PIN_DRV_4_8, + 95, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(96, "PORT07", 0, + 96, UNIPHIER_PIN_DRV_4_8, + 96, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(97, "PORT10", 0, + 97, UNIPHIER_PIN_DRV_4_8, + 97, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(98, "PORT11", 0, + 98, UNIPHIER_PIN_DRV_4_8, + 98, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(99, "PORT12", 0, + 99, UNIPHIER_PIN_DRV_4_8, + 99, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(100, "PORT13", 0, + 100, UNIPHIER_PIN_DRV_4_8, + 100, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(101, "PORT14", 0, + 101, UNIPHIER_PIN_DRV_4_8, + 101, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "PORT15", 0, + 102, UNIPHIER_PIN_DRV_4_8, + 102, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(103, "PORT16", 0, + 103, UNIPHIER_PIN_DRV_4_8, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(104, "PORT17", 0, + 104, UNIPHIER_PIN_DRV_4_8, + 104, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(105, "T0HPD", 0, + 105, UNIPHIER_PIN_DRV_4_8, + 105, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(106, "T1HPD", 0, + 106, UNIPHIER_PIN_DRV_4_8, + 106, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(107, "R0HPD", 0, + 107, UNIPHIER_PIN_DRV_4_8, + 107, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(108, "R1HPD", 0, + 108, UNIPHIER_PIN_DRV_4_8, + 108, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(109, "XPERST", 0, + 109, UNIPHIER_PIN_DRV_4_8, + 109, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(110, "XPEWAKE", 0, + 110, UNIPHIER_PIN_DRV_4_8, + 110, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(111, "XPECLKRQ", 0, + 111, UNIPHIER_PIN_DRV_4_8, + 111, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(112, "SDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 112, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(113, "SCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 113, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(114, "SDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 114, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(115, "SCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 115, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(116, "SDA2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 116, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(117, "SCL2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 117, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(118, "SDA3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 118, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(119, "SCL3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 119, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(120, "SPISYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 120, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(121, "SPISCLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 121, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "SPITXD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 122, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(123, "SPIRXD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 123, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 124, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(125, "USB0OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 125, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(126, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 126, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(127, "USB1OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 127, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(128, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 128, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(129, "USB2OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 129, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(130, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 130, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(131, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 131, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(132, "SMTD0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 132, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(133, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 133, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(134, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 134, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(135, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 135, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(136, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 136, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(137, "SMTD1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 137, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(138, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 138, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(139, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 139, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(140, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 140, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(141, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 141, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(142, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 142, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(143, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 143, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(144, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 144, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(145, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 145, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(146, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 146, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(147, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 147, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(148, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 148, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(149, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 149, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(150, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 150, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(151, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 151, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(152, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 152, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(153, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 153, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(154, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 154, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(155, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 155, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(156, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 156, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(157, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 157, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(158, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 158, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(159, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 159, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(160, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 160, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(161, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 161, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(162, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 162, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(163, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 163, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(164, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 164, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(165, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 165, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(166, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 166, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(167, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 167, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(168, "CH7CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 168, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(169, "CH7PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 169, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(170, "CH7VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 170, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(171, "CH7DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 171, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(172, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 172, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(173, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 173, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(174, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 174, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(175, "AI1D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 175, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(176, "AI1D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 176, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(177, "AI1D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 177, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(178, "AI1D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 178, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(179, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 179, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(180, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 180, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(181, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 181, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(182, "AI2D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 182, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(183, "AI2D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 183, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(184, "AI2D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 184, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(185, "AI2D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 185, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(186, "AI3ADCCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 186, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(187, "AI3BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 187, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(188, "AI3LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 188, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(189, "AI3D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 189, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(190, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 190, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(191, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 191, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(192, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 192, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(193, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 193, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(194, "AO1D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 194, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(195, "AO1D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 195, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(196, "AO1D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 196, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(197, "AO1D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 197, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(198, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 198, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(199, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 199, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(200, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 200, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(201, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 201, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(202, "AO2D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 202, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(203, "AO2D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 203, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(204, "AO2D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 204, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(205, "AO2D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 205, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(206, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 206, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(207, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 207, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(208, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 208, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(209, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 209, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(210, "AO4DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 210, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(211, "AO4BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 211, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(212, "AO4LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 212, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(213, "AO4DMIX", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 213, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(214, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 214, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(215, "VI1C0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 215, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(216, "VI1C1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 216, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(217, "VI1C2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 217, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(218, "VI1C3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 218, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(219, "VI1C4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 219, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(220, "VI1C5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 220, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(221, "VI1C6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 221, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(222, "VI1C7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 222, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(223, "VI1C8", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 223, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(224, "VI1C9", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 224, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(225, "VI1Y0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 225, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(226, "VI1Y1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 226, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(227, "VI1Y2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 227, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(228, "VI1Y3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 228, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(229, "VI1Y4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 229, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(230, "VI1Y5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 230, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(231, "VI1Y6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 231, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(232, "VI1Y7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 232, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(233, "VI1Y8", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 233, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(234, "VI1Y9", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 234, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(235, "VI1DE", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 235, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(236, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 236, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(237, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 237, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(238, "VO1CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 238, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(239, "VO1D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 239, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(240, "VO1D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 240, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(241, "VO1D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 241, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(242, "VO1D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 242, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(243, "VO1D4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 243, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(244, "VO1D5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 244, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(245, "VO1D6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 245, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(246, "VO1D7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 246, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(247, "SDCD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 247, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(248, "SDWP", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 248, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(249, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 249, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(251, "SDCMD", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(252, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE, + 48, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(253, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE, + 52, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(254, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE, + 56, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(255, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE, + 60, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0}; +static const unsigned i2c0_pins[] = {112, 113}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {114, 115}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {116, 117}; +static const unsigned i2c2_muxvals[] = {0, 0}; +static const unsigned i2c3_pins[] = {118, 119}; +static const unsigned i2c3_muxvals[] = {0, 0}; +static const unsigned i2c5_pins[] = {87, 88}; +static const unsigned i2c5_muxvals[] = {2, 2}; +static const unsigned i2c5b_pins[] = {196, 197}; +static const unsigned i2c5b_muxvals[] = {2, 2}; +static const unsigned i2c5c_pins[] = {215, 216}; +static const unsigned i2c5c_muxvals[] = {2, 2}; +static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30, + 31, 32, 33, 34, 35}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {26, 27}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned uart0_pins[] = {47, 48}; +static const unsigned uart0_muxvals[] = {0, 0}; +static const unsigned uart0b_pins[] = {227, 228}; +static const unsigned uart0b_muxvals[] = {3, 3}; +static const unsigned uart1_pins[] = {49, 50}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {51, 52}; +static const unsigned uart2_muxvals[] = {0, 0}; +static const unsigned uart3_pins[] = {53, 54}; +static const unsigned uart3_muxvals[] = {0, 0}; +static const unsigned usb0_pins[] = {124, 125}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {126, 127}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {128, 129}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned port_range0_pins[] = { + 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */ + 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */ + 251, 252, 253, 254, 255, 247, 248, 249, /* PORT2x */ + 39, 40, 41, 42, 43, 44, 45, 46, /* PORT3x */ + 156, 157, 158, 159, 160, 161, 162, 163, /* PORT4x */ + 164, 165, 166, 167, 168, 169, 170, 171, /* PORT5x */ + 190, 191, 192, 193, 194, 195, 196, 197, /* PORT6x */ + 198, 199, 200, 201, 202, 203, 204, 205, /* PORT7x */ + 120, 121, 122, 123, 55, 56, 57, 58, /* PORT8x */ + 124, 125, 126, 127, 49, 50, 53, 54, /* PORT9x */ + 148, 149, 150, 151, 152, 153, 154, 155, /* PORT10x */ + 133, 134, 131, 130, 138, 139, 136, 135, /* PORT11x */ + 28, 29, 30, 31, 32, 33, 34, 35, /* PORT12x */ + 179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */ + 4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */ +}; +static const unsigned port_range0_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ +}; +static const unsigned port_range1_pins[] = { + 109, 110, 111, /* PORT175-177 */ + 206, 207, 208, 209, 210, 211, 212, 213, /* PORT18x */ + 12, 13, 14, 15, 16, 17, 107, 108, /* PORT19x */ + 140, 141, 142, 143, 144, 145, 146, 147, /* PORT20x */ + 59, 60, 61, 62, 63, 64, 65, 66, /* PORT21x */ + 214, 215, 216, 217, 218, 219, 220, 221, /* PORT22x */ + 222, 223, 224, 225, 226, 227, 228, 229, /* PORT23x */ + 19, 20, 21, 22, 23, 24, 25, 26, /* PORT24x */ + 230, 231, 232, 233, 234, 235, 236, 237, /* PORT25x */ + 239, 240, 241, 242, 243, 244, 245, 246, /* PORT26x */ + 172, 173, 174, 175, 176, 177, 178, 129, /* PORT27x */ + 0, 1, 2, 67, 85, 86, 87, 88, /* PORT28x */ + 105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */ + 183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */ +}; +static const unsigned port_range1_muxvals[] = { + 15, 15, 15, /* PORT175-177 */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT29x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT30x */ +}; +static const unsigned xirq_pins[] = { + 68, 69, 70, 71, 72, 73, 74, 75, /* XIRQ0-7 */ + 76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */ + 84, 85, 86, 87, 88, /* XIRQ16-20 */ +}; +static const unsigned xirq_muxvals[] = { + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */ + 14, 14, 14, 14, 14, /* XIRQ16-20 */ +}; +static const unsigned xirq_alternatives_pins[] = { + 91, 92, 239, 144, 240, 156, 241, 106, 128, +}; +static const unsigned xirq_alternatives_muxvals[] = { + 14, 14, 14, 14, 14, 14, 14, 14, 14, +}; + +static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c5), + UNIPHIER_PINCTRL_GROUP(i2c5b), + UNIPHIER_PINCTRL_GROUP(i2c5c), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119), + UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 8), +}; + +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"}; +static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const uart0_groups[] = {"uart0", "uart0b"}; +static const char * const uart1_groups[] = {"uart1"}; +static const char * const uart2_groups[] = {"uart2"}; +static const char * const uart3_groups[] = {"uart3"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2"}; +static const char * const port_groups[] = { + "port00", "port01", "port02", "port03", + "port04", "port05", "port06", "port07", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port20", "port21", "port22", "port23", + "port24", "port25", "port26", "port27", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port40", "port41", "port42", "port43", + "port44", "port45", "port46", "port47", + "port50", "port51", "port52", "port53", + "port54", "port55", "port56", "port57", + "port60", "port61", "port62", "port63", + "port64", "port65", "port66", "port67", + "port70", "port71", "port72", "port73", + "port74", "port75", "port76", "port77", + "port80", "port81", "port82", "port83", + "port84", "port85", "port86", "port87", + "port90", "port91", "port92", "port93", + "port94", "port95", "port96", "port97", + "port100", "port101", "port102", "port103", + "port104", "port105", "port106", "port107", + "port110", "port111", "port112", "port113", + "port114", "port115", "port116", "port117", + "port120", "port121", "port122", "port123", + "port124", "port125", "port126", "port127", + "port130", "port131", "port132", "port133", + "port134", "port135", "port136", "port137", + "port140", "port141", "port142", "port143", + "port144", "port145", "port146", "port147", + /* port150-174 missing */ + /* none */ "port175", "port176", "port177", + "port180", "port181", "port182", "port183", + "port184", "port185", "port186", "port187", + "port190", "port191", "port192", "port193", + "port194", "port195", "port196", "port197", + "port200", "port201", "port202", "port203", + "port204", "port205", "port206", "port207", + "port210", "port211", "port212", "port213", + "port214", "port215", "port216", "port217", + "port220", "port221", "port222", "port223", + "port224", "port225", "port226", "port227", + "port230", "port231", "port232", "port233", + "port234", "port235", "port236", "port237", + "port240", "port241", "port242", "port243", + "port244", "port245", "port246", "port247", + "port250", "port251", "port252", "port253", + "port254", "port255", "port256", "port257", + "port260", "port261", "port262", "port263", + "port264", "port265", "port266", "port267", + "port270", "port271", "port272", "port273", + "port274", "port275", "port276", "port277", + "port280", "port281", "port282", "port283", + "port284", "port285", "port286", "port287", + "port290", "port291", "port292", "port293", + "port294", "port295", "port296", "port297", + "port300", "port301", "port302", "port303", + "port304", "port305", "port306", "port307", +}; +static const char * const xirq_groups[] = { + "xirq0", "xirq1", "xirq2", "xirq3", + "xirq4", "xirq5", "xirq6", "xirq7", + "xirq8", "xirq9", "xirq10", "xirq11", + "xirq12", "xirq13", "xirq14", "xirq15", + "xirq16", "xirq17", "xirq18", "xirq19", + "xirq20", + "xirq3b", "xirq4b", "xirq16b", "xirq17b", "xirq17c", + "xirq18b", "xirq18c", "xirq19b", "xirq20b", +}; + +static const struct uniphier_pinmux_function ph1_pro5_functions[] = { + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(i2c5), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(port), + UNIPHIER_PINMUX_FUNCTION(xirq), +}; + +static struct uniphier_pinctrl_socdata ph1_pro5_pindata = { + .groups = ph1_pro5_groups, + .groups_count = ARRAY_SIZE(ph1_pro5_groups), + .functions = ph1_pro5_functions, + .functions_count = ARRAY_SIZE(ph1_pro5_functions), + .mux_bits = 4, + .reg_stride = 8, + .load_pinctrl = true, +}; + +static struct pinctrl_desc ph1_pro5_pinctrl_desc = { + .name = DRIVER_NAME, + .pins = ph1_pro5_pins, + .npins = ARRAY_SIZE(ph1_pro5_pins), + .owner = THIS_MODULE, +}; + +static int ph1_pro5_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &ph1_pro5_pinctrl_desc, + &ph1_pro5_pindata); +} + +static const struct of_device_id ph1_pro5_pinctrl_match[] = { + { .compatible = "socionext,ph1-pro5-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ph1_pro5_pinctrl_match); + +static struct platform_driver ph1_pro5_pinctrl_driver = { + .probe = ph1_pro5_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = ph1_pro5_pinctrl_match, + }, +}; +module_platform_driver(ph1_pro5_pinctrl_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier PH1-Pro5 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 3c0fd8e3de93fc12b35cf5be585a5d8dc68b7162 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:06 +0900 Subject: pinctrl: UniPhier: add UniPhier ProXstream2 pinctrl driver Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/uniphier/Kconfig | 4 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-proxstream2.c | 1269 ++++++++++++++++++++++++ 3 files changed, 1274 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-proxstream2.c diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 89bda60066bd..69c5d5fa61da 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -21,4 +21,8 @@ config PINCTRL_UNIPHIER_PH1_PRO5 tristate "UniPhier PH1-Pro5 SoC pinctrl driver" select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PROXSTREAM2 + tristate "UniPhier ProXstream2 SoC pinctrl driver" + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b0cd3e86bc94..aed038c59f04 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c new file mode 100644 index 000000000000..3f036e236ad9 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c @@ -0,0 +1,1269 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +#define DRIVER_NAME "proxstream2-pinctrl" + +static const struct pinctrl_pin_desc proxstream2_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_4_8, + 0, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE, + 1, UNIPHIER_PIN_DRV_4_8, + 1, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE, + 2, UNIPHIER_PIN_DRV_4_8, + 2, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE, + 3, UNIPHIER_PIN_DRV_4_8, + 3, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_4_8, + 4, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE, + 5, UNIPHIER_PIN_DRV_4_8, + 5, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE, + 6, UNIPHIER_PIN_DRV_4_8, + 6, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE, + 7, UNIPHIER_PIN_DRV_4_8, + 7, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_4_8, + 8, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE, + 9, UNIPHIER_PIN_DRV_4_8, + 9, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE, + 10, UNIPHIER_PIN_DRV_4_8, + 10, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE, + 11, UNIPHIER_PIN_DRV_4_8, + 11, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_4_8, + 12, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE, + 13, UNIPHIER_PIN_DRV_4_8, + 13, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE, + 14, UNIPHIER_PIN_DRV_4_8, + 14, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(15, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 15, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(16, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 16, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(17, "SMTD0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 17, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(18, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 18, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(19, "SMTCLK0CG", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 19, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(20, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 20, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(21, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 21, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(22, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 22, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(23, "SMTD1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 23, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(24, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 24, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(25, "SMTCLK1CG", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 25, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(26, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 26, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(27, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 27, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(28, "XIRQ19", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 28, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(29, "XIRQ20", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 29, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE, + 30, UNIPHIER_PIN_DRV_4_8, + 30, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE, + 31, UNIPHIER_PIN_DRV_4_8, + 31, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_4_8, + 32, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE, + 33, UNIPHIER_PIN_DRV_4_8, + 33, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE, + 34, UNIPHIER_PIN_DRV_4_8, + 34, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE, + 35, UNIPHIER_PIN_DRV_4_8, + 35, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_4_8, + 36, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE, + 37, UNIPHIER_PIN_DRV_4_8, + 37, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE, + 38, UNIPHIER_PIN_DRV_4_8, + 38, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE, + 39, UNIPHIER_PIN_DRV_4_8, + 39, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_4_8, + 40, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE, + 41, UNIPHIER_PIN_DRV_4_8, + 41, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE, + 42, UNIPHIER_PIN_DRV_4_8, + 42, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE, + 43, UNIPHIER_PIN_DRV_4_8, + 43, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_4_8, + 44, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE, + 45, UNIPHIER_PIN_DRV_4_8, + 45, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE, + 46, UNIPHIER_PIN_DRV_4_8, + 46, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 53, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 54, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 55, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 56, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 57, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 58, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 59, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 60, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 61, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 68, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(69, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 69, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(70, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 70, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 71, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(72, "XIRQ9", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 72, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(73, "XIRQ10", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 73, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(74, "XIRQ16", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 74, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(75, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 75, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(76, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 76, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(77, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 77, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(78, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 85, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(86, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "STS0CLKO", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 87, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(88, "STS0SYNCO", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "STS0VALO", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 89, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(90, "STS0DATAO", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 91, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(92, "PORT163", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 92, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(93, "PORT165", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 93, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(94, "PORT166", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 94, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(95, "PORT132", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 95, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(96, "PORT133", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 96, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(97, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 97, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(98, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 98, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(99, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 99, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(100, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 100, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(101, "AI2D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 101, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "AI2D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 102, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(103, "AI2D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(104, "AI2D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 104, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(105, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 105, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(106, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 106, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(107, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 107, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(108, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 108, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 109, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 110, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 111, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 112, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(113, "TXD2", 0, + 113, UNIPHIER_PIN_DRV_4_8, + 113, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(114, "RXD2", 0, + 114, UNIPHIER_PIN_DRV_4_8, + 114, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(115, "TXD1", 0, + 115, UNIPHIER_PIN_DRV_4_8, + 115, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(116, "RXD1", 0, + 116, UNIPHIER_PIN_DRV_4_8, + 116, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(117, "PORT190", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 117, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(118, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 118, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(119, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 119, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(120, "VI1DE", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 120, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 121, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 122, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(123, "VI1G2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 123, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "VI1G3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 124, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(125, "VI1G4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 125, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(126, "VI1G5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 126, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(127, "VI1G6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 127, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(128, "VI1G7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 128, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(129, "VI1G8", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 129, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(130, "VI1G9", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 130, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(131, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 131, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 132, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 133, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(134, "VI1R2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 134, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(135, "VI1R3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 135, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(136, "VI1R4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 136, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(137, "VI1R5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 137, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(138, "VI1R6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 138, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(139, "VI1R7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 139, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(140, "VI1R8", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 140, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(141, "VI1R9", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 141, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE, + 142, UNIPHIER_PIN_DRV_4_8, + 142, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(143, "MDC", 0, + 143, UNIPHIER_PIN_DRV_4_8, + 143, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(144, "MDIO", 0, + 144, UNIPHIER_PIN_DRV_4_8, + 144, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0, + 145, UNIPHIER_PIN_DRV_4_8, + 145, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0, + 146, UNIPHIER_PIN_DRV_4_8, + 146, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0, + 147, UNIPHIER_PIN_DRV_4_8, + 147, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0, + 148, UNIPHIER_PIN_DRV_4_8, + 148, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0, + 149, UNIPHIER_PIN_DRV_4_8, + 149, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0, + 150, UNIPHIER_PIN_DRV_4_8, + 150, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0, + 151, UNIPHIER_PIN_DRV_4_8, + 151, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0, + 152, UNIPHIER_PIN_DRV_4_8, + 152, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0, + 153, UNIPHIER_PIN_DRV_4_8, + 153, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0, + 154, UNIPHIER_PIN_DRV_4_8, + 154, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0, + 155, UNIPHIER_PIN_DRV_4_8, + 155, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0, + 156, UNIPHIER_PIN_DRV_4_8, + 156, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0, + 157, UNIPHIER_PIN_DRV_4_8, + 157, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0, + 158, UNIPHIER_PIN_DRV_4_8, + 158, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(159, "SDA3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 159, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(160, "SCL3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 160, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(161, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 161, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(162, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 162, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(163, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 163, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(164, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 164, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(165, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 165, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(166, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 166, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(167, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 167, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(168, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 168, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(169, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 169, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(170, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 170, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(171, "SDA2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 171, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(172, "SCL2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 172, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(173, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 173, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(174, "AI1D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 174, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(175, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 175, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(176, "AO2D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 176, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(177, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 177, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(178, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 178, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(179, "PORT222", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 179, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(180, "PORT223", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 180, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(181, "PORT224", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 181, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(182, "PORT225", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 182, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(183, "PORT226", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 183, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(184, "PORT227", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 184, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(185, "PORT230", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 185, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(186, "FANPWM", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 186, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(187, "HRDDCSDA0", 0, + 187, UNIPHIER_PIN_DRV_4_8, + 187, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(188, "HRDDCSCL0", 0, + 188, UNIPHIER_PIN_DRV_4_8, + 188, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(189, "HRDDCSDA1", 0, + 189, UNIPHIER_PIN_DRV_4_8, + 189, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(190, "HRDDCSCL1", 0, + 190, UNIPHIER_PIN_DRV_4_8, + 190, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(191, "HTDDCSDA0", 0, + 191, UNIPHIER_PIN_DRV_4_8, + 191, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(192, "HTDDCSCL0", 0, + 192, UNIPHIER_PIN_DRV_4_8, + 192, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(193, "HTDDCSDA1", 0, + 193, UNIPHIER_PIN_DRV_4_8, + 193, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(194, "HTDDCSCL1", 0, + 194, UNIPHIER_PIN_DRV_4_8, + 194, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(195, "PORT241", 0, + 195, UNIPHIER_PIN_DRV_4_8, + 195, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(196, "PORT242", 0, + 196, UNIPHIER_PIN_DRV_4_8, + 196, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(197, "PORT243", 0, + 197, UNIPHIER_PIN_DRV_4_8, + 197, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(198, "MVSYNC", 0, + 198, UNIPHIER_PIN_DRV_4_8, + 198, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(199, "SPISYNC0", UNIPHIER_PIN_IECTRL_NONE, + 199, UNIPHIER_PIN_DRV_4_8, + 199, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(200, "SPISCLK0", UNIPHIER_PIN_IECTRL_NONE, + 200, UNIPHIER_PIN_DRV_4_8, + 200, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(201, "SPITXD0", UNIPHIER_PIN_IECTRL_NONE, + 201, UNIPHIER_PIN_DRV_4_8, + 201, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(202, "SPIRXD0", UNIPHIER_PIN_IECTRL_NONE, + 202, UNIPHIER_PIN_DRV_4_8, + 202, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(203, "CK54EXI", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 203, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(204, "AEXCKA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 204, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(205, "AEXCKA2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 205, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(206, "CK27EXI", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 206, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(207, "STCDIN", 0, + 207, UNIPHIER_PIN_DRV_4_8, + 207, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(208, "PHSYNI", 0, + 208, UNIPHIER_PIN_DRV_4_8, + 208, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(209, "PVSYNI", 0, + 209, UNIPHIER_PIN_DRV_4_8, + 209, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(210, "MVSYN", UNIPHIER_PIN_IECTRL_NONE, + 210, UNIPHIER_PIN_DRV_4_8, + 210, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(211, "STCV", UNIPHIER_PIN_IECTRL_NONE, + 211, UNIPHIER_PIN_DRV_4_8, + 211, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(212, "PORT262", UNIPHIER_PIN_IECTRL_NONE, + 212, UNIPHIER_PIN_DRV_4_8, + 212, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(213, "USB0VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 213, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(214, "USB1VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 214, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(215, "PORT265", UNIPHIER_PIN_IECTRL_NONE, + 215, UNIPHIER_PIN_DRV_4_8, + 215, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(216, "CK25O", 0, + 216, UNIPHIER_PIN_DRV_4_8, + 216, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(217, "TXD0", 0, + 217, UNIPHIER_PIN_DRV_4_8, + 217, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(218, "RXD0", 0, + 218, UNIPHIER_PIN_DRV_4_8, + 218, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(219, "TXD3", 0, + 219, UNIPHIER_PIN_DRV_4_8, + 219, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(220, "RXD3", 0, + 220, UNIPHIER_PIN_DRV_4_8, + 220, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(221, "PORT273", 0, + 221, UNIPHIER_PIN_DRV_4_8, + 221, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(222, "STCDOUTC", 0, + 222, UNIPHIER_PIN_DRV_4_8, + 222, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(223, "PORT274", 0, + 223, UNIPHIER_PIN_DRV_4_8, + 223, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(224, "PORT275", 0, + 224, UNIPHIER_PIN_DRV_4_8, + 224, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(225, "PORT276", 0, + 225, UNIPHIER_PIN_DRV_4_8, + 225, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(226, "PORT277", 0, + 226, UNIPHIER_PIN_DRV_4_8, + 226, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(227, "PORT280", 0, + 227, UNIPHIER_PIN_DRV_4_8, + 227, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(228, "PORT281", 0, + 228, UNIPHIER_PIN_DRV_4_8, + 228, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(229, "PORT282", 0, + 229, UNIPHIER_PIN_DRV_4_8, + 229, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(230, "PORT283", 0, + 230, UNIPHIER_PIN_DRV_4_8, + 230, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(231, "PORT284", 0, + 231, UNIPHIER_PIN_DRV_4_8, + 231, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(232, "PORT285", 0, + 232, UNIPHIER_PIN_DRV_4_8, + 232, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(233, "T0HPD", 0, + 233, UNIPHIER_PIN_DRV_4_8, + 233, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(234, "T1HPD", 0, + 234, UNIPHIER_PIN_DRV_4_8, + 234, UNIPHIER_PIN_PULL_DOWN), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9}; +static const unsigned i2c0_pins[] = {109, 110}; +static const unsigned i2c0_muxvals[] = {8, 8}; +static const unsigned i2c1_pins[] = {111, 112}; +static const unsigned i2c1_muxvals[] = {8, 8}; +static const unsigned i2c2_pins[] = {171, 172}; +static const unsigned i2c2_muxvals[] = {8, 8}; +static const unsigned i2c3_pins[] = {159, 160}; +static const unsigned i2c3_muxvals[] = {8, 8}; +static const unsigned i2c5_pins[] = {183, 184}; +static const unsigned i2c5_muxvals[] = {11, 11}; +static const unsigned i2c6_pins[] = {185, 186}; +static const unsigned i2c6_muxvals[] = {11, 11}; +static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41, + 42, 43, 44, 45, 46}; +static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8}; +static const unsigned nand_cs1_pins[] = {37, 38}; +static const unsigned nand_cs1_muxvals[] = {8, 8}; +static const unsigned uart0_pins[] = {217, 218}; +static const unsigned uart0_muxvals[] = {8, 8}; +static const unsigned uart0b_pins[] = {179, 180}; +static const unsigned uart0b_muxvals[] = {10, 10}; +static const unsigned uart1_pins[] = {115, 116}; +static const unsigned uart1_muxvals[] = {8, 8}; +static const unsigned uart2_pins[] = {113, 114}; +static const unsigned uart2_muxvals[] = {8, 8}; +static const unsigned uart3_pins[] = {219, 220}; +static const unsigned uart3_muxvals[] = {8, 8}; +static const unsigned uart3b_pins[] = {181, 182}; +static const unsigned uart3b_muxvals[] = {10, 10}; +static const unsigned usb0_pins[] = {56, 57}; +static const unsigned usb0_muxvals[] = {8, 8}; +static const unsigned usb1_pins[] = {58, 59}; +static const unsigned usb1_muxvals[] = {8, 8}; +static const unsigned usb2_pins[] = {60, 61}; +static const unsigned usb2_muxvals[] = {8, 8}; +static const unsigned usb3_pins[] = {62, 63}; +static const unsigned usb3_muxvals[] = {8, 8}; +static const unsigned port_range0_pins[] = { + 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */ + 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */ + 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */ + 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */ + 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */ + 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */ + 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */ + 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */ + 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */ + 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */ +}; +static const unsigned port_range0_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ +}; +static const unsigned port_range1_pins[] = { + 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */ + 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */ + 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */ + 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */ + 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */ + 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */ + 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */ + 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */ + 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */ + 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */ + 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */ + 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */ + 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */ + 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */ + 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */ + 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */ + 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */ +}; +static const unsigned port_range1_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */ +}; +static const unsigned xirq_pins[] = { + 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */ + 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */ + 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */ +}; +static const unsigned xirq_muxvals[] = { + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ +}; + +static const struct uniphier_pinctrl_group proxstream2_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c5), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(uart3b), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107), + UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108), + UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109), + UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110), + UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111), + UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112), + UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113), + UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114), + UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115), + UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116), + UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117), + UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118), + UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119), + UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120), + UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121), + UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122), + UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123), + UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124), + UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125), + UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126), + UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127), + UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128), + UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129), + UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130), + UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131), + UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132), + UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133), + UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134), + UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23), +}; + +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const i2c5_groups[] = {"i2c5"}; +static const char * const i2c6_groups[] = {"i2c6"}; +static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const uart0_groups[] = {"uart0", "uart0b"}; +static const char * const uart1_groups[] = {"uart1"}; +static const char * const uart2_groups[] = {"uart2"}; +static const char * const uart3_groups[] = {"uart3", "uart3b"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2"}; +static const char * const usb3_groups[] = {"usb3"}; +static const char * const port_groups[] = { + "port00", "port01", "port02", "port03", + "port04", "port05", "port06", "port07", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port20", "port21", "port22", "port23", + "port24", "port25", "port26", "port27", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port40", "port41", "port42", "port43", + "port44", "port45", "port46", "port47", + "port50", "port51", "port52", "port53", + "port54", "port55", "port56", "port57", + "port60", "port61", "port62", "port63", + "port64", "port65", "port66", "port67", + "port70", "port71", "port72", "port73", + "port74", "port75", "port76", "port77", + "port80", "port81", "port82", "port83", + "port84", "port85", "port86", "port87", + "port90", "port91", "port92", "port93", + "port94", "port95", "port96", "port97", + "port100", "port101", "port102", "port103", + "port104", "port105", "port106", "port107", + /* port110-117 missing */ + "port120", "port121", "port122", "port123", + "port124", "port125", "port126", "port127", + "port130", "port131", "port132", "port133", + "port134", "port135", "port136", "port137", + "port140", "port141", "port142", "port143", + "port144", "port145", "port146", "port147", + "port150", "port151", "port152", "port153", + "port154", "port155", "port156", "port157", + "port160", "port161", "port162", "port163", + "port164", "port165", "port166", "port167", + "port170", "port171", "port172", "port173", + "port174", "port175", "port176", "port177", + "port180", "port181", "port182", "port183", + "port184", "port185", "port186", "port187", + "port190", "port191", "port192", "port193", + "port194", "port195", "port196", "port197", + "port200", "port201", "port202", "port203", + "port204", "port205", "port206", "port207", + "port210", "port211", "port212", "port213", + "port214", "port215", "port216", "port217", + "port220", "port221", "port222", "port223", + "port224", "port225", "port226", "port227", + "port230", "port231", "port232", "port233", + "port234", "port235", "port236", "port237", + "port240", "port241", "port242", "port243", + "port244", "port245", "port246", "port247", + "port250", "port251", "port252", "port253", + "port254", "port255", "port256", "port257", + "port260", "port261", "port262", "port263", + "port264", "port265", "port266", "port267", + "port270", "port271", "port272", "port273", + "port274", "port275", "port276", "port277", + "port280", "port281", "port282", "port283", + "port284", "port285", "port286", "port287", +}; +static const char * const xirq_groups[] = { + "xirq0", "xirq1", "xirq2", "xirq3", + "xirq4", "xirq5", "xirq6", "xirq7", + "xirq8", "xirq9", "xirq10", "xirq11", + "xirq12", "xirq13", "xirq14", "xirq15", + "xirq16", "xirq17", "xirq18", "xirq19", + "xirq20", "xirq21", "xirq22", "xirq23", +}; + +static const struct uniphier_pinmux_function proxstream2_functions[] = { + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(i2c5), + UNIPHIER_PINMUX_FUNCTION(i2c6), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(usb3), + UNIPHIER_PINMUX_FUNCTION(port), + UNIPHIER_PINMUX_FUNCTION(xirq), +}; + +static struct uniphier_pinctrl_socdata proxstream2_pindata = { + .groups = proxstream2_groups, + .groups_count = ARRAY_SIZE(proxstream2_groups), + .functions = proxstream2_functions, + .functions_count = ARRAY_SIZE(proxstream2_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static struct pinctrl_desc proxstream2_pinctrl_desc = { + .name = DRIVER_NAME, + .pins = proxstream2_pins, + .npins = ARRAY_SIZE(proxstream2_pins), + .owner = THIS_MODULE, +}; + +static int proxstream2_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &proxstream2_pinctrl_desc, + &proxstream2_pindata); +} + +static const struct of_device_id proxstream2_pinctrl_match[] = { + { .compatible = "socionext,proxstream2-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, proxstream2_pinctrl_match); + +static struct platform_driver proxstream2_pinctrl_driver = { + .probe = proxstream2_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = proxstream2_pinctrl_match, + }, +}; +module_platform_driver(proxstream2_pinctrl_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier ProXstream2 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From b3b6616378a4dcf1e903c8ad70fabfe4c2ad529b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jul 2015 11:40:07 +0900 Subject: pinctrl: UniPhier: add UniPhier PH1-LD6b pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Changes in v2: - sort groups and funcs alphabetically - add i2c pin-mux settings - sort members of platform_driver - change to tristate - add THIS_MODULE to pinctrl_desc - use module_platform_driver Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/pinctrl/uniphier/Kconfig | 4 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c | 1274 +++++++++++++++++++++++++++ 3 files changed, 1279 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 69c5d5fa61da..eab23ef9ddbf 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -25,4 +25,8 @@ config PINCTRL_UNIPHIER_PROXSTREAM2 tristate "UniPhier ProXstream2 SoC pinctrl driver" select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_LD6B + tristate "UniPhier PH1-LD6b SoC pinctrl driver" + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index aed038c59f04..e215b1097297 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c new file mode 100644 index 000000000000..9720e697fbc1 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c @@ -0,0 +1,1274 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +#define DRIVER_NAME "ph1-ld6b-pinctrl" + +static const struct pinctrl_pin_desc ph1_ld6b_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_4_8, + 0, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE, + 1, UNIPHIER_PIN_DRV_4_8, + 1, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE, + 2, UNIPHIER_PIN_DRV_4_8, + 2, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE, + 3, UNIPHIER_PIN_DRV_4_8, + 3, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_4_8, + 4, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE, + 5, UNIPHIER_PIN_DRV_4_8, + 5, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE, + 6, UNIPHIER_PIN_DRV_4_8, + 6, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE, + 7, UNIPHIER_PIN_DRV_4_8, + 7, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_4_8, + 8, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE, + 9, UNIPHIER_PIN_DRV_4_8, + 9, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE, + 10, UNIPHIER_PIN_DRV_4_8, + 10, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE, + 11, UNIPHIER_PIN_DRV_4_8, + 11, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_4_8, + 12, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE, + 13, UNIPHIER_PIN_DRV_4_8, + 13, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE, + 14, UNIPHIER_PIN_DRV_4_8, + 14, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(15, "PCA00", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 15, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(16, "PCA01", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 16, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(17, "PCA02", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 17, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(18, "PCA03", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 18, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(19, "PCA04", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 19, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(20, "PCA05", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 20, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(21, "PCA06", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 21, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(22, "PCA07", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 22, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(23, "PCA08", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 23, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(24, "PCA09", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 24, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(25, "PCA10", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 25, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(26, "PCA11", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 26, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(27, "PCA12", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 27, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(28, "PCA13", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 28, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(29, "PCA14", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 29, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE, + 30, UNIPHIER_PIN_DRV_4_8, + 30, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE, + 31, UNIPHIER_PIN_DRV_4_8, + 31, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE, + 32, UNIPHIER_PIN_DRV_4_8, + 32, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE, + 33, UNIPHIER_PIN_DRV_4_8, + 33, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE, + 34, UNIPHIER_PIN_DRV_4_8, + 34, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE, + 35, UNIPHIER_PIN_DRV_4_8, + 35, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE, + 36, UNIPHIER_PIN_DRV_4_8, + 36, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE, + 37, UNIPHIER_PIN_DRV_4_8, + 37, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE, + 38, UNIPHIER_PIN_DRV_4_8, + 38, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE, + 39, UNIPHIER_PIN_DRV_4_8, + 39, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE, + 40, UNIPHIER_PIN_DRV_4_8, + 40, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE, + 41, UNIPHIER_PIN_DRV_4_8, + 41, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE, + 42, UNIPHIER_PIN_DRV_4_8, + 42, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE, + 43, UNIPHIER_PIN_DRV_4_8, + 43, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE, + 44, UNIPHIER_PIN_DRV_4_8, + 44, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE, + 45, UNIPHIER_PIN_DRV_4_8, + 45, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE, + 46, UNIPHIER_PIN_DRV_4_8, + 46, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE, + 0, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE, + 4, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE, + 8, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE, + 12, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE, + 16, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE, + 20, UNIPHIER_PIN_DRV_8_12_16_20, + -1, UNIPHIER_PIN_PULL_UP_FIXED), + UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 53, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 54, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 55, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 56, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 57, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 58, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 59, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 60, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 61, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(64, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "HS0VALOUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "HS0DOUT0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "HS0DOUT1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 68, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(69, "HS0DOUT2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 69, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(70, "HS0DOUT3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 70, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(71, "HS0DOUT4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 71, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(72, "HS0DOUT5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 72, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(73, "HS0DOUT6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 73, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(74, "HS0DOUT7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 74, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(75, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 75, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(76, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 76, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(77, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 77, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(78, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 85, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(86, "HS2BCLKIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "HS2SYNCIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 87, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(88, "HS2VALIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "HS2DIN0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 89, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(90, "HS2DIN1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "HS2DIN2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 91, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(92, "HS2DIN3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 92, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(93, "HS2DIN4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 93, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(94, "HS2DIN5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 94, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(95, "HS2DIN6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 95, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(96, "HS2DIN7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 96, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(97, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 97, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(98, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 98, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(99, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 99, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(100, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 100, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(101, "AO1D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 101, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "AO1D1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 102, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(103, "AO1D2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(104, "AO1D3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 104, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(105, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 105, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(106, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 106, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(107, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 107, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(108, "AO2D0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 108, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 109, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 110, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 111, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 112, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(113, "SBO0", 0, + 113, UNIPHIER_PIN_DRV_4_8, + 113, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(114, "SBI0", 0, + 114, UNIPHIER_PIN_DRV_4_8, + 114, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(115, "TXD1", 0, + 115, UNIPHIER_PIN_DRV_4_8, + 115, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(116, "RXD1", 0, + 116, UNIPHIER_PIN_DRV_4_8, + 116, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(117, "PWSRA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 117, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(118, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 118, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(119, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 119, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(120, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 120, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 121, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 122, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(123, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 123, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 124, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(125, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 125, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(126, "XIRQ8", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 126, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(127, "PORT00", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 127, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(128, "PORT01", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 128, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(129, "PORT02", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 129, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(130, "PORT03", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 130, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(131, "PORT04", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 131, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 132, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 133, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(134, "PORT07", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 134, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(135, "PORT10", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 135, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(136, "PORT11", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 136, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(137, "PORT12", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 137, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(138, "PORT13", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 138, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(139, "PORT14", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 139, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(140, "PORT15", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 140, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(141, "PORT16", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 141, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE, + 142, UNIPHIER_PIN_DRV_4_8, + 142, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(143, "MDC", 0, + 143, UNIPHIER_PIN_DRV_4_8, + 143, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(144, "MDIO", 0, + 144, UNIPHIER_PIN_DRV_4_8, + 144, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0, + 145, UNIPHIER_PIN_DRV_4_8, + 145, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0, + 146, UNIPHIER_PIN_DRV_4_8, + 146, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0, + 147, UNIPHIER_PIN_DRV_4_8, + 147, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0, + 148, UNIPHIER_PIN_DRV_4_8, + 148, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0, + 149, UNIPHIER_PIN_DRV_4_8, + 149, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0, + 150, UNIPHIER_PIN_DRV_4_8, + 150, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0, + 151, UNIPHIER_PIN_DRV_4_8, + 151, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0, + 152, UNIPHIER_PIN_DRV_4_8, + 152, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0, + 153, UNIPHIER_PIN_DRV_4_8, + 153, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0, + 154, UNIPHIER_PIN_DRV_4_8, + 154, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0, + 155, UNIPHIER_PIN_DRV_4_8, + 155, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0, + 156, UNIPHIER_PIN_DRV_4_8, + 156, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0, + 157, UNIPHIER_PIN_DRV_4_8, + 157, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0, + 158, UNIPHIER_PIN_DRV_4_8, + 158, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(159, "A_D_PCD00OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 159, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(160, "A_D_PCD01OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 160, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(161, "A_D_PCD02OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 161, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(162, "A_D_PCD03OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 162, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(163, "A_D_PCD04OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 163, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(164, "A_D_PCD05OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 164, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(165, "A_D_PCD06OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 165, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(166, "A_D_PCD07OUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 166, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(167, "A_D_PCD00IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 167, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(168, "A_D_PCD01IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 168, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(169, "A_D_PCD02IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 169, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(170, "A_D_PCD03IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 170, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(171, "A_D_PCD04IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 171, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(172, "A_D_PCD05IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 172, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(173, "A_D_PCD06IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 173, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(174, "A_D_PCD07IN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 174, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(175, "A_D_PCDNOE", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 175, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(176, "A_D_PC0READY", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 176, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(177, "A_D_PC0CD1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 177, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(178, "A_D_PC0CD2", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 178, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(179, "A_D_PC0WAIT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 179, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(180, "A_D_PC0RESET", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 180, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(181, "A_D_PC0CE1", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 181, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(182, "A_D_PC0WE", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 182, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(183, "A_D_PC0OE", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 183, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(184, "A_D_PC0IOWR", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 184, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(185, "A_D_PC0IORD", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 185, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(186, "A_D_PC0NOE", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 186, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(187, "A_D_HS0BCLKIN", 0, + 187, UNIPHIER_PIN_DRV_4_8, + 187, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(188, "A_D_HS0SYNCIN", 0, + 188, UNIPHIER_PIN_DRV_4_8, + 188, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(189, "A_D_HS0VALIN", 0, + 189, UNIPHIER_PIN_DRV_4_8, + 189, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(190, "A_D_HS0DIN0", 0, + 190, UNIPHIER_PIN_DRV_4_8, + 190, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(191, "A_D_HS0DIN1", 0, + 191, UNIPHIER_PIN_DRV_4_8, + 191, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(192, "A_D_HS0DIN2", 0, + 192, UNIPHIER_PIN_DRV_4_8, + 192, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(193, "A_D_HS0DIN3", 0, + 193, UNIPHIER_PIN_DRV_4_8, + 193, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(194, "A_D_HS0DIN4", 0, + 194, UNIPHIER_PIN_DRV_4_8, + 194, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(195, "A_D_HS0DIN5", 0, + 195, UNIPHIER_PIN_DRV_4_8, + 195, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(196, "A_D_HS0DIN6", 0, + 196, UNIPHIER_PIN_DRV_4_8, + 196, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(197, "A_D_HS0DIN7", 0, + 197, UNIPHIER_PIN_DRV_4_8, + 197, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(198, "A_D_AO1ARC", 0, + 198, UNIPHIER_PIN_DRV_4_8, + 198, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(199, "A_D_SPIXRST", UNIPHIER_PIN_IECTRL_NONE, + 199, UNIPHIER_PIN_DRV_4_8, + 199, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(200, "A_D_SPISCLK0", UNIPHIER_PIN_IECTRL_NONE, + 200, UNIPHIER_PIN_DRV_4_8, + 200, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(201, "A_D_SPITXD0", UNIPHIER_PIN_IECTRL_NONE, + 201, UNIPHIER_PIN_DRV_4_8, + 201, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(202, "A_D_SPIRXD0", UNIPHIER_PIN_IECTRL_NONE, + 202, UNIPHIER_PIN_DRV_4_8, + 202, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(203, "A_D_DMDCLK", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 203, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(204, "A_D_DMDPSYNC", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 204, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(205, "A_D_DMDVAL", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 205, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(206, "A_D_DMDDATA", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_8, + 206, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(207, "A_D_HDMIRXXIRQ", 0, + 207, UNIPHIER_PIN_DRV_4_8, + 207, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(208, "A_D_VBIXIRQ", 0, + 208, UNIPHIER_PIN_DRV_4_8, + 208, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(209, "A_D_HDMITXXIRQ", 0, + 209, UNIPHIER_PIN_DRV_4_8, + 209, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(210, "A_D_DMDIRQ", UNIPHIER_PIN_IECTRL_NONE, + 210, UNIPHIER_PIN_DRV_4_8, + 210, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(211, "A_D_SPICIRQ", UNIPHIER_PIN_IECTRL_NONE, + 211, UNIPHIER_PIN_DRV_4_8, + 211, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(212, "A_D_SPIBIRQ", UNIPHIER_PIN_IECTRL_NONE, + 212, UNIPHIER_PIN_DRV_4_8, + 212, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(213, "A_D_BESDAOUT", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 213, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(214, "A_D_BESDAIN", UNIPHIER_PIN_IECTRL_NONE, + -1, UNIPHIER_PIN_DRV_FIXED_4, + 214, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(215, "A_D_BESCLOUT", UNIPHIER_PIN_IECTRL_NONE, + 215, UNIPHIER_PIN_DRV_4_8, + 215, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(216, "A_D_VDACCLKOUT", 0, + 216, UNIPHIER_PIN_DRV_4_8, + 216, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(217, "A_D_VDACDOUT5", 0, + 217, UNIPHIER_PIN_DRV_4_8, + 217, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(218, "A_D_VDACDOUT6", 0, + 218, UNIPHIER_PIN_DRV_4_8, + 218, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(219, "A_D_VDACDOUT7", 0, + 219, UNIPHIER_PIN_DRV_4_8, + 219, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(220, "A_D_VDACDOUT8", 0, + 220, UNIPHIER_PIN_DRV_4_8, + 220, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(221, "A_D_VDACDOUT9", 0, + 221, UNIPHIER_PIN_DRV_4_8, + 221, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(222, "A_D_SIFBCKIN", 0, + 222, UNIPHIER_PIN_DRV_4_8, + 222, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(223, "A_D_SIFLRCKIN", 0, + 223, UNIPHIER_PIN_DRV_4_8, + 223, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(224, "A_D_SIFDIN", 0, + 224, UNIPHIER_PIN_DRV_4_8, + 224, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(225, "A_D_LIBCKOUT", 0, + 225, UNIPHIER_PIN_DRV_4_8, + 225, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(226, "A_D_LILRCKOUT", 0, + 226, UNIPHIER_PIN_DRV_4_8, + 226, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(227, "A_D_LIDIN", 0, + 227, UNIPHIER_PIN_DRV_4_8, + 227, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(228, "A_D_LODOUT", 0, + 228, UNIPHIER_PIN_DRV_4_8, + 228, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(229, "A_D_HPDOUT", 0, + 229, UNIPHIER_PIN_DRV_4_8, + 229, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(230, "A_D_MCLK", 0, + 230, UNIPHIER_PIN_DRV_4_8, + 230, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(231, "A_D_A2PLLREFOUT", 0, + 231, UNIPHIER_PIN_DRV_4_8, + 231, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(232, "A_D_HDMI3DSDAOUT", 0, + 232, UNIPHIER_PIN_DRV_4_8, + 232, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(233, "A_D_HDMI3DSDAIN", 0, + 233, UNIPHIER_PIN_DRV_4_8, + 233, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(234, "A_D_HDMI3DSCLIN", 0, + 234, UNIPHIER_PIN_DRV_4_8, + 234, UNIPHIER_PIN_PULL_DOWN), +}; + +static const unsigned adinter_pins[] = { + 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, + 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, + 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, + 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, + 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, + 229, 230, 231, 232, 233, 234, +}; +static const unsigned adinter_muxvals[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, +}; +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {109, 110}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {111, 112}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {115, 116}; +static const unsigned i2c2_muxvals[] = {1, 1}; +static const unsigned i2c3_pins[] = {118, 119}; +static const unsigned i2c3_muxvals[] = {1, 1}; +static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41, + 42, 43, 44, 45, 46}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {37, 38}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned uart0_pins[] = {135, 136}; +static const unsigned uart0_muxvals[] = {3, 3}; +static const unsigned uart0b_pins[] = {11, 12}; +static const unsigned uart0b_muxvals[] = {2, 2}; +static const unsigned uart1_pins[] = {115, 116}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart1b_pins[] = {113, 114}; +static const unsigned uart1b_muxvals[] = {1, 1}; +static const unsigned uart2_pins[] = {113, 114}; +static const unsigned uart2_muxvals[] = {2, 2}; +static const unsigned uart2b_pins[] = {86, 87}; +static const unsigned uart2b_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {56, 57}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {58, 59}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {60, 61}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned usb3_pins[] = {62, 63}; +static const unsigned usb3_muxvals[] = {0, 0}; +static const unsigned port_range0_pins[] = { + 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */ + 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */ + 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */ + 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */ + 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */ + 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */ + 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */ + 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */ + 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */ + 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */ +}; +static const unsigned port_range0_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ +}; +static const unsigned port_range1_pins[] = { + 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */ + 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */ + 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */ + 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */ + 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */ + 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */ + 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */ + 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */ + 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */ + 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */ + 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */ + 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */ + 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */ + 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */ + 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */ + 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */ + 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */ +}; +static const unsigned port_range1_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */ +}; +static const unsigned xirq_pins[] = { + 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */ + 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */ + 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */ +}; +static const unsigned xirq_muxvals[] = { + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ +}; + +static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { + UNIPHIER_PINCTRL_GROUP(adinter), + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart1b), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart2b), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88), + UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89), + UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90), + UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91), + UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92), + UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93), + UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94), + UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95), + UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96), + UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97), + UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98), + UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99), + UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100), + UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101), + UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102), + UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103), + UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104), + UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105), + UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106), + UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107), + UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108), + UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109), + UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110), + UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111), + UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112), + UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113), + UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114), + UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115), + UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116), + UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117), + UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118), + UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119), + UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120), + UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121), + UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122), + UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123), + UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124), + UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125), + UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126), + UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127), + UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128), + UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129), + UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130), + UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131), + UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132), + UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133), + UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134), + UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23), +}; + +static const char * const adinter_groups[] = {"adinter"}; +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const uart0_groups[] = {"uart0", "uart0b"}; +static const char * const uart1_groups[] = {"uart1", "uart1b"}; +static const char * const uart2_groups[] = {"uart2", "uart2b"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2"}; +static const char * const usb3_groups[] = {"usb3"}; +static const char * const port_groups[] = { + "port00", "port01", "port02", "port03", + "port04", "port05", "port06", "port07", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port20", "port21", "port22", "port23", + "port24", "port25", "port26", "port27", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port40", "port41", "port42", "port43", + "port44", "port45", "port46", "port47", + "port50", "port51", "port52", "port53", + "port54", "port55", "port56", "port57", + "port60", "port61", "port62", "port63", + "port64", "port65", "port66", "port67", + "port70", "port71", "port72", "port73", + "port74", "port75", "port76", "port77", + "port80", "port81", "port82", "port83", + "port84", "port85", "port86", "port87", + "port90", "port91", "port92", "port93", + "port94", "port95", "port96", "port97", + "port100", "port101", "port102", "port103", + "port104", "port105", "port106", "port107", + /* port110-117 missing */ + "port120", "port121", "port122", "port123", + "port124", "port125", "port126", "port127", + "port130", "port131", "port132", "port133", + "port134", "port135", "port136", "port137", + "port140", "port141", "port142", "port143", + "port144", "port145", "port146", "port147", + "port150", "port151", "port152", "port153", + "port154", "port155", "port156", "port157", + "port160", "port161", "port162", "port163", + "port164", "port165", "port166", "port167", + "port170", "port171", "port172", "port173", + "port174", "port175", "port176", "port177", + "port180", "port181", "port182", "port183", + "port184", "port185", "port186", "port187", + "port190", "port191", "port192", "port193", + "port194", "port195", "port196", "port197", + "port200", "port201", "port202", "port203", + "port204", "port205", "port206", "port207", + "port210", "port211", "port212", "port213", + "port214", "port215", "port216", "port217", + "port220", "port221", "port222", "port223", + "port224", "port225", "port226", "port227", + "port230", "port231", "port232", "port233", + "port234", "port235", "port236", "port237", + "port240", "port241", "port242", "port243", + "port244", "port245", "port246", "port247", + "port250", "port251", "port252", "port253", + "port254", "port255", "port256", "port257", + "port260", "port261", "port262", "port263", + "port264", "port265", "port266", "port267", + "port270", "port271", "port272", "port273", + "port274", "port275", "port276", "port277", + "port280", "port281", "port282", "port283", + "port284", "port285", "port286", "port287", +}; +static const char * const xirq_groups[] = { + "xirq0", "xirq1", "xirq2", "xirq3", + "xirq4", "xirq5", "xirq6", "xirq7", + "xirq8", "xirq9", "xirq10", "xirq11", + "xirq12", "xirq13", "xirq14", "xirq15", + "xirq16", "xirq17", "xirq18", "xirq19", + "xirq20", "xirq21", "xirq22", "xirq23", +}; + +static const struct uniphier_pinmux_function ph1_ld6b_functions[] = { + UNIPHIER_PINMUX_FUNCTION(adinter), /* Achip-Dchip interconnect */ + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(usb3), + UNIPHIER_PINMUX_FUNCTION(port), + UNIPHIER_PINMUX_FUNCTION(xirq), +}; + +static struct uniphier_pinctrl_socdata ph1_ld6b_pindata = { + .groups = ph1_ld6b_groups, + .groups_count = ARRAY_SIZE(ph1_ld6b_groups), + .functions = ph1_ld6b_functions, + .functions_count = ARRAY_SIZE(ph1_ld6b_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static struct pinctrl_desc ph1_ld6b_pinctrl_desc = { + .name = DRIVER_NAME, + .pins = ph1_ld6b_pins, + .npins = ARRAY_SIZE(ph1_ld6b_pins), + .owner = THIS_MODULE, +}; + +static int ph1_ld6b_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &ph1_ld6b_pinctrl_desc, + &ph1_ld6b_pindata); +} + +static const struct of_device_id ph1_ld6b_pinctrl_match[] = { + { .compatible = "socionext,ph1-ld6b-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ph1_ld6b_pinctrl_match); + +static struct platform_driver ph1_ld6b_pinctrl_driver = { + .probe = ph1_ld6b_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = ph1_ld6b_pinctrl_match, + }, +}; +module_platform_driver(ph1_ld6b_pinctrl_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier PH1-LD6b pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 95b612cc6c7f95f4e08f1b3dbc6588fda49b1b12 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 9 Jul 2015 10:55:01 +0900 Subject: pinctrl: move CONFIG_PINCTRL to drivers/Makefile Kbuild should descend into drivers/pinctrl/ only when CONFIG_PINCTRL is enabled because everything under that directory depends on CONFIG_PINCTRL. We can avoid the conditional, ifeq ($(CONFIG_OF),y) ... endif. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij --- drivers/Makefile | 2 +- drivers/pinctrl/Makefile | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index b64b49f6e01b..e4b260ecec15 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -11,7 +11,7 @@ obj-y += bus/ obj-$(CONFIG_GENERIC_PHY) += phy/ # GPIO must come after pinctrl as gpios may need to mux pins etc -obj-y += pinctrl/ +obj-$(CONFIG_PINCTRL) += pinctrl/ obj-y += gpio/ obj-y += pwm/ obj-$(CONFIG_PCI) += pci/ diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f6710a8a1503..76ba976cb9ca 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -2,12 +2,10 @@ subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG -obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o +obj-y += core.o pinctrl-utils.o obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o -ifeq ($(CONFIG_OF),y) -obj-$(CONFIG_PINCTRL) += devicetree.o -endif +obj-$(CONFIG_OF) += devicetree.o obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o -- cgit v1.2.3 From 8749f8ed5cc07f4f130f2e5b2c41da78388146ec Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 22 Jun 2015 18:12:24 +0300 Subject: pinctrl: samsung: don't truncate the last char We were allocating enough space because sizeof("-grp") and sizeof("-mux") are both equal to 5 but in the snprintf() we only allowed for 4 characters so the last 'p' and 'x' characters were truncated. The allocate and sprintf can be done in one step with the kasprintf(). Signed-off-by: Dan Carpenter Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-exynos5440.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index f5619fb50447..fa84db6a5b15 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -44,9 +44,7 @@ #define PIN_NAME_LENGTH 10 #define GROUP_SUFFIX "-grp" -#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) #define FUNCTION_SUFFIX "-mux" -#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) /* * pin configuration type and its value are packed together into a 16-bits. @@ -215,12 +213,11 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, * Allocate memory for pin group name. The pin group name is derived * from the node name from which these map entries are be created. */ - gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); + gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX); if (!gname) { dev_err(dev, "failed to alloc memory for group name\n"); goto free_map; } - snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); /* * don't have config options? then skip over to creating function @@ -254,13 +251,12 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, skip_cfgs: /* create the function map entry */ if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { - fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); + fname = kasprintf(GFP_KERNEL, + "%s%s", np->name, FUNCTION_SUFFIX); if (!fname) { dev_err(dev, "failed to alloc memory for func name\n"); goto free_cfg; } - snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, - FUNCTION_SUFFIX); map[*nmaps].data.mux.group = gname; map[*nmaps].data.mux.function = fname; @@ -710,14 +706,12 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, } /* derive pin group name from the node name */ - gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, - GFP_KERNEL); + gname = devm_kasprintf(dev, GFP_KERNEL, + "%s%s", cfg_np->name, GROUP_SUFFIX); if (!gname) { dev_err(dev, "failed to alloc memory for group name\n"); return -ENOMEM; } - snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, - GROUP_SUFFIX); grp->name = gname; grp->pins = pin_list; @@ -731,14 +725,12 @@ skip_to_pin_function: continue; /* derive function name from the node name */ - fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, - GFP_KERNEL); + fname = devm_kasprintf(dev, GFP_KERNEL, + "%s%s", cfg_np->name, FUNCTION_SUFFIX); if (!fname) { dev_err(dev, "failed to alloc memory for func name\n"); return -ENOMEM; } - snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, - FUNCTION_SUFFIX); func->name = fname; func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); -- cgit v1.2.3 From 583facb6ae27dfb4d0fb5a952dade5aa990a05c9 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 22 Jun 2015 18:13:15 +0300 Subject: pinctrl: samsung: remove "out of memory" messages Checkpatch.pl complains about these: WARNING: Possible unnecessary 'out of memory' message The messages use a little extra RAM and they add a few extra lines of code. We're probably never going to hit these out of memory situations but if we did then kmalloc() has pretty good error messages built-in. Signed-off-by: Dan Carpenter Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-exynos5440.c | 67 ++++++++-------------------- 1 file changed, 18 insertions(+), 49 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index fa84db6a5b15..5574b8ae5949 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -203,10 +203,8 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, /* Allocate memory for pin-map entries */ map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); - if (!map) { - dev_err(dev, "could not alloc memory for pin-maps\n"); + if (!map) return -ENOMEM; - } *nmaps = 0; /* @@ -214,10 +212,8 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, * from the node name from which these map entries are be created. */ gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX); - if (!gname) { - dev_err(dev, "failed to alloc memory for group name\n"); + if (!gname) goto free_map; - } /* * don't have config options? then skip over to creating function @@ -228,10 +224,8 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, /* Allocate memory for config entries */ cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); - if (!cfg) { - dev_err(dev, "failed to alloc memory for configs\n"); + if (!cfg) goto free_gname; - } /* Prepare a list of config settings */ for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { @@ -253,10 +247,8 @@ skip_cfgs: if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { fname = kasprintf(GFP_KERNEL, "%s%s", np->name, FUNCTION_SUFFIX); - if (!fname) { - dev_err(dev, "failed to alloc memory for func name\n"); + if (!fname) goto free_cfg; - } map[*nmaps].data.mux.group = gname; map[*nmaps].data.mux.function = fname; @@ -647,10 +639,8 @@ static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, } *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); - if (!*pin_list) { - dev_err(dev, "failed to allocate memory for pin list\n"); + if (!*pin_list) return -ENOMEM; - } return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", *pin_list, *npins); @@ -678,17 +668,15 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, return -EINVAL; groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); - if (!groups) { - dev_err(dev, "failed allocate memory for ping group list\n"); + if (!groups) return -EINVAL; - } + grp = groups; functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); - if (!functions) { - dev_err(dev, "failed to allocate memory for function list\n"); + if (!functions) return -EINVAL; - } + func = functions; /* @@ -708,10 +696,8 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, /* derive pin group name from the node name */ gname = devm_kasprintf(dev, GFP_KERNEL, "%s%s", cfg_np->name, GROUP_SUFFIX); - if (!gname) { - dev_err(dev, "failed to alloc memory for group name\n"); + if (!gname) return -ENOMEM; - } grp->name = gname; grp->pins = pin_list; @@ -727,18 +713,13 @@ skip_to_pin_function: /* derive function name from the node name */ fname = devm_kasprintf(dev, GFP_KERNEL, "%s%s", cfg_np->name, FUNCTION_SUFFIX); - if (!fname) { - dev_err(dev, "failed to alloc memory for func name\n"); + if (!fname) return -ENOMEM; - } func->name = fname; func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); - if (!func->groups) { - dev_err(dev, "failed to alloc memory for group list " - "in pin function"); + if (!func->groups) return -ENOMEM; - } func->groups[0] = gname; func->num_groups = gname ? 1 : 0; func->function = function; @@ -766,10 +747,8 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev, int pin, ret; ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); - if (!ctrldesc) { - dev_err(dev, "could not allocate memory for pinctrl desc\n"); + if (!ctrldesc) return -ENOMEM; - } ctrldesc->name = "exynos5440-pinctrl"; ctrldesc->owner = THIS_MODULE; @@ -779,10 +758,8 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev, pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * EXYNOS5440_MAX_PINS, GFP_KERNEL); - if (!pindesc) { - dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); + if (!pindesc) return -ENOMEM; - } ctrldesc->pins = pindesc; ctrldesc->npins = EXYNOS5440_MAX_PINS; @@ -796,10 +773,8 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev, */ pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * ctrldesc->npins, GFP_KERNEL); - if (!pin_names) { - dev_err(&pdev->dev, "mem alloc for pin names failed\n"); + if (!pin_names) return -ENOMEM; - } /* for each pin, set the name of the pin */ for (pin = 0; pin < ctrldesc->npins; pin++) { @@ -836,10 +811,8 @@ static int exynos5440_gpiolib_register(struct platform_device *pdev, int ret; gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); - if (!gc) { - dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n"); + if (!gc) return -ENOMEM; - } priv->gc = gc; gc->base = 0; @@ -941,10 +914,8 @@ static int exynos5440_gpio_irq_init(struct platform_device *pdev, intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, GFP_KERNEL); - if (!intd) { - dev_err(dev, "failed to allocate memory for gpio intr data\n"); + if (!intd) return -ENOMEM; - } for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { irq = irq_of_parse_and_map(dev->of_node, i); @@ -987,10 +958,8 @@ static int exynos5440_pinctrl_probe(struct platform_device *pdev) } priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - dev_err(dev, "could not allocate memory for private data\n"); + if (!priv) return -ENOMEM; - } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->reg_base = devm_ioremap_resource(&pdev->dev, res); -- cgit v1.2.3 From 16ccaf5bb5a52372bfebd3dfbb79dd810ad49c09 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 30 Jun 2015 11:29:57 +0300 Subject: pinctrl: sh-pfc: Accept standard function, pins and groups properties The "function", "pins" and "groups" pinmux and pinctrl properties have been standardized. Support them in addition to the custom "renesas,*" properties. New-style and old-style properties can't be mixed in DT. Signed-off-by: Laurent Pinchart Signed-off-by: Linus Walleij --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 20 +++++------ drivers/pinctrl/sh-pfc/pinctrl.c | 42 +++++++++++++++++----- 2 files changed, 44 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 51cee44fc140..e089142cfb14 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -58,12 +58,12 @@ are parsed through phandles and processed purely based on their content. Pin Configuration Node Properties: -- renesas,pins : An array of strings, each string containing the name of a pin. -- renesas,groups : An array of strings, each string containing the name of a pin +- pins : An array of strings, each string containing the name of a pin. +- groups : An array of strings, each string containing the name of a pin group. -- renesas,function: A string containing the name of the function to mux to the - pin group(s) specified by the renesas,groups property +- function: A string containing the name of the function to mux to the pin + group(s) specified by the groups property. Valid values for pin, group and function names can be found in the group and function arrays of the PFC data file corresponding to the SoC @@ -141,19 +141,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps mmcif_pins: mmcif { mux { - renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; - renesas,function = "mmc0"; + groups = "mmc0_data8_0", "mmc0_ctrl_0"; + function = "mmc0"; }; cfg { - renesas,groups = "mmc0_data8_0"; - renesas,pins = "PORT279"; + groups = "mmc0_data8_0"; + pins = "PORT279"; bias-pull-up; }; }; scifa4_pins: scifa4 { - renesas,groups = "scifa4_data", "scifa4_ctrl"; - renesas,function = "scifa4"; + groups = "scifa4_data", "scifa4_ctrl"; + function = "scifa4"; }; }; diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index ff678966008b..6fe7459f0ccb 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -40,6 +40,10 @@ struct sh_pfc_pinctrl { struct pinctrl_pin_desc *pins; struct sh_pfc_pin_config *configs; + + const char *func_prop_name; + const char *groups_prop_name; + const char *pins_prop_name; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) @@ -96,10 +100,13 @@ static int sh_pfc_map_add_config(struct pinctrl_map *map, return 0; } -static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, +static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps, unsigned int *index) { + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pmx->pfc->dev; struct pinctrl_map *maps = *map; unsigned int nmaps = *num_maps; unsigned int idx = *index; @@ -113,10 +120,27 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, const char *pin; int ret; + /* Support both the old Renesas-specific properties and the new standard + * properties. Mixing old and new properties isn't allowed, neither + * inside a subnode nor across subnodes. + */ + if (!pmx->func_prop_name) { + if (of_find_property(np, "groups", NULL) || + of_find_property(np, "pins", NULL)) { + pmx->func_prop_name = "function"; + pmx->groups_prop_name = "groups"; + pmx->pins_prop_name = "pins"; + } else { + pmx->func_prop_name = "renesas,function"; + pmx->groups_prop_name = "renesas,groups"; + pmx->pins_prop_name = "renesas,pins"; + } + } + /* Parse the function and configuration properties. At least a function * or one configuration must be specified. */ - ret = of_property_read_string(np, "renesas,function", &function); + ret = of_property_read_string(np, pmx->func_prop_name, &function); if (ret < 0 && ret != -EINVAL) { dev_err(dev, "Invalid function in DT\n"); return ret; @@ -129,11 +153,12 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, if (!function && num_configs == 0) { dev_err(dev, "DT node must contain at least a function or config\n"); + ret = -ENODEV; goto done; } /* Count the number of pins and groups and reallocate mappings. */ - ret = of_property_count_strings(np, "renesas,pins"); + ret = of_property_count_strings(np, pmx->pins_prop_name); if (ret == -EINVAL) { num_pins = 0; } else if (ret < 0) { @@ -143,7 +168,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, num_pins = ret; } - ret = of_property_count_strings(np, "renesas,groups"); + ret = of_property_count_strings(np, pmx->groups_prop_name); if (ret == -EINVAL) { num_groups = 0; } else if (ret < 0) { @@ -174,7 +199,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, *num_maps = nmaps; /* Iterate over pins and groups and create the mappings. */ - of_property_for_each_string(np, "renesas,groups", prop, group) { + of_property_for_each_string(np, pmx->groups_prop_name, prop, group) { if (function) { maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; maps[idx].data.mux.group = group; @@ -198,7 +223,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, goto done; } - of_property_for_each_string(np, "renesas,pins", prop, pin) { + of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { ret = sh_pfc_map_add_config(&maps[idx], pin, PIN_MAP_TYPE_CONFIGS_PIN, configs, num_configs); @@ -246,7 +271,7 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, index = 0; for_each_child_of_node(np, child) { - ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps, + ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, &index); if (ret < 0) goto done; @@ -254,7 +279,8 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, /* If no mapping has been found in child nodes try the config node. */ if (*num_maps == 0) { - ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index); + ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, + &index); if (ret < 0) goto done; } -- cgit v1.2.3 From c7977ec4a33633c8e8d9267dd014356cf857351c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jun 2015 11:39:53 +0200 Subject: pinctrl: sh-pfc: Convert to platform_get_*() If the pin function controller (which can be a GPIO controller) is instantiated before the interrupt controllers, due to the ordering in the DTS, the irq domains for the interrupt controllers referenced by its "interrupts-extended" property cannot be found yet: irq: no irq domain found for /interrupt-controller@e61c0000 ! As the sh-pfc driver accesses the platform device's resources directly, it cannot find the (optional) IRQ resources, and thinks no interrupts are available. This may lead to failures later, when GPIOs are used as interupts: gpio-keys keyboard: Unable to claim irq 0; error -22 gpio-keys: probe of keyboard failed with error -22 To fix this, add support for deferred probing to sh-pfc, by converting the driver from direct platform device resource access to using the platform_get_resource() and platform_get_irq() helpers. Note that while this fixes the root cause worked around by commit e4ba0a9bddff3ba5 ("ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug"), I strongly recommend against reverting the workaround now, as this would lead to lots of probe deferrals in drivers relying on pinctrl. This may be reconsidered once the DT code starts taking into account phandle dependencies during device instantation. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 46 ++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 865d235612c5..979623895904 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -29,24 +29,25 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc, struct platform_device *pdev) { - unsigned int num_windows = 0; - unsigned int num_irqs = 0; + unsigned int num_windows, num_irqs; struct sh_pfc_window *windows; unsigned int *irqs = NULL; struct resource *res; unsigned int i; + int irq; /* Count the MEM and IRQ resources. */ - for (i = 0; i < pdev->num_resources; ++i) { - switch (resource_type(&pdev->resource[i])) { - case IORESOURCE_MEM: - num_windows++; + for (num_windows = 0;; num_windows++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); + if (!res) break; - - case IORESOURCE_IRQ: - num_irqs++; + } + for (num_irqs = 0;; num_irqs++) { + irq = platform_get_irq(pdev, num_irqs); + if (irq == -EPROBE_DEFER) + return irq; + if (irq < 0) break; - } } if (num_windows == 0) @@ -72,22 +73,17 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc, } /* Fill them. */ - for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) { - switch (resource_type(res)) { - case IORESOURCE_MEM: - windows->phys = res->start; - windows->size = resource_size(res); - windows->virt = devm_ioremap_resource(pfc->dev, res); - if (IS_ERR(windows->virt)) - return -ENOMEM; - windows++; - break; - - case IORESOURCE_IRQ: - *irqs++ = res->start; - break; - } + for (i = 0; i < num_windows; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + windows->phys = res->start; + windows->size = resource_size(res); + windows->virt = devm_ioremap_resource(pfc->dev, res); + if (IS_ERR(windows->virt)) + return -ENOMEM; + windows++; } + for (i = 0; i < num_irqs; i++) + *irqs++ = platform_get_irq(pdev, i); return 0; } -- cgit v1.2.3 From 9f21c67da6a62aa082a1f20feb983ab5ed89a915 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jul 2015 13:56:52 +0200 Subject: pinctrl: sh-pfc: sh73a0: Remove obsolete multi-platform check Since the removal of the sh73a0 legacy SoC code in commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code for SH-Mobile AG5"), sh73a0 is only supported in generic ARM multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set, and the check can be removed. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index d2efbfb776ac..097526576f88 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_ARCH_MULTIPLATFORM -#include -#endif - #include "core.h" #include "sh_pfc.h" -- cgit v1.2.3 From 39ad6ff12cd54607b64642562ad850bb09176734 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jul 2015 13:56:53 +0200 Subject: pinctrl: sh-pfc: Remove obsolete sh73a0 platform_device_id entry Since the removal of the sh73a0 legacy SoC code in commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code for SH-Mobile AG5"), sh73a0 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 979623895904..23b2b3be26fd 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -605,9 +605,6 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_SH7269 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, #endif -#ifdef CONFIG_PINCTRL_PFC_SH73A0 - { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_SH7720 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, #endif -- cgit v1.2.3 From d009fa3b2b28b28f58920aaa76fa0abeb573828c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jul 2015 13:56:54 +0200 Subject: pinctrl: sh-pfc: r8a7740: Remove obsolete multi-platform check Since the removal of the r8a7740 legacy SoC code in commit 44d88c754e57a6d9 ("ARM: shmobile: Remove legacy SoC code for R-Mobile A1"), r8a7740 is only supported in generic ARM multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set, and the check can be removed. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index d0bb1459783a..82ef1862dd1b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -22,10 +22,6 @@ #include #include -#ifndef CONFIG_ARCH_MULTIPLATFORM -#include -#endif - #include "core.h" #include "sh_pfc.h" -- cgit v1.2.3 From 03c42c3e5216e2777f8ae819d6a076e94dcdfbdd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jul 2015 13:56:55 +0200 Subject: pinctrl: sh-pfc: Remove obsolete r8a7740 platform_device_id entry Since the removal of the r8a7740 legacy SoC code in commit 44d88c754e57a6d9 ("ARM: shmobile: Remove legacy SoC code for R-Mobile A1"), r8a7740 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 23b2b3be26fd..fb9c44805234 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -587,9 +587,6 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { -#ifdef CONFIG_PINCTRL_PFC_R8A7740 - { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_R8A7778 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, #endif -- cgit v1.2.3 From 6417049f662d85a6f3a6b7cb8bc98bae3edae0a4 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 6 Jul 2015 18:11:50 +0300 Subject: pinctrl: single: dra7: remove PCS_QUIRK_SHARED_IRQ On DRA7 there is one pinctrl domain (dra7_pmx_core) and PRCM wake-up IRQ is not shared, so remove quirk. Cc: Nishanth Menon Fixes: 31320beaa3d3 ('pinctrl: single: Add DRA7 pinctrl compatibility') Signed-off-by: Grygorii Strashko Acked-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b2de09d3b1a0..1cd085d92147 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1982,7 +1982,6 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = { }; static const struct pcs_soc_data pinctrl_single_dra7 = { - .flags = PCS_QUIRK_SHARED_IRQ, .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ }; -- cgit v1.2.3 From e3f3aaac06657e6fc834e217ae450f51a6e0968c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Jul 2015 15:27:30 +0900 Subject: pinctrl: sirf: Drop owner assignment from platform_driver platform_driver does not need to set an owner because platform_driver_register() will set it. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas7.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 9384e0aa3996..d6e80fe1c7f7 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -4621,7 +4621,6 @@ failed: static struct platform_driver atlas7_gpio_driver = { .driver = { .name = "atlas7-gpio", - .owner = THIS_MODULE, .of_match_table = atlas7_gpio_ids, }, .probe = atlas7_gpio_probe, -- cgit v1.2.3 From ad64498762dd6f262f8c7c37926cd56693e109ba Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 6 Jul 2015 18:09:30 -0700 Subject: pinctrl: qcom: Hook pm_power_down for shutdown support Assign pm_power_off() if we have the PS_HOLD functionality so that we can properly shutdown the SoC. Otherwise, shutdown won't do anything besides put the CPU into a tight loop. Unfortunately, we have to use a singleton here because pm_power_off() doesn't take any arguments. Fortunately there's only one instance of the pinctrl device on a running system so this isn't a problem. Cc: Pramod Gurav Signed-off-by: Stephen Boyd Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e457d52302a2..6242af8a42d5 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "../core.h" #include "../pinconf.h" @@ -855,6 +856,13 @@ static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, return NOTIFY_DONE; } +static struct msm_pinctrl *poweroff_pctrl; + +static void msm_ps_hold_poweroff(void) +{ + msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); +} + static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) { int i; @@ -867,6 +875,8 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) if (register_restart_handler(&pctrl->restart_nb)) dev_err(pctrl->dev, "failed to setup restart handler.\n"); + poweroff_pctrl = pctrl; + pm_power_off = msm_ps_hold_poweroff; break; } } -- cgit v1.2.3 From 75629981069cf194336426bbbfb03f9c93d7ad67 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 14 Jul 2015 11:17:58 +0100 Subject: pinctrl: pinconf: Allow groups to be configured via debugfs The function pinconf_dbg_config_write() currently only supports configuring a pin configuration mapping via the debugfs. Allow group mappings to also be configured via the debugfs. Signed-off-by: Jon Hunter Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 1fc09dc20199..4744d6363dfb 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -470,10 +470,12 @@ exit: * pinconf_dbg_config_write() - modify the pinctrl config in the pinctrl * map, of a dev/pin/state entry based on user entries to pinconf-config * @user_buf: contains the modification request with expected format: - * modify config_pin + * modify * modify is literal string, alternatives like add/delete not supported yet - * config_pin is literal, alternatives like config_mux not supported yet - * are values that should match the pinctrl-maps + * is the configuration to be changed. Supported configs are + * "config_pin" or "config_group", alternatives like config_mux are not + * supported yet. + * are values that should match the pinctrl-maps * reflects the new config and is driver dependant */ static ssize_t pinconf_dbg_config_write(struct file *file, @@ -511,13 +513,19 @@ static ssize_t pinconf_dbg_config_write(struct file *file, if (strcmp(token, "modify")) return -EINVAL; - /* Get arg type: "config_pin" type supported so far */ + /* + * Get arg type: "config_pin" and "config_group" + * types are supported so far + */ token = strsep(&b, " "); if (!token) return -EINVAL; - if (strcmp(token, "config_pin")) + if (!strcmp(token, "config_pin")) + dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN; + else if (!strcmp(token, "config_group")) + dbg->map_type = PIN_MAP_TYPE_CONFIGS_GROUP; + else return -EINVAL; - dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN; /* get arg 'device_name' */ token = strsep(&b, " "); -- cgit v1.2.3 From d96310aeddc692cf1f06861cf722c4843e0a3f28 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 14 Jul 2015 11:17:59 +0100 Subject: pinctrl: pinconf: Fix display of configs The function pinconf_dbg_config_print() only prints the configuration of the 1st pin config in an array of pin configurations. Fix this so that all pin configurations in the array are displayed. There are a few places in the code where the pin configs are displayed and so add a helper function to display the pin configs to simplify the code. Signed-off-by: Jon Hunter Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf.c | 64 ++++++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 4744d6363dfb..cbf26a6992a0 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -202,18 +202,34 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) #ifdef CONFIG_DEBUG_FS -void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) +void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, + unsigned long *configs, unsigned num_configs) { - struct pinctrl_dev *pctldev; const struct pinconf_ops *confops; int i; - pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); if (pctldev) confops = pctldev->desc->confops; else confops = NULL; + for (i = 0; i < num_configs; i++) { + seq_puts(s, "config "); + if (confops && confops->pin_config_config_dbg_show) + confops->pin_config_config_dbg_show(pctldev, s, + configs[i]); + else + seq_printf(s, "%08lx", configs[i]); + seq_puts(s, "\n"); + } +} + +void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) +{ + struct pinctrl_dev *pctldev; + + pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); + switch (map->type) { case PIN_MAP_TYPE_CONFIGS_PIN: seq_printf(s, "pin "); @@ -227,15 +243,8 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) seq_printf(s, "%s\n", map->data.configs.group_or_pin); - for (i = 0; i < map->data.configs.num_configs; i++) { - seq_printf(s, "config "); - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, - map->data.configs.configs[i]); - else - seq_printf(s, "%08lx", map->data.configs.configs[i]); - seq_printf(s, "\n"); - } + pinconf_show_config(s, pctldev, map->data.configs.configs, + map->data.configs.num_configs); } void pinconf_show_setting(struct seq_file *s, @@ -243,9 +252,7 @@ void pinconf_show_setting(struct seq_file *s, { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - const struct pinconf_ops *confops = pctldev->desc->confops; struct pin_desc *desc; - int i; switch (setting->type) { case PIN_MAP_TYPE_CONFIGS_PIN: @@ -269,17 +276,8 @@ void pinconf_show_setting(struct seq_file *s, * FIXME: We should really get the pin controler to dump the config * values, so they can be decoded to something meaningful. */ - for (i = 0; i < setting->data.configs.num_configs; i++) { - seq_printf(s, " "); - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, - setting->data.configs.configs[i]); - else - seq_printf(s, "%08lx", - setting->data.configs.configs[i]); - } - - seq_printf(s, "\n"); + pinconf_show_config(s, pctldev, setting->data.configs.configs, + setting->data.configs.num_configs); } static void pinconf_dump_pin(struct pinctrl_dev *pctldev, @@ -412,10 +410,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) const struct pinctrl_map *map; const struct pinctrl_map *found = NULL; struct pinctrl_dev *pctldev; - const struct pinconf_ops *confops = NULL; struct dbg_cfg *dbg = &pinconf_dbg_conf; int i, j; - unsigned long config; mutex_lock(&pinctrl_maps_mutex); @@ -449,16 +445,10 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) } pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name); - config = *found->data.configs.configs; - seq_printf(s, "Dev %s has config of %s in state %s: 0x%08lX\n", - dbg->dev_name, dbg->pin_name, - dbg->state_name, config); - - if (pctldev) - confops = pctldev->desc->confops; - - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, config); + seq_printf(s, "Dev %s has config of %s in state %s:\n", + dbg->dev_name, dbg->pin_name, dbg->state_name); + pinconf_show_config(s, pctldev, found->data.configs.configs, + found->data.configs.num_configs); exit: mutex_unlock(&pinctrl_maps_mutex); -- cgit v1.2.3 From bd6eab90073814a3211fc9688c2d59ce369ccff2 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Wed, 15 Jul 2015 00:25:27 +0200 Subject: pinctrl: lpc18xx: add support for usb1 pinconf The dedicated USB1 pins can be configured with pull-down and for low power mode (suspend). Add support for this in the pinctrl driver. Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-lpc18xx.c | 54 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index ef0b697639a7..e56f9203cc87 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -37,6 +37,9 @@ #define LPC18XX_SCU_PIN_EHD_MASK 0x300 #define LPC18XX_SCU_PIN_EHD_POS 8 +#define LPC18XX_SCU_USB1_EPD BIT(2) +#define LPC18XX_SCU_USB1_EPWR BIT(4) + #define LPC18XX_SCU_I2C0_EFP BIT(0) #define LPC18XX_SCU_I2C0_EHD BIT(2) #define LPC18XX_SCU_I2C0_EZI BIT(3) @@ -617,8 +620,31 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = { static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg) { - /* TODO */ - return -ENOTSUPP; + switch (param) { + case PIN_CONFIG_LOW_POWER_MODE: + if (reg & LPC18XX_SCU_USB1_EPWR) + *arg = 0; + else + *arg = 1; + break; + + case PIN_CONFIG_BIAS_DISABLE: + if (reg & LPC18XX_SCU_USB1_EPD) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (reg & LPC18XX_SCU_USB1_EPD) + *arg = 1; + else + return -EINVAL; + break; + + default: + return -ENOTSUPP; + } + + return 0; } static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg, @@ -782,8 +808,28 @@ static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev, enum pin_config_param param, u16 param_val, u32 *reg) { - /* TODO */ - return -ENOTSUPP; + switch (param) { + case PIN_CONFIG_LOW_POWER_MODE: + if (param_val) + *reg &= ~LPC18XX_SCU_USB1_EPWR; + else + *reg |= LPC18XX_SCU_USB1_EPWR; + break; + + case PIN_CONFIG_BIAS_DISABLE: + *reg &= ~LPC18XX_SCU_USB1_EPD; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + *reg |= LPC18XX_SCU_USB1_EPD; + break; + + default: + dev_err(pctldev->dev, "Property not supported\n"); + return -ENOTSUPP; + } + + return 0; } static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev, -- cgit v1.2.3 From 099f3e4adddc8fe9899fb879053887a95e9aed7d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 14 Jul 2015 23:40:33 -0700 Subject: pinctrl: qcom: spmi-mpp: Add support for setting analog output level When the MPP is configured for analog output the output level is selected by the AOUT_CTL register, this patch makes it possible to control this. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 7 +++++++ drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 23 ++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index d29fb96a57d3..0e4d4e62e220 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -127,6 +127,13 @@ to specify in a pin configuration subnode: Definition: Selects the power source for the specified pins. Valid power sources are defined in +- qcom,analog-level: + Usage: optional + Value type: + Definition: Selects the source for analog output. Valued values are + defined in + PMIC_MPP_AOUT_LVL_* + - qcom,analog-mode: Usage: optional Value type: diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 9dde023640ba..e52a72348a67 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -61,6 +61,7 @@ #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 #define PMIC_MPP_REG_DIG_IN_CTL 0x43 #define PMIC_MPP_REG_EN_CTL 0x46 +#define PMIC_MPP_REG_AOUT_CTL 0x48 #define PMIC_MPP_REG_AIN_CTL 0x4a #define PMIC_MPP_REG_SINK_CTL 0x4c @@ -100,6 +101,7 @@ #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) #define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2) #define PMIC_MPP_CONF_SINK_MODE (PIN_CONFIG_END + 3) +#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 4) /** * struct pmic_mpp_pad - keep current MPP settings @@ -115,6 +117,7 @@ * @num_sources: Number of power-sources supported by this MPP. * @power_source: Current power-source used. * @amux_input: Set the source for analog input. + * @aout_level: Analog output level * @pullup: Pullup resistor value. Valid in Bidirectional mode only. * @function: See pmic_mpp_functions[]. * @drive_strength: Amount of current in sink mode @@ -131,6 +134,7 @@ struct pmic_mpp_pad { unsigned int num_sources; unsigned int power_source; unsigned int amux_input; + unsigned int aout_level; unsigned int pullup; unsigned int function; unsigned int drive_strength; @@ -145,6 +149,7 @@ struct pmic_mpp_state { static const struct pinconf_generic_params pmic_mpp_bindings[] = { {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, + {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE, 0}, {"qcom,sink-mode", PMIC_MPP_CONF_SINK_MODE, 0}, }; @@ -152,6 +157,7 @@ static const struct pinconf_generic_params pmic_mpp_bindings[] = { #ifdef CONFIG_DEBUG_FS static const struct pin_config_item pmic_conf_items[] = { PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), + PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), PCONFDUMP(PMIC_MPP_CONF_ANALOG_MODE, "analog output", NULL, false), PCONFDUMP(PMIC_MPP_CONF_SINK_MODE, "sink mode", NULL, false), }; @@ -358,6 +364,9 @@ static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: arg = pad->drive_strength; break; + case PMIC_MPP_CONF_ANALOG_LEVEL: + arg = pad->aout_level; + break; case PMIC_MPP_CONF_ANALOG_MODE: arg = pad->analog_mode; break; @@ -433,6 +442,9 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; pad->amux_input = arg; break; + case PMIC_MPP_CONF_ANALOG_LEVEL: + pad->aout_level = arg; + break; case PMIC_MPP_CONF_ANALOG_MODE: pad->analog_mode = !!arg; break; @@ -462,6 +474,10 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, if (ret < 0) return ret; + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); + if (ret < 0) + return ret; + ret = pmic_mpp_write_mode_ctl(state, pad); if (ret < 0) return ret; @@ -507,6 +523,7 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, " %-7s", modes[pad->analog_mode ? 1 : (pad->sink_mode ? 2 : 0)]); seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); seq_printf(s, " vin-%d", pad->power_source); + seq_printf(s, " %d", pad->aout_level); seq_printf(s, " %-8s", biases[pad->pullup]); seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); } @@ -748,6 +765,12 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, pad->drive_strength = val; + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); + if (val < 0) + return val; + + pad->aout_level = val; + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); if (val < 0) return val; -- cgit v1.2.3 From eb5c144cbbc0ca9bb9a77c7c83fddc87469318de Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 17 Jun 2015 23:47:30 -0700 Subject: pinctrl: qcom: spmi-mpp: Transpose pinmux function The "function" of the MPP driver was inherited from the GPIO driver, but the differences between the two hardware blocks makes both the driver and the device tree binding to be awkward. Instead of overloading the "normal" function with various modes this patch transposes the pinmux function to represent the three operating modes of the MPP (digital, analog and current sink). The properties of pin pairing and DTEST routing is moved to separate properties. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 29 ++-- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 157 ++++++++++++--------- 2 files changed, 99 insertions(+), 87 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index 0e4d4e62e220..b096d8351b8f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -77,12 +77,9 @@ to specify in a pin configuration subnode: Value type: Definition: Specify the alternative function to be configured for the specified pins. Valid values are: - "normal", - "paired", - "dtest1", - "dtest2", - "dtest3", - "dtest4" + "digital", + "analog", + "sink" - bias-disable: Usage: optional @@ -134,17 +131,11 @@ to specify in a pin configuration subnode: defined in PMIC_MPP_AOUT_LVL_* -- qcom,analog-mode: +- qcom,dtest: Usage: optional - Value type: - Definition: Selects Analog mode of operation: combined with input-enable - and/or output-high, output-low MPP could operate as - Bidirectional Logic, Analog Input, Analog Output. - -- qcom,sink-mode: - Usage: optional - Value type: or - Definition: Selects sink mode of operation + Value type: + Definition: Selects which dtest rail to be routed in the various functions. + Valid values are 1-4 - qcom,amux-route: Usage: optional @@ -152,6 +143,10 @@ to specify in a pin configuration subnode: Definition: Selects the source for analog input. Valid values are defined in PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... +- qcom,paired: + Usage: optional + Value type: + Definition: Indicates that the pin should be operating in paired mode. Example: @@ -168,7 +163,7 @@ Example: pm8841_default: default { gpio { pins = "mpp1", "mpp2", "mpp3", "mpp4"; - function = "normal"; + function = "digital"; input-enable; power-source = ; }; diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index e52a72348a67..e3be3ce2cada 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -95,13 +95,17 @@ #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 #define PMIC_MPP_MODE_CURRENT_SINK 6 +#define PMIC_MPP_SELECTOR_NORMAL 0 +#define PMIC_MPP_SELECTOR_PAIRED 1 +#define PMIC_MPP_SELECTOR_DTEST_FIRST 4 + #define PMIC_MPP_PHYSICAL_OFFSET 1 /* Qualcomm specific pin configurations */ #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) -#define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2) -#define PMIC_MPP_CONF_SINK_MODE (PIN_CONFIG_END + 3) -#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 4) +#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) +#define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) +#define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) /** * struct pmic_mpp_pad - keep current MPP settings @@ -111,9 +115,7 @@ * @out_value: Cached pin output value. * @output_enabled: Set to true if MPP output logic is enabled. * @input_enabled: Set to true if MPP input buffer logic is enabled. - * @analog_mode: Set to true when MPP should operate in Analog Input, Analog - * Output or Bidirectional Analog mode. - * @sink_mode: Boolean indicating if ink mode is slected + * @paired: Pin operates in paired mode * @num_sources: Number of power-sources supported by this MPP. * @power_source: Current power-source used. * @amux_input: Set the source for analog input. @@ -121,6 +123,7 @@ * @pullup: Pullup resistor value. Valid in Bidirectional mode only. * @function: See pmic_mpp_functions[]. * @drive_strength: Amount of current in sink mode + * @dtest: DTEST route selector */ struct pmic_mpp_pad { u16 base; @@ -129,8 +132,7 @@ struct pmic_mpp_pad { bool out_value; bool output_enabled; bool input_enabled; - bool analog_mode; - bool sink_mode; + bool paired; unsigned int num_sources; unsigned int power_source; unsigned int amux_input; @@ -138,6 +140,7 @@ struct pmic_mpp_pad { unsigned int pullup; unsigned int function; unsigned int drive_strength; + unsigned int dtest; }; struct pmic_mpp_state { @@ -150,16 +153,16 @@ struct pmic_mpp_state { static const struct pinconf_generic_params pmic_mpp_bindings[] = { {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, - {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE, 0}, - {"qcom,sink-mode", PMIC_MPP_CONF_SINK_MODE, 0}, + {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, + {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, }; #ifdef CONFIG_DEBUG_FS static const struct pin_config_item pmic_conf_items[] = { PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), - PCONFDUMP(PMIC_MPP_CONF_ANALOG_MODE, "analog output", NULL, false), - PCONFDUMP(PMIC_MPP_CONF_SINK_MODE, "sink mode", NULL, false), + PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), + PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), }; #endif @@ -167,11 +170,12 @@ static const char *const pmic_mpp_groups[] = { "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", }; +#define PMIC_MPP_DIGITAL 0 +#define PMIC_MPP_ANALOG 1 +#define PMIC_MPP_SINK 2 + static const char *const pmic_mpp_functions[] = { - PMIC_MPP_FUNC_NORMAL, PMIC_MPP_FUNC_PAIRED, - "reserved1", "reserved2", - PMIC_MPP_FUNC_DTEST1, PMIC_MPP_FUNC_DTEST2, - PMIC_MPP_FUNC_DTEST3, PMIC_MPP_FUNC_DTEST4, + "digital", "analog", "sink" }; static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip) @@ -260,31 +264,46 @@ static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, struct pmic_mpp_pad *pad) { + unsigned int mode; + unsigned int sel; unsigned int val; - - if (pad->analog_mode) { - val = PMIC_MPP_MODE_ANALOG_INPUT; - if (pad->output_enabled) { - if (pad->input_enabled) - val = PMIC_MPP_MODE_ANALOG_BIDIR; - else - val = PMIC_MPP_MODE_ANALOG_OUTPUT; - } - } else if (pad->sink_mode) { - val = PMIC_MPP_MODE_CURRENT_SINK; - } else { - val = PMIC_MPP_MODE_DIGITAL_INPUT; - if (pad->output_enabled) { - if (pad->input_enabled) - val = PMIC_MPP_MODE_DIGITAL_BIDIR; - else - val = PMIC_MPP_MODE_DIGITAL_OUTPUT; - } + unsigned int en; + + switch (pad->function) { + case PMIC_MPP_ANALOG: + if (pad->input_enabled && pad->output_enabled) + mode = PMIC_MPP_MODE_ANALOG_BIDIR; + else if (pad->input_enabled) + mode = PMIC_MPP_MODE_ANALOG_INPUT; + else + mode = PMIC_MPP_MODE_ANALOG_OUTPUT; + break; + case PMIC_MPP_DIGITAL: + if (pad->input_enabled && pad->output_enabled) + mode = PMIC_MPP_MODE_DIGITAL_BIDIR; + else if (pad->input_enabled) + mode = PMIC_MPP_MODE_DIGITAL_INPUT; + else + mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; + break; + case PMIC_MPP_SINK: + default: + mode = PMIC_MPP_MODE_CURRENT_SINK; + break; } - val = val << PMIC_MPP_REG_MODE_DIR_SHIFT; - val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT; - val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK; + if (pad->dtest) + sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; + else if (pad->paired) + sel = PMIC_MPP_SELECTOR_PAIRED; + else + sel = PMIC_MPP_SELECTOR_NORMAL; + + en = !!pad->out_value; + + val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | + sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | + en; return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); } @@ -358,21 +377,21 @@ static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT: arg = pad->out_value; break; + case PMIC_MPP_CONF_DTEST_SELECTOR: + arg = pad->dtest; + break; case PMIC_MPP_CONF_AMUX_ROUTE: arg = pad->amux_input; break; + case PMIC_MPP_CONF_PAIRED: + arg = pad->paired; + break; case PIN_CONFIG_DRIVE_STRENGTH: arg = pad->drive_strength; break; case PMIC_MPP_CONF_ANALOG_LEVEL: arg = pad->aout_level; break; - case PMIC_MPP_CONF_ANALOG_MODE: - arg = pad->analog_mode; - break; - case PMIC_MPP_CONF_SINK_MODE: - arg = pad->sink_mode; - break; default: return -EINVAL; } @@ -434,6 +453,9 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pad->output_enabled = true; pad->out_value = arg; break; + case PMIC_MPP_CONF_DTEST_SELECTOR: + pad->dtest = arg; + break; case PIN_CONFIG_DRIVE_STRENGTH: arg = pad->drive_strength; break; @@ -445,11 +467,8 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, case PMIC_MPP_CONF_ANALOG_LEVEL: pad->aout_level = arg; break; - case PMIC_MPP_CONF_ANALOG_MODE: - pad->analog_mode = !!arg; - break; - case PMIC_MPP_CONF_SINK_MODE: - pad->sink_mode = !!arg; + case PMIC_MPP_CONF_PAIRED: + pad->paired = !!arg; break; default: return -EINVAL; @@ -498,10 +517,6 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, "0.6kOhm", "10kOhm", "30kOhm", "Disabled" }; - static const char *const modes[] = { - "digital", "analog", "sink" - }; - pad = pctldev->desc->pins[pin].drv_data; seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); @@ -520,12 +535,15 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, } seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); - seq_printf(s, " %-7s", modes[pad->analog_mode ? 1 : (pad->sink_mode ? 2 : 0)]); seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); seq_printf(s, " vin-%d", pad->power_source); seq_printf(s, " %d", pad->aout_level); seq_printf(s, " %-8s", biases[pad->pullup]); seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); + if (pad->dtest) + seq_printf(s, " dtest%d", pad->dtest); + if (pad->paired) + seq_puts(s, " paired"); } } @@ -646,6 +664,7 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, struct pmic_mpp_pad *pad) { int type, subtype, val, dir; + unsigned int sel; type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); if (type < 0) @@ -691,52 +710,50 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, case PMIC_MPP_MODE_DIGITAL_INPUT: pad->input_enabled = true; pad->output_enabled = false; - pad->analog_mode = false; - pad->sink_mode = false; + pad->function = PMIC_MPP_DIGITAL; break; case PMIC_MPP_MODE_DIGITAL_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; - pad->analog_mode = false; - pad->sink_mode = false; + pad->function = PMIC_MPP_DIGITAL; break; case PMIC_MPP_MODE_DIGITAL_BIDIR: pad->input_enabled = true; pad->output_enabled = true; - pad->analog_mode = false; - pad->sink_mode = false; + pad->function = PMIC_MPP_DIGITAL; break; case PMIC_MPP_MODE_ANALOG_BIDIR: pad->input_enabled = true; pad->output_enabled = true; - pad->analog_mode = true; - pad->sink_mode = false; + pad->function = PMIC_MPP_ANALOG; break; case PMIC_MPP_MODE_ANALOG_INPUT: pad->input_enabled = true; pad->output_enabled = false; - pad->analog_mode = true; - pad->sink_mode = false; + pad->function = PMIC_MPP_ANALOG; break; case PMIC_MPP_MODE_ANALOG_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; - pad->analog_mode = true; - pad->sink_mode = false; + pad->function = PMIC_MPP_ANALOG; break; case PMIC_MPP_MODE_CURRENT_SINK: pad->input_enabled = false; pad->output_enabled = true; - pad->analog_mode = false; - pad->sink_mode = true; + pad->function = PMIC_MPP_SINK; break; default: dev_err(state->dev, "unknown MPP direction\n"); return -ENODEV; } - pad->function = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; - pad->function &= PMIC_MPP_REG_MODE_FUNCTION_MASK; + sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; + sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; + + if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) + pad->dtest = sel + 1; + else if (sel == PMIC_MPP_SELECTOR_PAIRED) + pad->paired = true; val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); if (val < 0) -- cgit v1.2.3 From b4c45fe974bc5fa6240a729ea1f77db8b56d132a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 14 Jul 2015 23:40:35 -0700 Subject: pinctrl: qcom: ssbi: Family A gpio & mpp drivers This introduces pinctrl drivers for gpio and mpp blocks found in family A PMICs. Tested-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 5 + drivers/pinctrl/qcom/Kconfig | 12 + drivers/pinctrl/qcom/Makefile | 2 + drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 791 ++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 882 +++++++++++++++++++++ include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 51 ++ 6 files changed, 1743 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index b096d8351b8f..d7803a2a94e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -7,8 +7,13 @@ of PMIC's from Qualcomm. Usage: required Value type: Definition: Should contain one of: + "qcom,pm8018-mpp", + "qcom,pm8038-mpp", + "qcom,pm8821-mpp", "qcom,pm8841-mpp", "qcom,pm8916-mpp", + "qcom,pm8917-mpp", + "qcom,pm8921-mpp", "qcom,pm8941-mpp", "qcom,pma8084-mpp", diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 58f5632b27f4..8eef820b216e 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -76,4 +76,16 @@ config PINCTRL_QCOM_SPMI_PMIC which are using SPMI for communication with SoC. Example PMIC's devices are pm8841, pm8941 and pma8084. +config PINCTRL_QCOM_SSBI_PMIC + tristate "Qualcomm SSBI PMIC pin controller driver" + depends on GPIOLIB && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips, + which are using SSBI for communication with SoC. Example PMIC's + devices are pm8058 and pm8921. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 3666c703ce88..e321f7ab325b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -9,3 +9,5 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o +obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o +obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c new file mode 100644 index 000000000000..c978b311031b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -0,0 +1,791 @@ +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinctrl-utils.h" + +/* mode */ +#define PM8XXX_GPIO_MODE_ENABLED BIT(0) +#define PM8XXX_GPIO_MODE_INPUT 0 +#define PM8XXX_GPIO_MODE_OUTPUT 2 + +/* output buffer */ +#define PM8XXX_GPIO_PUSH_PULL 0 +#define PM8XXX_GPIO_OPEN_DRAIN 1 + +/* bias */ +#define PM8XXX_GPIO_BIAS_PU_30 0 +#define PM8XXX_GPIO_BIAS_PU_1P5 1 +#define PM8XXX_GPIO_BIAS_PU_31P5 2 +#define PM8XXX_GPIO_BIAS_PU_1P5_30 3 +#define PM8XXX_GPIO_BIAS_PD 4 +#define PM8XXX_GPIO_BIAS_NP 5 + +/* GPIO registers */ +#define SSBI_REG_ADDR_GPIO_BASE 0x150 +#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n) + +#define PM8XXX_BANK_WRITE BIT(7) + +#define PM8XXX_MAX_GPIOS 44 + +/* custom pinconf parameters */ +#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) +#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) + +/** + * struct pm8xxx_pin_data - dynamic configuration for a pin + * @reg: address of the control register + * @irq: IRQ from the PMIC interrupt controller + * @power_source: logical selected voltage source, mapping in static data + * is used translate to register values + * @mode: operating mode for the pin (input/output) + * @open_drain: output buffer configured as open-drain (vs push-pull) + * @output_value: configured output value + * @bias: register view of configured bias + * @pull_up_strength: placeholder for selected pull up strength + * only used to configure bias when pull up is selected + * @output_strength: selector of output-strength + * @disable: pin disabled / configured as tristate + * @function: pinmux selector + * @inverted: pin logic is inverted + */ +struct pm8xxx_pin_data { + unsigned reg; + int irq; + u8 power_source; + u8 mode; + bool open_drain; + bool output_value; + u8 bias; + u8 pull_up_strength; + u8 output_strength; + bool disable; + u8 function; + bool inverted; +}; + +struct pm8xxx_gpio { + struct device *dev; + struct regmap *regmap; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + + struct pinctrl_desc desc; + unsigned npins; +}; + +static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { + {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, + {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { + PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), + PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), +}; +#endif + +static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = { + "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", +}; + +static const char * const pm8xxx_gpio_functions[] = { + PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, + PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, + PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, + PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, +}; + +static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl, + struct pm8xxx_pin_data *pin, int bank) +{ + unsigned int val = bank << 4; + int ret; + + ret = regmap_write(pctrl->regmap, pin->reg, val); + if (ret) { + dev_err(pctrl->dev, "failed to select bank %d\n", bank); + return ret; + } + + ret = regmap_read(pctrl->regmap, pin->reg, &val); + if (ret) { + dev_err(pctrl->dev, "failed to read register %d\n", bank); + return ret; + } + + return val; +} + +static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl, + struct pm8xxx_pin_data *pin, + int bank, + u8 val) +{ + int ret; + + val |= PM8XXX_BANK_WRITE; + val |= bank << 4; + + ret = regmap_write(pctrl->regmap, pin->reg, val); + if (ret) + dev_err(pctrl->dev, "failed to write register\n"); + + return ret; +} + +static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->npins; +} + +static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return pm8xxx_groups[group]; +} + + +static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctrl->desc.pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pm8xxx_pinctrl_ops = { + .get_groups_count = pm8xxx_get_groups_count, + .get_group_name = pm8xxx_get_group_name, + .get_group_pins = pm8xxx_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pm8xxx_gpio_functions); +} + +static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return pm8xxx_gpio_functions[function]; +} + +static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pm8xxx_groups; + *num_groups = pctrl->npins; + return 0; +} + +static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; + u8 val; + + pin->function = function; + val = pin->function << 1; + + pm8xxx_write_bank(pctrl, pin, 4, val); + + return 0; +} + +static const struct pinmux_ops pm8xxx_pinmux_ops = { + .get_functions_count = pm8xxx_get_functions_count, + .get_function_name = pm8xxx_get_function_name, + .get_function_groups = pm8xxx_get_function_groups, + .set_mux = pm8xxx_pinmux_set_mux, +}; + +static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *config) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param = pinconf_to_config_param(*config); + unsigned arg; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = pin->bias == PM8XXX_GPIO_BIAS_NP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = pin->bias == PM8XXX_GPIO_BIAS_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30; + break; + case PM8XXX_QCOM_PULL_UP_STRENGTH: + arg = pin->pull_up_strength; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + arg = pin->disable; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg = pin->mode == PM8XXX_GPIO_MODE_INPUT; + break; + case PIN_CONFIG_OUTPUT: + if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) + arg = pin->output_value; + else + arg = 0; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = pin->power_source; + break; + case PM8XXX_QCOM_DRIVE_STRENGH: + arg = pin->output_strength; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + arg = !pin->open_drain; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + arg = pin->open_drain; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *configs, + unsigned num_configs) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param; + unsigned arg; + unsigned i; + u8 banks = 0; + u8 val; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pin->bias = PM8XXX_GPIO_BIAS_NP; + banks |= BIT(2); + pin->disable = 0; + banks |= BIT(3); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + pin->bias = PM8XXX_GPIO_BIAS_PD; + banks |= BIT(2); + pin->disable = 0; + banks |= BIT(3); + break; + case PM8XXX_QCOM_PULL_UP_STRENGTH: + if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) { + dev_err(pctrl->dev, "invalid pull-up strength\n"); + return -EINVAL; + } + pin->pull_up_strength = arg; + /* FALLTHROUGH */ + case PIN_CONFIG_BIAS_PULL_UP: + pin->bias = pin->pull_up_strength; + banks |= BIT(2); + pin->disable = 0; + banks |= BIT(3); + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pin->disable = 1; + banks |= BIT(3); + break; + case PIN_CONFIG_INPUT_ENABLE: + pin->mode = PM8XXX_GPIO_MODE_INPUT; + banks |= BIT(0) | BIT(1); + break; + case PIN_CONFIG_OUTPUT: + pin->mode = PM8XXX_GPIO_MODE_OUTPUT; + pin->output_value = !!arg; + banks |= BIT(0) | BIT(1); + break; + case PIN_CONFIG_POWER_SOURCE: + pin->power_source = arg; + banks |= BIT(0); + break; + case PM8XXX_QCOM_DRIVE_STRENGH: + if (arg > PMIC_GPIO_STRENGTH_LOW) { + dev_err(pctrl->dev, "invalid drive strength\n"); + return -EINVAL; + } + pin->output_strength = arg; + banks |= BIT(3); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + pin->open_drain = 0; + banks |= BIT(1); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + pin->open_drain = 1; + banks |= BIT(1); + break; + default: + dev_err(pctrl->dev, + "unsupported config parameter: %x\n", + param); + return -EINVAL; + } + } + + if (banks & BIT(0)) { + val = pin->power_source << 1; + val |= PM8XXX_GPIO_MODE_ENABLED; + pm8xxx_write_bank(pctrl, pin, 0, val); + } + + if (banks & BIT(1)) { + val = pin->mode << 2; + val |= pin->open_drain << 1; + val |= pin->output_value; + pm8xxx_write_bank(pctrl, pin, 1, val); + } + + if (banks & BIT(2)) { + val = pin->bias << 1; + pm8xxx_write_bank(pctrl, pin, 2, val); + } + + if (banks & BIT(3)) { + val = pin->output_strength << 2; + val |= pin->disable; + pm8xxx_write_bank(pctrl, pin, 3, val); + } + + if (banks & BIT(4)) { + val = pin->function << 1; + pm8xxx_write_bank(pctrl, pin, 4, val); + } + + if (banks & BIT(5)) { + val = 0; + if (!pin->inverted) + val |= BIT(3); + pm8xxx_write_bank(pctrl, pin, 5, val); + } + + return 0; +} + +static const struct pinconf_ops pm8xxx_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = pm8xxx_pin_config_get, + .pin_config_group_set = pm8xxx_pin_config_set, +}; + +static struct pinctrl_desc pm8xxx_pinctrl_desc = { + .name = "pm8xxx_gpio", + .pctlops = &pm8xxx_pinctrl_ops, + .pmxops = &pm8xxx_pinmux_ops, + .confops = &pm8xxx_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int pm8xxx_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + u8 val; + + pin->mode = PM8XXX_GPIO_MODE_INPUT; + val = pin->mode << 2; + + pm8xxx_write_bank(pctrl, pin, 1, val); + + return 0; +} + +static int pm8xxx_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + u8 val; + + pin->mode = PM8XXX_GPIO_MODE_OUTPUT; + pin->output_value = !!value; + + val = pin->mode << 2; + val |= pin->open_drain << 1; + val |= pin->output_value; + + pm8xxx_write_bank(pctrl, pin, 1, val); + + return 0; +} + +static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + bool state; + int ret; + + if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) { + ret = pin->output_value; + } else { + ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); + if (!ret) + ret = !!state; + } + + return ret; +} + +static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + u8 val; + + pin->output_value = !!value; + + val = pin->mode << 2; + val |= pin->open_drain << 1; + val |= pin->output_value; + + pm8xxx_write_bank(pctrl, pin, 1, val); +} + +static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) + return -EINVAL; + + if (flags) + *flags = gpio_desc->args[1]; + + return gpio_desc->args[0] - 1; +} + + +static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + return pin->irq; +} + +#ifdef CONFIG_DEBUG_FS +#include + +static void pm8xxx_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + static const char * const modes[] = { + "in", "both", "out", "off" + }; + static const char * const biases[] = { + "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", + "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" + }; + static const char * const buffer_types[] = { + "push-pull", "open-drain" + }; + static const char * const strengths[] = { + "no", "high", "medium", "low" + }; + + seq_printf(s, " gpio%-2d:", offset + 1); + if (pin->disable) { + seq_puts(s, " ---"); + } else { + seq_printf(s, " %-4s", modes[pin->mode]); + seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); + seq_printf(s, " VIN%d", pin->power_source); + seq_printf(s, " %-27s", biases[pin->bias]); + seq_printf(s, " %-10s", buffer_types[pin->open_drain]); + seq_printf(s, " %-4s", pin->output_value ? "high" : "low"); + seq_printf(s, " %-7s", strengths[pin->output_strength]); + if (pin->inverted) + seq_puts(s, " inverted"); + } +} + +static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define msm_gpio_dbg_show NULL +#endif + +static struct gpio_chip pm8xxx_gpio_template = { + .direction_input = pm8xxx_gpio_direction_input, + .direction_output = pm8xxx_gpio_direction_output, + .get = pm8xxx_gpio_get, + .set = pm8xxx_gpio_set, + .of_xlate = pm8xxx_gpio_of_xlate, + .to_irq = pm8xxx_gpio_to_irq, + .dbg_show = pm8xxx_gpio_dbg_show, + .owner = THIS_MODULE, +}; + +static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, + struct pm8xxx_pin_data *pin) +{ + int val; + + val = pm8xxx_read_bank(pctrl, pin, 0); + if (val < 0) + return val; + + pin->power_source = (val >> 1) & 0x7; + + val = pm8xxx_read_bank(pctrl, pin, 1); + if (val < 0) + return val; + + pin->mode = (val >> 2) & 0x3; + pin->open_drain = !!(val & BIT(1)); + pin->output_value = val & BIT(0); + + val = pm8xxx_read_bank(pctrl, pin, 2); + if (val < 0) + return val; + + pin->bias = (val >> 1) & 0x7; + if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) + pin->pull_up_strength = pin->bias; + else + pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; + + val = pm8xxx_read_bank(pctrl, pin, 3); + if (val < 0) + return val; + + pin->output_strength = (val >> 2) & 0x3; + pin->disable = val & BIT(0); + + val = pm8xxx_read_bank(pctrl, pin, 4); + if (val < 0) + return val; + + pin->function = (val >> 1) & 0x7; + + val = pm8xxx_read_bank(pctrl, pin, 5); + if (val < 0) + return val; + + pin->inverted = !(val & BIT(3)); + + return 0; +} + +static const struct of_device_id pm8xxx_gpio_of_match[] = { + { .compatible = "qcom,pm8018-gpio", .data = (void *)6 }, + { .compatible = "qcom,pm8038-gpio", .data = (void *)12 }, + { .compatible = "qcom,pm8058-gpio", .data = (void *)40 }, + { .compatible = "qcom,pm8917-gpio", .data = (void *)38 }, + { .compatible = "qcom,pm8921-gpio", .data = (void *)44 }, + { }, +}; +MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match); + +static int pm8xxx_gpio_probe(struct platform_device *pdev) +{ + struct pm8xxx_pin_data *pin_data; + struct pinctrl_pin_desc *pins; + struct pm8xxx_gpio *pctrl; + int ret; + int i; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev); + + pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!pctrl->regmap) { + dev_err(&pdev->dev, "parent regmap unavailable\n"); + return -ENXIO; + } + + pctrl->desc = pm8xxx_pinctrl_desc; + pctrl->desc.npins = pctrl->npins; + + pins = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pinctrl_pin_desc), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pin_data = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pm8xxx_pin_data), + GFP_KERNEL); + if (!pin_data) + return -ENOMEM; + + for (i = 0; i < pctrl->desc.npins; i++) { + pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); + pin_data[i].irq = platform_get_irq(pdev, i); + if (pin_data[i].irq < 0) { + dev_err(&pdev->dev, + "missing interrupts for pin %d\n", i); + return pin_data[i].irq; + } + + ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); + if (ret) + return ret; + + pins[i].number = i; + pins[i].name = pm8xxx_groups[i]; + pins[i].drv_data = &pin_data[i]; + } + pctrl->desc.pins = pins; + + pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); + pctrl->desc.custom_params = pm8xxx_gpio_bindings; +#ifdef CONFIG_DEBUG_FS + pctrl->desc.custom_conf_items = pm8xxx_conf_items; +#endif + + pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl); + if (!pctrl->pctrl) { + dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); + return -ENODEV; + } + + pctrl->chip = pm8xxx_gpio_template; + pctrl->chip.base = -1; + pctrl->chip.dev = &pdev->dev; + pctrl->chip.of_node = pdev->dev.of_node; + pctrl->chip.of_gpio_n_cells = 2; + pctrl->chip.label = dev_name(pctrl->dev); + pctrl->chip.ngpio = pctrl->npins; + ret = gpiochip_add(&pctrl->chip); + if (ret) { + dev_err(&pdev->dev, "failed register gpiochip\n"); + goto unregister_pinctrl; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, + dev_name(pctrl->dev), + 0, 0, pctrl->chip.ngpio); + if (ret) { + dev_err(pctrl->dev, "failed to add pin range\n"); + goto unregister_gpiochip; + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); + + return 0; + +unregister_gpiochip: + gpiochip_remove(&pctrl->chip); + +unregister_pinctrl: + pinctrl_unregister(pctrl->pctrl); + + return ret; +} + +static int pm8xxx_gpio_remove(struct platform_device *pdev) +{ + struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} + +static struct platform_driver pm8xxx_gpio_driver = { + .driver = { + .name = "qcom-ssbi-gpio", + .of_match_table = pm8xxx_gpio_of_match, + }, + .probe = pm8xxx_gpio_probe, + .remove = pm8xxx_gpio_remove, +}; + +module_platform_driver(pm8xxx_gpio_driver); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c new file mode 100644 index 000000000000..2d1b69f171be --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -0,0 +1,882 @@ +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinctrl-utils.h" + +/* MPP registers */ +#define SSBI_REG_ADDR_MPP_BASE 0x50 +#define SSBI_REG_ADDR_MPP(n) (SSBI_REG_ADDR_MPP_BASE + n) + +/* MPP Type: type */ +#define PM8XXX_MPP_TYPE_D_INPUT 0 +#define PM8XXX_MPP_TYPE_D_OUTPUT 1 +#define PM8XXX_MPP_TYPE_D_BI_DIR 2 +#define PM8XXX_MPP_TYPE_A_INPUT 3 +#define PM8XXX_MPP_TYPE_A_OUTPUT 4 +#define PM8XXX_MPP_TYPE_SINK 5 +#define PM8XXX_MPP_TYPE_DTEST_SINK 6 +#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7 + +/* Digital Input: control */ +#define PM8XXX_MPP_DIN_TO_INT 0 +#define PM8XXX_MPP_DIN_TO_DBUS1 1 +#define PM8XXX_MPP_DIN_TO_DBUS2 2 +#define PM8XXX_MPP_DIN_TO_DBUS3 3 + +/* Digital Output: control */ +#define PM8XXX_MPP_DOUT_CTRL_LOW 0 +#define PM8XXX_MPP_DOUT_CTRL_HIGH 1 +#define PM8XXX_MPP_DOUT_CTRL_MPP 2 +#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3 + +/* Bidirectional: control */ +#define PM8XXX_MPP_BI_PULLUP_1KOHM 0 +#define PM8XXX_MPP_BI_PULLUP_OPEN 1 +#define PM8XXX_MPP_BI_PULLUP_10KOHM 2 +#define PM8XXX_MPP_BI_PULLUP_30KOHM 3 + +/* Analog Output: control */ +#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0 +#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1 +#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2 +#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3 + +/* Current Sink: control */ +#define PM8XXX_MPP_CS_CTRL_DISABLE 0 +#define PM8XXX_MPP_CS_CTRL_ENABLE 1 +#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2 +#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3 + +/* DTEST Current Sink: control */ +#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0 +#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1 +#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2 +#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3 + +/* DTEST Digital Output: control */ +#define PM8XXX_MPP_DTEST_DBUS1 0 +#define PM8XXX_MPP_DTEST_DBUS2 1 +#define PM8XXX_MPP_DTEST_DBUS3 2 +#define PM8XXX_MPP_DTEST_DBUS4 3 + +/* custom pinconf parameters */ +#define PM8XXX_CONFIG_AMUX (PIN_CONFIG_END + 1) +#define PM8XXX_CONFIG_DTEST_SELECTOR (PIN_CONFIG_END + 2) +#define PM8XXX_CONFIG_ALEVEL (PIN_CONFIG_END + 3) +#define PM8XXX_CONFIG_PAIRED (PIN_CONFIG_END + 4) + +/** + * struct pm8xxx_pin_data - dynamic configuration for a pin + * @reg: address of the control register + * @irq: IRQ from the PMIC interrupt controller + * @mode: operating mode for the pin (digital, analog or current sink) + * @input: pin is input + * @output: pin is output + * @high_z: pin is floating + * @paired: mpp operates in paired mode + * @output_value: logical output value of the mpp + * @power_source: selected power source + * @dtest: DTEST route selector + * @amux: input muxing in analog mode + * @aout_level: selector of the output in analog mode + * @drive_strength: drive strength of the current sink + * @pullup: pull up value, when in digital bidirectional mode + */ +struct pm8xxx_pin_data { + unsigned reg; + int irq; + + u8 mode; + + bool input; + bool output; + bool high_z; + bool paired; + bool output_value; + + u8 power_source; + u8 dtest; + u8 amux; + u8 aout_level; + u8 drive_strength; + unsigned pullup; +}; + +struct pm8xxx_mpp { + struct device *dev; + struct regmap *regmap; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + + struct pinctrl_desc desc; + unsigned npins; +}; + +static const struct pinconf_generic_params pm8xxx_mpp_bindings[] = { + {"qcom,amux-route", PM8XXX_CONFIG_AMUX, 0}, + {"qcom,analog-level", PM8XXX_CONFIG_ALEVEL, 0}, + {"qcom,dtest", PM8XXX_CONFIG_DTEST_SELECTOR, 0}, + {"qcom,paired", PM8XXX_CONFIG_PAIRED, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pm8xxx_conf_items[] = { + PCONFDUMP(PM8XXX_CONFIG_AMUX, "analog mux", NULL, true), + PCONFDUMP(PM8XXX_CONFIG_ALEVEL, "analog level", NULL, true), + PCONFDUMP(PM8XXX_CONFIG_DTEST_SELECTOR, "dtest", NULL, true), + PCONFDUMP(PM8XXX_CONFIG_PAIRED, "paired", NULL, false), +}; +#endif + +#define PM8XXX_MAX_MPPS 12 +static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = { + "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", "mpp12", +}; + +#define PM8XXX_MPP_DIGITAL 0 +#define PM8XXX_MPP_ANALOG 1 +#define PM8XXX_MPP_SINK 2 + +static const char * const pm8xxx_mpp_functions[] = { + "digital", "analog", "sink", +}; + +static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl, + struct pm8xxx_pin_data *pin) +{ + unsigned level; + unsigned ctrl; + unsigned type; + int ret; + u8 val; + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + if (pin->dtest) { + type = PM8XXX_MPP_TYPE_DTEST_OUTPUT; + ctrl = pin->dtest - 1; + } else if (pin->input && pin->output) { + type = PM8XXX_MPP_TYPE_D_BI_DIR; + if (pin->high_z) + ctrl = PM8XXX_MPP_BI_PULLUP_OPEN; + else if (pin->pullup == 600) + ctrl = PM8XXX_MPP_BI_PULLUP_1KOHM; + else if (pin->pullup == 10000) + ctrl = PM8XXX_MPP_BI_PULLUP_10KOHM; + else + ctrl = PM8XXX_MPP_BI_PULLUP_30KOHM; + } else if (pin->input) { + type = PM8XXX_MPP_TYPE_D_INPUT; + if (pin->dtest) + ctrl = pin->dtest; + else + ctrl = PM8XXX_MPP_DIN_TO_INT; + } else { + type = PM8XXX_MPP_TYPE_D_OUTPUT; + ctrl = !!pin->output_value; + if (pin->paired) + ctrl |= BIT(1); + } + + level = pin->power_source; + break; + case PM8XXX_MPP_ANALOG: + if (pin->output) { + type = PM8XXX_MPP_TYPE_A_OUTPUT; + level = pin->aout_level; + ctrl = pin->output_value; + if (pin->paired) + ctrl |= BIT(1); + } else { + type = PM8XXX_MPP_TYPE_A_INPUT; + level = pin->amux; + ctrl = 0; + } + break; + case PM8XXX_MPP_SINK: + level = (pin->drive_strength / 5) - 1; + if (pin->dtest) { + type = PM8XXX_MPP_TYPE_DTEST_SINK; + ctrl = pin->dtest - 1; + } else { + type = PM8XXX_MPP_TYPE_SINK; + ctrl = pin->output_value; + if (pin->paired) + ctrl |= BIT(1); + } + break; + default: + return -EINVAL; + } + + val = type << 5 | level << 2 | ctrl; + ret = regmap_write(pctrl->regmap, pin->reg, val); + if (ret) + dev_err(pctrl->dev, "failed to write register\n"); + + return ret; +} + +static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->npins; +} + +static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return pm8xxx_groups[group]; +} + + +static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctrl->desc.pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pm8xxx_pinctrl_ops = { + .get_groups_count = pm8xxx_get_groups_count, + .get_group_name = pm8xxx_get_group_name, + .get_group_pins = pm8xxx_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pm8xxx_mpp_functions); +} + +static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return pm8xxx_mpp_functions[function]; +} + +static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pm8xxx_groups; + *num_groups = pctrl->npins; + return 0; +} + +static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; + + pin->mode = function; + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static const struct pinmux_ops pm8xxx_pinmux_ops = { + .get_functions_count = pm8xxx_get_functions_count, + .get_function_name = pm8xxx_get_function_name, + .get_function_groups = pm8xxx_get_function_groups, + .set_mux = pm8xxx_pinmux_set_mux, +}; + +static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *config) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param = pinconf_to_config_param(*config); + unsigned arg; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + arg = pin->pullup; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + arg = pin->high_z; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg = pin->input; + break; + case PIN_CONFIG_OUTPUT: + arg = pin->output_value; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = pin->power_source; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pin->drive_strength; + break; + case PM8XXX_CONFIG_DTEST_SELECTOR: + arg = pin->dtest; + break; + case PM8XXX_CONFIG_AMUX: + arg = pin->amux; + break; + case PM8XXX_CONFIG_ALEVEL: + arg = pin->aout_level; + break; + case PM8XXX_CONFIG_PAIRED: + arg = pin->paired; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *configs, + unsigned num_configs) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param; + unsigned arg; + unsigned i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + pin->pullup = arg; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pin->high_z = true; + break; + case PIN_CONFIG_INPUT_ENABLE: + pin->input = true; + break; + case PIN_CONFIG_OUTPUT: + pin->output = true; + pin->output_value = !!arg; + break; + case PIN_CONFIG_POWER_SOURCE: + pin->power_source = arg; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + pin->drive_strength = arg; + break; + case PM8XXX_CONFIG_DTEST_SELECTOR: + pin->dtest = arg; + break; + case PM8XXX_CONFIG_AMUX: + pin->amux = arg; + break; + case PM8XXX_CONFIG_ALEVEL: + pin->aout_level = arg; + break; + case PM8XXX_CONFIG_PAIRED: + pin->paired = !!arg; + break; + default: + dev_err(pctrl->dev, + "unsupported config parameter: %x\n", + param); + return -EINVAL; + } + } + + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static const struct pinconf_ops pm8xxx_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = pm8xxx_pin_config_get, + .pin_config_group_set = pm8xxx_pin_config_set, +}; + +static struct pinctrl_desc pm8xxx_pinctrl_desc = { + .name = "pm8xxx_mpp", + .pctlops = &pm8xxx_pinctrl_ops, + .pmxops = &pm8xxx_pinmux_ops, + .confops = &pm8xxx_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int pm8xxx_mpp_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + pin->input = true; + break; + case PM8XXX_MPP_ANALOG: + pin->input = true; + pin->output = true; + break; + case PM8XXX_MPP_SINK: + return -EINVAL; + } + + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static int pm8xxx_mpp_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + pin->output = true; + break; + case PM8XXX_MPP_ANALOG: + pin->input = false; + pin->output = true; + break; + case PM8XXX_MPP_SINK: + pin->input = false; + pin->output = true; + break; + } + + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset) +{ + struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + bool state; + int ret; + + if (!pin->input) + return pin->output_value; + + ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); + if (!ret) + ret = !!state; + + return ret; +} + +static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + pin->output_value = !!value; + + pm8xxx_mpp_update(pctrl, pin); +} + +static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) + return -EINVAL; + + if (flags) + *flags = gpio_desc->args[1]; + + return gpio_desc->args[0] - 1; +} + + +static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + return pin->irq; +} + +#ifdef CONFIG_DEBUG_FS +#include + +static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + static const char * const aout_lvls[] = { + "1v25", "1v25_2", "0v625", "0v3125", "mpp", "abus1", "abus2", + "abus3" + }; + + static const char * const amuxs[] = { + "amux5", "amux6", "amux7", "amux8", "amux9", "abus1", "abus2", + "abus3", + }; + + seq_printf(s, " mpp%-2d:", offset + 1); + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + seq_puts(s, " digital "); + if (pin->dtest) { + seq_printf(s, "dtest%d\n", pin->dtest); + } else if (pin->input && pin->output) { + if (pin->high_z) + seq_puts(s, "bi-dir high-z"); + else + seq_printf(s, "bi-dir %dOhm", pin->pullup); + } else if (pin->input) { + if (pin->dtest) + seq_printf(s, "in dtest%d", pin->dtest); + else + seq_puts(s, "in gpio"); + } else if (pin->output) { + seq_puts(s, "out "); + + if (!pin->paired) { + seq_puts(s, pin->output_value ? + "high" : "low"); + } else { + seq_puts(s, pin->output_value ? + "inverted" : "follow"); + } + } + break; + case PM8XXX_MPP_ANALOG: + seq_puts(s, " analog "); + if (pin->output) { + seq_printf(s, "out %s ", aout_lvls[pin->aout_level]); + if (!pin->paired) { + seq_puts(s, pin->output_value ? + "high" : "low"); + } else { + seq_puts(s, pin->output_value ? + "inverted" : "follow"); + } + } else { + seq_printf(s, "input mux %s", amuxs[pin->amux]); + } + break; + case PM8XXX_MPP_SINK: + seq_printf(s, " sink %dmA ", pin->drive_strength); + if (pin->dtest) { + seq_printf(s, "dtest%d", pin->dtest); + } else { + if (!pin->paired) { + seq_puts(s, pin->output_value ? + "high" : "low"); + } else { + seq_puts(s, pin->output_value ? + "inverted" : "follow"); + } + } + break; + } + +} + +static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + pm8xxx_mpp_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define msm_mpp_dbg_show NULL +#endif + +static struct gpio_chip pm8xxx_mpp_template = { + .direction_input = pm8xxx_mpp_direction_input, + .direction_output = pm8xxx_mpp_direction_output, + .get = pm8xxx_mpp_get, + .set = pm8xxx_mpp_set, + .of_xlate = pm8xxx_mpp_of_xlate, + .to_irq = pm8xxx_mpp_to_irq, + .dbg_show = pm8xxx_mpp_dbg_show, + .owner = THIS_MODULE, +}; + +static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, + struct pm8xxx_pin_data *pin) +{ + unsigned int val; + unsigned level; + unsigned ctrl; + unsigned type; + int ret; + + ret = regmap_read(pctrl->regmap, pin->reg, &val); + if (ret) { + dev_err(pctrl->dev, "failed to read register\n"); + return ret; + } + + type = (val >> 5) & 7; + level = (val >> 2) & 7; + ctrl = (val) & 3; + + switch (type) { + case PM8XXX_MPP_TYPE_D_INPUT: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->input = true; + pin->power_source = level; + pin->dtest = ctrl; + break; + case PM8XXX_MPP_TYPE_D_OUTPUT: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->output = true; + pin->power_source = level; + pin->output_value = !!(ctrl & BIT(0)); + pin->paired = !!(ctrl & BIT(1)); + break; + case PM8XXX_MPP_TYPE_D_BI_DIR: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->input = true; + pin->output = true; + pin->power_source = level; + switch (ctrl) { + case PM8XXX_MPP_BI_PULLUP_1KOHM: + pin->pullup = 600; + break; + case PM8XXX_MPP_BI_PULLUP_OPEN: + pin->high_z = true; + break; + case PM8XXX_MPP_BI_PULLUP_10KOHM: + pin->pullup = 10000; + break; + case PM8XXX_MPP_BI_PULLUP_30KOHM: + pin->pullup = 30000; + break; + } + break; + case PM8XXX_MPP_TYPE_A_INPUT: + pin->mode = PM8XXX_MPP_ANALOG; + pin->input = true; + pin->amux = level; + break; + case PM8XXX_MPP_TYPE_A_OUTPUT: + pin->mode = PM8XXX_MPP_ANALOG; + pin->output = true; + pin->aout_level = level; + pin->output_value = !!(ctrl & BIT(0)); + pin->paired = !!(ctrl & BIT(1)); + break; + case PM8XXX_MPP_TYPE_SINK: + pin->mode = PM8XXX_MPP_SINK; + pin->drive_strength = 5 * (level + 1); + pin->output_value = !!(ctrl & BIT(0)); + pin->paired = !!(ctrl & BIT(1)); + break; + case PM8XXX_MPP_TYPE_DTEST_SINK: + pin->mode = PM8XXX_MPP_SINK; + pin->dtest = ctrl + 1; + pin->drive_strength = 5 * (level + 1); + break; + case PM8XXX_MPP_TYPE_DTEST_OUTPUT: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->power_source = level; + if (ctrl >= 1) + pin->dtest = ctrl; + break; + } + + return 0; +} + +static const struct of_device_id pm8xxx_mpp_of_match[] = { + { .compatible = "qcom,pm8018-mpp", .data = (void *)6 }, + { .compatible = "qcom,pm8038-mpp", .data = (void *)6 }, + { .compatible = "qcom,pm8917-mpp", .data = (void *)10 }, + { .compatible = "qcom,pm8821-mpp", .data = (void *)4 }, + { .compatible = "qcom,pm8921-mpp", .data = (void *)12 }, + { }, +}; +MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); + +static int pm8xxx_mpp_probe(struct platform_device *pdev) +{ + struct pm8xxx_pin_data *pin_data; + struct pinctrl_pin_desc *pins; + struct pm8xxx_mpp *pctrl; + int ret; + int i; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev); + + pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!pctrl->regmap) { + dev_err(&pdev->dev, "parent regmap unavailable\n"); + return -ENXIO; + } + + pctrl->desc = pm8xxx_pinctrl_desc; + pctrl->desc.npins = pctrl->npins; + + pins = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pinctrl_pin_desc), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pin_data = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pm8xxx_pin_data), + GFP_KERNEL); + if (!pin_data) + return -ENOMEM; + + for (i = 0; i < pctrl->desc.npins; i++) { + pin_data[i].reg = SSBI_REG_ADDR_MPP(i); + pin_data[i].irq = platform_get_irq(pdev, i); + if (pin_data[i].irq < 0) { + dev_err(&pdev->dev, + "missing interrupts for pin %d\n", i); + return pin_data[i].irq; + } + + ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); + if (ret) + return ret; + + pins[i].number = i; + pins[i].name = pm8xxx_groups[i]; + pins[i].drv_data = &pin_data[i]; + } + pctrl->desc.pins = pins; + + pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings); + pctrl->desc.custom_params = pm8xxx_mpp_bindings; +#ifdef CONFIG_DEBUG_FS + pctrl->desc.custom_conf_items = pm8xxx_conf_items; +#endif + + pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl); + if (!pctrl->pctrl) { + dev_err(&pdev->dev, "couldn't register pm8xxx mpp driver\n"); + return -ENODEV; + } + + pctrl->chip = pm8xxx_mpp_template; + pctrl->chip.base = -1; + pctrl->chip.dev = &pdev->dev; + pctrl->chip.of_node = pdev->dev.of_node; + pctrl->chip.of_gpio_n_cells = 2; + pctrl->chip.label = dev_name(pctrl->dev); + pctrl->chip.ngpio = pctrl->npins; + ret = gpiochip_add(&pctrl->chip); + if (ret) { + dev_err(&pdev->dev, "failed register gpiochip\n"); + goto unregister_pinctrl; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, + dev_name(pctrl->dev), + 0, 0, pctrl->chip.ngpio); + if (ret) { + dev_err(pctrl->dev, "failed to add pin range\n"); + goto unregister_gpiochip; + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Qualcomm pm8xxx mpp driver probed\n"); + + return 0; + +unregister_gpiochip: + gpiochip_remove(&pctrl->chip); + +unregister_pinctrl: + pinctrl_unregister(pctrl->pctrl); + + return ret; +} + +static int pm8xxx_mpp_remove(struct platform_device *pdev) +{ + struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} + +static struct platform_driver pm8xxx_mpp_driver = { + .driver = { + .name = "qcom-ssbi-mpp", + .of_match_table = pm8xxx_mpp_of_match, + }, + .probe = pm8xxx_mpp_probe, + .remove = pm8xxx_mpp_remove, +}; + +module_platform_driver(pm8xxx_mpp_driver); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm PM8xxx MPP driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h index c10205491f8d..a15c1704d0ec 100644 --- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h @@ -7,6 +7,47 @@ #define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H /* power-source */ + +/* Digital Input/Output: level [PM8058] */ +#define PM8058_MPP_VPH 0 +#define PM8058_MPP_S3 1 +#define PM8058_MPP_L2 2 +#define PM8058_MPP_L3 3 + +/* Digital Input/Output: level [PM8901] */ +#define PM8901_MPP_MSMIO 0 +#define PM8901_MPP_DIG 1 +#define PM8901_MPP_L5 2 +#define PM8901_MPP_S4 3 +#define PM8901_MPP_VPH 4 + +/* Digital Input/Output: level [PM8921] */ +#define PM8921_MPP_S4 1 +#define PM8921_MPP_L15 3 +#define PM8921_MPP_L17 4 +#define PM8921_MPP_VPH 7 + +/* Digital Input/Output: level [PM8821] */ +#define PM8821_MPP_1P8 0 +#define PM8821_MPP_VPH 7 + +/* Digital Input/Output: level [PM8018] */ +#define PM8018_MPP_L4 0 +#define PM8018_MPP_L14 1 +#define PM8018_MPP_S3 2 +#define PM8018_MPP_L6 3 +#define PM8018_MPP_L2 4 +#define PM8018_MPP_L5 5 +#define PM8018_MPP_VPH 7 + +/* Digital Input/Output: level [PM8038] */ +#define PM8038_MPP_L20 0 +#define PM8038_MPP_L11 1 +#define PM8038_MPP_L5 2 +#define PM8038_MPP_L15 3 +#define PM8038_MPP_L17 4 +#define PM8038_MPP_VPH 7 + #define PM8841_MPP_VPH 0 #define PM8841_MPP_S3 2 @@ -37,6 +78,16 @@ #define PMIC_MPP_AMUX_ROUTE_ABUS3 6 #define PMIC_MPP_AMUX_ROUTE_ABUS4 7 +/* Analog Output: level */ +#define PMIC_MPP_AOUT_LVL_1V25 0 +#define PMIC_MPP_AOUT_LVL_1V25_2 1 +#define PMIC_MPP_AOUT_LVL_0V625 2 +#define PMIC_MPP_AOUT_LVL_0V3125 3 +#define PMIC_MPP_AOUT_LVL_MPP 4 +#define PMIC_MPP_AOUT_LVL_ABUS1 5 +#define PMIC_MPP_AOUT_LVL_ABUS2 6 +#define PMIC_MPP_AOUT_LVL_ABUS3 7 + /* To be used with "function" */ #define PMIC_MPP_FUNC_NORMAL "normal" #define PMIC_MPP_FUNC_PAIRED "paired" -- cgit v1.2.3 From 8f1338cd80648adf5434798f5393ad7c55d10848 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 15 Jul 2015 11:47:14 -0500 Subject: pinctrl: add support for Qualcomm Technologies QDF2xxx ARM64 SoCs Add the pinctrl driver for the Qualcomm Technologies QDF2xxx ARM64 SoCs, which uses the Qualcomm Technologies TLMM pinctrl/gpio device. This driver is probed via ACPI and uses the pinctrl-msm.c backend driver. This driver is intended to be used only an ACPI-enabled system. As such, UEFI will handle all pin control configuration, so this driver does not provide pin control functions. It is effectively a GPIO-only driver. Signed-off-by: Timur Tabi Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 8 +++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 122 +++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 8eef820b216e..383263a92e59 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -63,6 +63,14 @@ config PINCTRL_MSM8916 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. +config PINCTRL_QDF2XXX + tristate "Qualcomm Technologies QDF2xxx pin controller driver" + depends on GPIOLIB && ACPI + select PINCTRL_MSM + help + This is the GPIO driver for the TLMM block found on the + Qualcomm Technologies QDF2xxx SOCs. + config PINCTRL_QCOM_SPMI_PMIC tristate "Qualcomm SPMI PMIC pin controller driver" depends on GPIOLIB && OF && SPMI diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index e321f7ab325b..13b190e72c21 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c new file mode 100644 index 000000000000..e9ff3bc150bb --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * GPIO and pin control functions on this SOC are handled by the "TLMM" + * device. The driver which controls this device is pinctrl-msm.c. Each + * SOC with a TLMM is expected to create a client driver that registers + * with pinctrl-msm.c. This means that all TLMM drivers are pin control + * drivers. + * + * This pin control driver is intended to be used only an ACPI-enabled + * system. As such, UEFI will handle all pin control configuration, so + * this driver does not provide pin control functions. It is effectively + * a GPIO-only driver. The alternative is to duplicate the GPIO code of + * pinctrl-msm.c into another driver. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static struct msm_pinctrl_soc_data qdf2xxx_pinctrl; + +static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) +{ + struct pinctrl_pin_desc *pins; + struct msm_pingroup *groups; + unsigned int i; + u32 num_gpios; + int ret; + + /* Query the number of GPIOs from ACPI */ + ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); + if (ret < 0) + return ret; + + if (!num_gpios) { + dev_warn(&pdev->dev, "missing num-gpios property\n"); + return -ENODEV; + } + + pins = devm_kcalloc(&pdev->dev, num_gpios, + sizeof(struct pinctrl_pin_desc), GFP_KERNEL); + groups = devm_kcalloc(&pdev->dev, num_gpios, + sizeof(struct msm_pingroup), GFP_KERNEL); + + for (i = 0; i < num_gpios; i++) { + pins[i].number = i; + + groups[i].npins = 1, + groups[i].pins = &pins[i].number; + groups[i].ctl_reg = 0x10000 * i; + groups[i].io_reg = 0x04 + 0x10000 * i; + groups[i].intr_cfg_reg = 0x08 + 0x10000 * i; + groups[i].intr_status_reg = 0x0c + 0x10000 * i; + groups[i].intr_target_reg = 0x08 + 0x10000 * i; + + groups[i].mux_bit = 2; + groups[i].pull_bit = 0; + groups[i].drv_bit = 6; + groups[i].oe_bit = 9; + groups[i].in_bit = 0; + groups[i].out_bit = 1; + groups[i].intr_enable_bit = 0; + groups[i].intr_status_bit = 0; + groups[i].intr_target_bit = 5; + groups[i].intr_target_kpss_val = 1; + groups[i].intr_raw_status_bit = 4; + groups[i].intr_polarity_bit = 1; + groups[i].intr_detection_bit = 2; + groups[i].intr_detection_width = 2; + } + + qdf2xxx_pinctrl.pins = pins; + qdf2xxx_pinctrl.groups = groups; + qdf2xxx_pinctrl.npins = num_gpios; + qdf2xxx_pinctrl.ngroups = num_gpios; + qdf2xxx_pinctrl.ngpios = num_gpios; + + return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl); +} + +static const struct acpi_device_id qdf2xxx_acpi_ids[] = { + {"QCOM8001"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); + +static struct platform_driver qdf2xxx_pinctrl_driver = { + .driver = { + .name = "qdf2xxx-pinctrl", + .acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids), + }, + .probe = qdf2xxx_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qdf2xxx_pinctrl_init(void) +{ + return platform_driver_register(&qdf2xxx_pinctrl_driver); +} +arch_initcall(qdf2xxx_pinctrl_init); + +static void __exit qdf2xxx_pinctrl_exit(void) +{ + platform_driver_unregister(&qdf2xxx_pinctrl_driver); +} +module_exit(qdf2xxx_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 03051bc242209f7130aec42d1a6ecb3be9f8f93b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 21 Jun 2015 21:11:06 +0200 Subject: pinctrl/rockchip: Consolidate chained IRQ handler install/remove Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 9affcd725776..626a4a6287e8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1689,8 +1689,8 @@ static int rockchip_interrupts_register(struct platform_device *pdev, gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; gc->wake_enabled = IRQ_MSK(bank->nr_pins); - irq_set_handler_data(bank->irq, bank); - irq_set_chained_handler(bank->irq, rockchip_irq_demux); + irq_set_chained_handler_and_data(bank->irq, + rockchip_irq_demux, bank); } return 0; -- cgit v1.2.3 From 20d5d142a645600f28cf42b8e3336f7309897b1e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 21 Jun 2015 21:11:06 +0200 Subject: pinctrl: Consolidate chained IRQ handler install/remove Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-single.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 1cd085d92147..07661c86f7ef 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1767,9 +1767,9 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs, return res; } } else { - irq_set_handler_data(pcs_soc->irq, pcs_soc); - irq_set_chained_handler(pcs_soc->irq, - pcs_irq_chain_handler); + irq_set_chained_handler_and_data(pcs_soc->irq, + pcs_irq_chain_handler, + pcs_soc); } /* -- cgit v1.2.3 From c21f7849f126570c0bb1ececbb3ddba7b20cfc03 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 21 Jun 2015 21:11:07 +0200 Subject: pinctrl/exynos: Consolidate chained IRQ handler install/remove Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index b18dabba03a4..14b02fcedb4b 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -542,8 +542,9 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) } weint_data[idx].irq = idx; weint_data[idx].bank = bank; - irq_set_handler_data(irq, &weint_data[idx]); - irq_set_chained_handler(irq, exynos_irq_eint0_15); + irq_set_chained_handler_and_data(irq, + exynos_irq_eint0_15, + &weint_data[idx]); } } -- cgit v1.2.3 From 1aa74fd0bb2cc344c18a625fa1d8e75c00b9bbf8 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:41 +0200 Subject: pinctrl/bcm2835: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index efcf2a2b3975..104d8a63bbce 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -584,9 +584,9 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(data->irq, handle_edge_irq); + irq_set_handler_locked(data, handle_edge_irq); else - __irq_set_handler_locked(data->irq, handle_level_irq); + irq_set_handler_locked(data, handle_level_irq); spin_unlock_irqrestore(&pc->irq_lock[bank], flags); -- cgit v1.2.3 From f3a085b4174e5806e2e6543323f9a70435ca0098 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:44 +0200 Subject: pinctrl/baytrail: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/intel/pinctrl-baytrail.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 2062c224e32f..8834fa9df87f 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -265,9 +265,9 @@ static int byt_irq_type(struct irq_data *d, unsigned type) writel(value, reg); if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); else if (type & IRQ_TYPE_LEVEL_MASK) - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); spin_unlock_irqrestore(&vg->lock, flags); -- cgit v1.2.3 From a4e3f7830fb742039c2c24535af931df3d6d2124 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:44 +0200 Subject: pinctrl/cherryview: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/intel/pinctrl-cherryview.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 3f737daa3fd2..ab87f5c5e9df 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1325,7 +1325,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) spin_lock_irqsave(&pctrl->lock, flags); if (!pctrl->intr_lines[intsel]) { - __irq_set_handler_locked(d->irq, handler); + irq_set_handler_locked(d, handler); pctrl->intr_lines[intsel] = offset; } spin_unlock_irqrestore(&pctrl->lock, flags); @@ -1389,9 +1389,9 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type) pctrl->intr_lines[value] = offset; if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); else if (type & IRQ_TYPE_LEVEL_MASK) - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); spin_unlock_irqrestore(&pctrl->lock, flags); -- cgit v1.2.3 From fc756bcd6aadbc59fa7142521729c8d38096ef9c Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:45 +0200 Subject: pinctrl/intel: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/intel/pinctrl-intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index f9ee0d68b288..27e4aa6971d1 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -758,9 +758,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type) writel(value, reg); if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); else if (type & IRQ_TYPE_LEVEL_MASK) - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); spin_unlock_irqrestore(&pctrl->lock, flags); -- cgit v1.2.3 From e0d6a2c6cefc50f123a2386686738820d9a088c6 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:47 +0200 Subject: pinctrl/adi2: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and update was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-adi2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index c3c3d2345fc6..a5976ebc4482 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -427,10 +427,10 @@ static int adi_gpio_irq_type(struct irq_data *d, unsigned int type) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { writel(pintmask, &pint_regs->edge_set); - __irq_set_handler_locked(irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); } else { writel(pintmask, &pint_regs->edge_clear); - __irq_set_handler_locked(irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); } out: -- cgit v1.2.3 From 9d8293147e8a09ac42018cfeb672cc0a3b90f65b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:47 +0200 Subject: pinctrl/amd: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-amd.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index d8e3f7c7fea3..ef72a8a8dc20 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -420,7 +420,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: @@ -428,7 +428,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); break; case IRQ_TYPE_EDGE_BOTH: @@ -436,7 +436,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); break; case IRQ_TYPE_LEVEL_HIGH: @@ -445,7 +445,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); break; case IRQ_TYPE_LEVEL_LOW: @@ -454,7 +454,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); break; case IRQ_TYPE_NONE: -- cgit v1.2.3 From c639845bcb87df4abffab94d72bd165d203c34a1 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:49 +0200 Subject: pinctrl/at91: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-at91.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index a0824477072b..6cec3861dff7 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1444,22 +1444,22 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) switch (type) { case IRQ_TYPE_EDGE_RISING: - __irq_set_handler_locked(d->irq, handle_simple_irq); + irq_set_handler_locked(d, handle_simple_irq); writel_relaxed(mask, pio + PIO_ESR); writel_relaxed(mask, pio + PIO_REHLSR); break; case IRQ_TYPE_EDGE_FALLING: - __irq_set_handler_locked(d->irq, handle_simple_irq); + irq_set_handler_locked(d, handle_simple_irq); writel_relaxed(mask, pio + PIO_ESR); writel_relaxed(mask, pio + PIO_FELLSR); break; case IRQ_TYPE_LEVEL_LOW: - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); writel_relaxed(mask, pio + PIO_LSR); writel_relaxed(mask, pio + PIO_FELLSR); break; case IRQ_TYPE_LEVEL_HIGH: - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); writel_relaxed(mask, pio + PIO_LSR); writel_relaxed(mask, pio + PIO_REHLSR); break; @@ -1468,7 +1468,7 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) * disable additional interrupt modes: * fall back to default behavior */ - __irq_set_handler_locked(d->irq, handle_simple_irq); + irq_set_handler_locked(d, handle_simple_irq); writel_relaxed(mask, pio + PIO_AIMDR); return 0; case IRQ_TYPE_NONE: -- cgit v1.2.3 From 2dbf1bc5a29c5912679d687d2a826f201e75e89d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:50 +0200 Subject: pinctrl/rockchip: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 626a4a6287e8..6e56c962b655 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1555,9 +1555,9 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) spin_unlock_irqrestore(&bank->slock, flags); if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); else - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); spin_lock_irqsave(&bank->slock, flags); irq_gc_lock(gc); -- cgit v1.2.3 From 34c0ad84f316e19f06af3c2764fe20cac110d985 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:51 +0200 Subject: pinctrl/qcom: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 6242af8a42d5..367ddbf518f7 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -734,9 +734,9 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_unlock_irqrestore(&pctrl->lock, flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); return 0; } -- cgit v1.2.3 From 40ec168ace3b963ddf768919ce96461ed885f9c8 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:57 +0200 Subject: pinctrl/exynos: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/samsung/pinctrl-exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 14b02fcedb4b..f402eff2867a 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -148,9 +148,9 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) } if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irqd->irq, handle_edge_irq); + irq_set_handler_locked(irqd, handle_edge_irq); else - __irq_set_handler_locked(irqd->irq, handle_level_irq); + irq_set_handler_locked(irqd, handle_level_irq); con = readl(d->virt_base + reg_con); con &= ~(EXYNOS_EINT_CON_MASK << shift); -- cgit v1.2.3 From f66eb498ff131d52f9c7b73f0a25a5e3b9095528 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 Jun 2015 15:52:57 +0200 Subject: pinctrl/samsung: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Signed-off-by: Thomas Gleixner Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 8 ++++---- drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index 01b43dbfb795..7a77eae60b83 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -131,13 +131,13 @@ static int s3c24xx_eint_get_trigger(unsigned int type) } } -static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) +static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type) { /* Edge- and level-triggered interrupts need different handlers */ if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); else - __irq_set_handler_locked(irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); } static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, @@ -181,7 +181,7 @@ static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) return -EINVAL; } - s3c24xx_eint_set_handler(data->irq, type); + s3c24xx_eint_set_handler(data, type); /* Set up interrupt trigger */ reg = d->virt_base + EINT_REG(index); diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index ec8cc3b47621..41050f4c67dc 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -260,13 +260,13 @@ static int s3c64xx_irq_get_trigger(unsigned int type) return trigger; } -static void s3c64xx_irq_set_handler(unsigned int irq, unsigned int type) +static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type) { /* Edge- and level-triggered interrupts need different handlers */ if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); else - __irq_set_handler_locked(irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); } static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, @@ -356,7 +356,7 @@ static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) return -EINVAL; } - s3c64xx_irq_set_handler(irqd->irq, type); + s3c64xx_irq_set_handler(irqd, type); /* Set up interrupt trigger */ reg = d->virt_base + EINTCON_REG(bank->eint_offset); @@ -567,7 +567,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) return -EINVAL; } - s3c64xx_irq_set_handler(irqd->irq, type); + s3c64xx_irq_set_handler(irqd, type); /* Set up interrupt trigger */ reg = d->virt_base + EINT0CON0_REG; -- cgit v1.2.3 From 5663bb27dec1a2bfaf9d92e3685834b91a36a5a3 Mon Sep 17 00:00:00 2001 From: Jiang Liu Date: Thu, 4 Jun 2015 12:13:16 +0800 Subject: pinctrl: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we already have a pointer to corresponding irq_desc. Signed-off-by: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org Signed-off-by: Thomas Gleixner --- drivers/pinctrl/intel/pinctrl-cherryview.c | 2 +- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++-- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 12 +++++------- drivers/pinctrl/pinctrl-amd.c | 2 +- drivers/pinctrl/pinctrl-at91.c | 2 +- drivers/pinctrl/pinctrl-coh901.c | 4 ++-- drivers/pinctrl/pinctrl-rockchip.c | 4 ++-- drivers/pinctrl/pinctrl-single.c | 2 +- drivers/pinctrl/pinctrl-st.c | 6 +++--- drivers/pinctrl/qcom/pinctrl-msm.c | 2 +- drivers/pinctrl/samsung/pinctrl-exynos.c | 8 ++++---- drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 18 +++++++++--------- drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 22 ++++++++++------------ drivers/pinctrl/sirf/pinctrl-sirf.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 4 ++-- 16 files changed, 46 insertions(+), 50 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index ab87f5c5e9df..f9a476765736 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1412,7 +1412,7 @@ static void chv_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; u32 intr_line; diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 27e4aa6971d1..bb377c110541 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -840,7 +840,7 @@ static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); int i; chained_irq_enter(chip, desc); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index ad1ea1695b4a..4be0124e9936 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1118,8 +1118,8 @@ mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); - struct mtk_pinctrl *pctl = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc); unsigned int status, eint_num; int offset, index, virq; const struct mtk_eint_offsets *eint_offsets = diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 809d88445db5..56e79c12562e 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -843,10 +843,9 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d) clk_disable(nmk_chip->clk); } -static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, - u32 status) +static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) { - struct irq_chip *host_chip = irq_get_chip(irq); + struct irq_chip *host_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); chained_irq_enter(host_chip, desc); @@ -871,17 +870,16 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) status = readl(nmk_chip->addr + NMK_GPIO_IS); clk_disable(nmk_chip->clk); - __nmk_gpio_irq_handler(irq, desc, status); + __nmk_gpio_irq_handler(desc, status); } -static void nmk_gpio_latent_irq_handler(unsigned int irq, - struct irq_desc *desc) +static void nmk_gpio_latent_irq_handler(unsigned int irq, struct irq_desc *desc) { struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); u32 status = nmk_chip->get_latent_status(nmk_chip->bank); - __nmk_gpio_irq_handler(irq, desc, status); + __nmk_gpio_irq_handler(desc, status); } /* I/O Functions */ diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index ef72a8a8dc20..2663a055546e 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -501,7 +501,7 @@ static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) u64 reg64; int handled = 0; unsigned long flags; - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct amd_gpio *gpio_dev = to_amd_gpio(gc); diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 6cec3861dff7..e1ab69928bba 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1596,7 +1596,7 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, struct at91_gpio_chip, chip); diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 29cbbab8c3a6..9579442a221d 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -521,8 +521,8 @@ static struct irq_chip u300_gpio_irqchip = { static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct irq_chip *parent_chip = irq_get_chip(irq); - struct gpio_chip *chip = irq_get_handler_data(irq); + struct irq_chip *parent_chip = irq_desc_get_chip(desc); + struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct u300_gpio *gpio = to_u300_gpio(chip); struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; int pinoffset = port->number << 3; /* get the right stride */ diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 6e56c962b655..28f9d08faf27 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1471,8 +1471,8 @@ static const struct gpio_chip rockchip_gpiolib_chip = { static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); - struct rockchip_pin_bank *bank = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); u32 pend; dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 07661c86f7ef..b8aaf9559ddd 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1684,7 +1684,7 @@ static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc) struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); struct irq_chip *chip; - chip = irq_get_chip(irq); + chip = irq_desc_get_chip(desc); chained_irq_enter(chip, desc); pcs_irq_handle(pcs_soc); /* REVISIT: export and add handle_bad_irq(irq, desc)? */ diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index c262e5f35c28..f8338d2e6b6b 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1463,7 +1463,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank) static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { /* interrupt dedicated per bank */ - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct st_gpio_bank *bank = gpio_chip_to_bank(gc); @@ -1474,8 +1474,8 @@ static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); - struct st_pinctrl *info = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct st_pinctrl *info = irq_desc_get_handler_data(desc); unsigned long status; int n; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 367ddbf518f7..3fd39921b3e8 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -770,7 +770,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) struct gpio_chip *gc = irq_desc_get_handler_data(desc); const struct msm_pingroup *g; struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); int irq_pin; int handled = 0; u32 val; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index f402eff2867a..07773c70c12c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -422,9 +422,9 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { /* interrupt handler for wakeup interrupts 0..15 */ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) { - struct exynos_weint_data *eintd = irq_get_handler_data(irq); + struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); struct samsung_pin_bank *bank = eintd->bank; - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); int eint_irq; chained_irq_enter(chip, desc); @@ -454,8 +454,8 @@ static inline void exynos_irq_demux_eint(unsigned long pend, /* interrupt handler for wakeup interrupt 16 */ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); - struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; unsigned long pend; unsigned long mask; diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index 7a77eae60b83..5d7b6112fc7e 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -243,7 +243,7 @@ static struct irq_chip s3c2410_eint0_3_chip = { static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); - struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc); unsigned int virq; /* the first 4 eints have a simple 1 to 1 mapping */ @@ -297,9 +297,9 @@ static struct irq_chip s3c2412_eint0_3_chip = { static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); + struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc); struct irq_data *data = irq_desc_get_irq_data(desc); - struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_data_get_irq_chip(data); unsigned int virq; chained_irq_enter(chip, desc); @@ -357,11 +357,11 @@ static struct irq_chip s3c24xx_eint_chip = { .irq_set_type = s3c24xx_eint_type, }; -static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, +static inline void s3c24xx_demux_eint(struct irq_desc *desc, u32 offset, u32 range) { - struct irq_chip *chip = irq_get_chip(irq); - struct s3c24xx_eint_data *data = irq_get_handler_data(irq); + struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_irq_chip(desc); struct samsung_pinctrl_drv_data *d = data->drvdata; unsigned int pend, mask; @@ -374,7 +374,7 @@ static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, pend &= range; while (pend) { - unsigned int virq; + unsigned int virq, irq; irq = __ffs(pend); pend &= ~(1 << irq); @@ -390,12 +390,12 @@ static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) { - s3c24xx_demux_eint(irq, desc, 0, 0xf0); + s3c24xx_demux_eint(desc, 0, 0xf0); } static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) { - s3c24xx_demux_eint(irq, desc, 8, 0xffff00); + s3c24xx_demux_eint(desc, 8, 0xffff00); } static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index 41050f4c67dc..8700f0c9eee1 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -410,8 +410,8 @@ static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = { static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); - struct s3c64xx_eint_gpio_data *data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc); struct samsung_pinctrl_drv_data *drvdata = data->drvdata; chained_irq_enter(chip, desc); @@ -599,11 +599,10 @@ static struct irq_chip s3c64xx_eint0_irq_chip = { .irq_set_type = s3c64xx_eint0_irq_set_type, }; -static inline void s3c64xx_irq_demux_eint(unsigned int irq, - struct irq_desc *desc, u32 range) +static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range) { - struct irq_chip *chip = irq_get_chip(irq); - struct s3c64xx_eint0_data *data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc); struct samsung_pinctrl_drv_data *drvdata = data->drvdata; unsigned int pend, mask; @@ -616,11 +615,10 @@ static inline void s3c64xx_irq_demux_eint(unsigned int irq, pend &= range; while (pend) { - unsigned int virq; + unsigned int virq, irq; irq = fls(pend) - 1; pend &= ~(1 << irq); - virq = irq_linear_revmap(data->domains[irq], data->pins[irq]); /* * Something must be really wrong if an unmapped EINT @@ -636,22 +634,22 @@ static inline void s3c64xx_irq_demux_eint(unsigned int irq, static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc) { - s3c64xx_irq_demux_eint(irq, desc, 0xf); + s3c64xx_irq_demux_eint(desc, 0xf); } static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc) { - s3c64xx_irq_demux_eint(irq, desc, 0xff0); + s3c64xx_irq_demux_eint(desc, 0xff0); } static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc) { - s3c64xx_irq_demux_eint(irq, desc, 0xff000); + s3c64xx_irq_demux_eint(desc, 0xff000); } static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc) { - s3c64xx_irq_demux_eint(irq, desc, 0xff00000); + s3c64xx_irq_demux_eint(desc, 0xff00000); } static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = { diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 8ba26e45499a..9455a2acf6c6 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -552,7 +552,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) struct sirfsoc_gpio_bank *bank; u32 status, ctrl; int idx = 0; - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); int i; for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index f09573e13203..4b1a35cc5578 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -711,8 +711,8 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip = { static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_get_chip(irq); - struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); unsigned long bank, reg, val; for (bank = 0; bank < pctl->desc->irq_banks; bank++) -- cgit v1.2.3 From fa00fecc16acd80b455f14803ad35195cdcef65d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:48:51 +0200 Subject: pinctrl/amd: Prepare amd_gpio_irq_handler for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 2663a055546e..5e86bb8ca80e 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -492,8 +492,9 @@ static struct irq_chip amd_gpio_irqchip = { .irq_set_type = amd_gpio_irq_set_type, }; -static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void amd_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); u32 i; u32 off; u32 reg; -- cgit v1.2.3 From fc02a46938fa2dd2494e20ca7b81c687bd027df4 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:50:02 +0200 Subject: pinctrl/coh901: Prepare u300_gpio_irq_handler for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-coh901.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 9579442a221d..3731cc67a88b 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -519,8 +519,9 @@ static struct irq_chip u300_gpio_irqchip = { .irq_set_type = u300_gpio_irq_type, }; -static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void u300_gpio_irq_handler(unsigned __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); struct irq_chip *parent_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct u300_gpio *gpio = to_u300_gpio(chip); -- cgit v1.2.3 From f43ebaf126d3f4b869ba5bcfb11a00f33f0892cf Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:50:50 +0200 Subject: pinctrl/pistachio: Prepare pistachio_gpio_irq_handler for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-pistachio.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 63100be81015..3dc2ae15f3a1 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -1310,9 +1310,11 @@ static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type) return 0; } -static void pistachio_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void pistachio_gpio_irq_handler(unsigned int __irq, + struct irq_desc *desc) { - struct gpio_chip *gc = irq_get_handler_data(irq); + unsigned int irq = irq_desc_get_irq(desc); + struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct pistachio_gpio_bank *bank = gc_to_bank(gc); struct irq_chip *chip = irq_get_chip(irq); unsigned long pending; -- cgit v1.2.3 From 415f748c8658033d37af520dfa321a9413b7d665 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:52:00 +0200 Subject: pinctrl/rockchip: Prepare rockchip_irq_demux for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/pinctrl-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 28f9d08faf27..cc2843a1f38c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1469,7 +1469,7 @@ static const struct gpio_chip rockchip_gpiolib_chip = { * Interrupt handling */ -static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) +static void rockchip_irq_demux(unsigned int __irq, struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); @@ -1482,7 +1482,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); while (pend) { - unsigned int virq; + unsigned int irq, virq; irq = __ffs(pend); pend &= ~BIT(irq); -- cgit v1.2.3 From d1800c234703465b1f0b75aba51e27d7a3f47060 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:53:06 +0200 Subject: pinctrl/qcom/msm: Prepare msm_gpio_irq_handler for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/qcom/pinctrl-msm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 3fd39921b3e8..492cdd51dc5c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -765,8 +765,9 @@ static struct irq_chip msm_gpio_irq_chip = { .irq_set_wake = msm_gpio_irq_set_wake, }; -static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void msm_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); const struct msm_pingroup *g; struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); -- cgit v1.2.3 From 3b0d1561ea5787a40b2f014d4f3dc48a575c3675 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:54:35 +0200 Subject: pinctrl/sirf: Prepare xxx_gpio-handle_irq for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/sirf/pinctrl-atlas7.c | 5 +++-- drivers/pinctrl/sirf/pinctrl-sirf.c | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index d6e80fe1c7f7..0cd945c3af67 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -4286,14 +4286,15 @@ static struct irq_chip atlas7_gpio_irq_chip = { .irq_set_type = atlas7_gpio_irq_type, }; -static void atlas7_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) +static void atlas7_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); struct atlas7_gpio_bank *bank = NULL; u32 status, ctrl; int pin_in_bank = 0, idx; - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int irq = irq_desc_get_irq(desc); for (idx = 0; idx < a7gc->nbank; idx++) { bank = &a7gc->banks[idx]; diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 9455a2acf6c6..f8bd9fb52033 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -545,8 +545,9 @@ static struct irq_chip sirfsoc_irq_chip = { .irq_set_type = sirfsoc_gpio_irq_type, }; -static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) +static void sirfsoc_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); struct sirfsoc_gpio_bank *bank; -- cgit v1.2.3 From eeef97b182fcbd4e32803be4f0b369d51e4c8535 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 13 Jul 2015 01:55:27 +0200 Subject: pinctrl/sunxi: Prepare sunxi_pinctrl_irq_handler for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 4b1a35cc5578..3e905480ec56 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -709,8 +709,9 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip = { IRQCHIP_EOI_IF_HANDLED, }; -static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) +static void sunxi_pinctrl_irq_handler(unsigned __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); unsigned long bank, reg, val; -- cgit v1.2.3 From 6de52c15132f6b86030bf3159020e3314ec14952 Mon Sep 17 00:00:00 2001 From: kbuild test robot Date: Fri, 17 Jul 2015 21:37:09 +0800 Subject: pinctrl: pinconf: pinconf_show_config() can be static Signed-off-by: Fengguang Wu Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index cbf26a6992a0..078e58d74fc0 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -202,7 +202,7 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) #ifdef CONFIG_DEBUG_FS -void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, +static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, unsigned long *configs, unsigned num_configs) { const struct pinconf_ops *confops; -- cgit v1.2.3