From 9d0554fff9a21d846adcfbd14cfb02e82773162c Mon Sep 17 00:00:00 2001 From: Jonghwan Choi Date: Sun, 23 Dec 2012 15:57:42 -0800 Subject: cpufreq: exynos: Use APLL_FREQ macro for cpu divider value Signed-off-by: Jonghwan Choi Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/cpufreq.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h index 39f0dc62122b..b5d39dd03b2a 100644 --- a/arch/arm/mach-exynos/include/mach/cpufreq.h +++ b/arch/arm/mach-exynos/include/mach/cpufreq.h @@ -18,6 +18,22 @@ enum cpufreq_level_index { L20, }; +#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \ + { \ + .freq = (f) * 1000, \ + .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \ + (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \ + .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \ + .mps = ((m) << 16 | (p) << 8 | (s)), \ + } + +struct apll_freq { + unsigned int freq; + u32 clk_div_cpu0; + u32 clk_div_cpu1; + u32 mps; +}; + struct exynos_dvfs_info { unsigned long mpll_freq_khz; unsigned int pll_safe_idx; -- cgit v1.2.3