diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-01-19 15:42:09 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-02-07 15:47:32 +0000 |
| commit | dd13df9b33b31850f2a57aecd042479f91594cde (patch) | |
| tree | ba160d76162e25be0fe1d901742657a75e429499 | |
| parent | e139ba142e92880a2b84741943d12205c6acbbac (diff) | |
[Variant 2/Spectre-v2] arm64: Move BP hardening to check_and_switch_context
Commit a8e4c0a919ae upstream.
We call arm64_apply_bp_hardening() from post_ttbr_update_workaround,
which has the unexpected consequence of being triggered on every
exception return to userspace when ARM64_SW_TTBR0_PAN is selected,
even if no context switch actually occured.
This is a bit suboptimal, and it would be more logical to only
invalidate the branch predictor when we actually switch to
a different mm.
In order to solve this, move the call to arm64_apply_bp_hardening()
into check_and_switch_context(), where we're guaranteed to pick
a different mm context.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | arch/arm64/mm/context.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index d99b36555a16..b1ac80fba578 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -231,6 +231,9 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: + + arm64_apply_bp_hardening(); + /* * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when * emulating PAN. @@ -246,8 +249,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); - - arm64_apply_bp_hardening(); } static int asids_init(void) |