diff options
author | Kevin Hilman <khilman@linaro.org> | 2015-08-14 09:45:22 -0700 |
---|---|---|
committer | Kevin Hilman <khilman@linaro.org> | 2015-08-14 09:55:00 -0700 |
commit | 4dddf720534a9a14fa9b048e7930dcc55b1b1e40 (patch) | |
tree | 6dead0bf02a9c08038d3238b1599823a25d9e881 /arch/arm/mach-mvebu | |
parent | a93bdb5f55d343fb51892050ed49da9d476da18a (diff) | |
parent | 07818b5b1ba0f494a7255ab634bad2dd2b908ed0 (diff) |
Merge branch 'linux-linaro-lsk-v3.10' into linux-linaro-lsk-v3.10-androidlsk-v3.10-15.08-android
Conflicts:
fs/exec.c
Resolution summary:
Conflict between upstream/LTS commit 9eae8ac6ab40 (fs: take
i_mutex during prepare_binprm for set[ug]id executables) and
android commit 9d0ff694bc22 (sched: move no_new_privs into new
atomic flags). Resolution: move task_no_new_privs() usage into
new function created by upstream/LTS comit.
Diffstat (limited to 'arch/arm/mach-mvebu')
-rw-r--r-- | arch/arm/mach-mvebu/armada-370-xp.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/coherency.c | 15 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/coherency.h | 1 |
3 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 1c48890bb72b..4377c3484a62 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -66,7 +66,8 @@ void __init armada_370_xp_init_early(void) ARMADA_370_XP_MBUS_WINS_BASE, ARMADA_370_XP_MBUS_WINS_SIZE, ARMADA_370_XP_SDRAM_WINS_BASE, - ARMADA_370_XP_SDRAM_WINS_SIZE); + ARMADA_370_XP_SDRAM_WINS_SIZE, + coherency_available()); #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 3ee701f1d38e..ea26ebb5bb5a 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -137,6 +137,20 @@ static struct notifier_block mvebu_hwcc_platform_nb = { .notifier_call = mvebu_hwcc_platform_notifier, }; +/* + * Keep track of whether we have IO hardware coherency enabled or not. + * On Armada 370's we will not be using it for example. We need to make + * that available [through coherency_available()] so the mbus controller + * doesn't enable the IO coherency bit in the attribute bits of the + * chip selects. + */ +static int coherency_enabled; + +int coherency_available(void) +{ + return coherency_enabled; +} + int __init coherency_init(void) { struct device_node *np; @@ -170,6 +184,7 @@ int __init coherency_init(void) coherency_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 1); set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); + coherency_enabled = 1; bus_register_notifier(&platform_bus_type, &mvebu_hwcc_platform_nb); } diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index 2f428137f6fe..1501a4e5eea0 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -19,6 +19,7 @@ int coherency_get_cpu_count(void); #endif int set_cpu_coherent(int cpu_id, int smp_group_id); +int coherency_available(void); int coherency_init(void); #endif /* __MACH_370_XP_COHERENCY_H */ |