diff options
| author | Viresh Kumar <viresh.kumar@st.com> | 2012-04-11 18:04:23 +0530 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-12 21:19:27 +0200 |
| commit | a45896bd3a4b7beb571fa704efa7c2782b791093 (patch) | |
| tree | abbcf23625304e123839af8af6e5ba278d20797e /drivers/clk/spear/clk.h | |
| parent | 270b9f421e66ee5d135c99ba1c2b883c7750ab6c (diff) | |
SPEAr: clk: Add General Purpose Timer Synthesizer clock
All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:
Fout= Fin/((2 ^ (N+1)) * (M+1))
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/spear/clk.h')
| -rw-r--r-- | drivers/clk/spear/clk.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h index ac9030bbd6ce..3321c46a071c 100644 --- a/drivers/clk/spear/clk.h +++ b/drivers/clk/spear/clk.h @@ -68,6 +68,20 @@ struct clk_frac { spinlock_t *lock; }; +/* GPT clk */ +struct gpt_rate_tbl { + u16 mscale; + u16 nscale; +}; + +struct clk_gpt { + struct clk_hw hw; + void __iomem *reg; + struct gpt_rate_tbl *rtbl; + u8 rtbl_cnt; + spinlock_t *lock; +}; + /* VCO-PLL clk */ struct pll_rate_tbl { u8 mode; @@ -103,6 +117,9 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, struct clk *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); +struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned + long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 + rtbl_cnt, spinlock_t *lock); struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem |