diff options
| author | Gustavo Padovan <gustavo.padovan@collabora.co.uk> | 2015-04-01 13:02:05 -0300 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2015-04-13 11:39:39 +0900 |
| commit | 453b44a3f6f3f43f50387a9af27c5356c273e831 (patch) | |
| tree | 403d076fa884eabc865d4540a822c9c357573d4b /drivers/gpu/drm/exynos | |
| parent | 1d8ac08d498d579aae36221a80b4b724b2f52f39 (diff) | |
drm/exynos: fimd: fix alpha setting for XR24 pixel format
XR24 planes were not shown properly, so now set the right registers
to correctly enable displaying these planes.
It also moves the alpha register settings to fimd_win_set_pixfmt()
to keep all pixel format stuff together.
v2: remove leftover var alpha
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_fimd.c | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 33a10ce967ea..6f51d3d7ef6f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -54,6 +54,9 @@ /* size control register for hardware windows 1 ~ 2. */ #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) +#define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) +#define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) + #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) @@ -620,6 +623,24 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) } writel(val, ctx->regs + WINCON(win)); + + /* hardware window 0 doesn't support alpha channel. */ + if (win != 0) { + /* OSD alpha */ + val = VIDISD14C_ALPHA0_R(0xf) | + VIDISD14C_ALPHA0_G(0xf) | + VIDISD14C_ALPHA0_B(0xf) | + VIDISD14C_ALPHA1_R(0xf) | + VIDISD14C_ALPHA1_G(0xf) | + VIDISD14C_ALPHA1_B(0xf); + + writel(val, ctx->regs + VIDOSD_C(win)); + + val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | + VIDW_ALPHA_G(0xf); + writel(val, ctx->regs + VIDWnALPHA0(win)); + writel(val, ctx->regs + VIDWnALPHA1(win)); + } } static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) @@ -667,7 +688,7 @@ static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos) struct fimd_context *ctx = crtc->ctx; struct fimd_win_data *win_data; int win = zpos; - unsigned long val, alpha, size; + unsigned long val, size; unsigned int last_x; unsigned int last_y; @@ -744,16 +765,6 @@ static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos) DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", win_data->offset_x, win_data->offset_y, last_x, last_y); - /* hardware window 0 doesn't support alpha channel. */ - if (win != 0) { - /* OSD alpha */ - alpha = VIDISD14C_ALPHA1_R(0xf) | - VIDISD14C_ALPHA1_G(0xf) | - VIDISD14C_ALPHA1_B(0xf); - - writel(alpha, ctx->regs + VIDOSD_C(win)); - } - /* OSD size */ if (win != 3 && win != 4) { u32 offset = VIDOSD_D(win); |