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author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2014-04-02 21:31:50 +0800 |
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committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2014-05-07 16:55:48 +0400 |
commit | fd03ee933c8768bc2a60a9ea55f0730bfe23bed1 (patch) | |
tree | 586893375195db558026214be42f2bc821f67f1d | |
parent | d024fa269e1a3f869a09e709feacab52bf6d9726 (diff) |
ARM: dts: fix L2 address in Hi3620
Fix the address of L2 controler register in hi3620 SoC.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
-rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index c227a221943f..6836795040ad 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -73,7 +73,7 @@ L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0xfc10000 0x100000>; + reg = <0x100000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>; |