diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2014-07-09 10:14:00 +0100 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2014-09-30 22:27:56 +0400 |
| commit | c3a1712c0e458ed7d3333011fe3f394ec3863a2a (patch) | |
| tree | 47390beedd6f7b5932753151890fc7d78b576bfb | |
| parent | a0cca0c4e6677c6d8181d03984c9105ac7d55b63 (diff) | |
pci: qcom: move device init to subsys_initcall_sync
This patch moves device init call from subsys_initcall to its sync
variant. This is required because most of the dependent regulators
drivers comeup at subsys_initcall level and this will result in defer
probe of this driver. This behaviour will have an side effect of pci
devices being probed at pci_scan_root_bus call, which means before the
bus resources are actually allocated. moving to subsys_initcall_sync
call will ensure that all the subsys_initcall level calls are finished
before invoking the deivce init.
Originally found while testing atl1c driver on IFC6410 board.
[ 0.281558] qcom_pcie 1b500000.pci: Failed to get vdd supply
[ 0.286396] platform 1b500000.pci: Driver qcom_pcie requests probe deferral
...
[ 1.804406] PCI host bridge to bus 0000:00
[ 1.806090] pci_bus 0000:00: root bus resource [mem 0x08000000-0x0fdfffff]
[ 1.810247] pci_bus 0000:00: root bus resource [io 0xfe00000-0xfefffff]
[ 1.817105] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
[ 1.824023] pci 0000:00:00.0: [17cb:0101] type 01 class 0xff0000
[ 1.832008] pci 0000:00:00.0: supports D1
[ 1.837829] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 1.842170] PCI: bus0: Fast back to back transfers disabled
[ 1.847485] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.853206] pci 0000:01:00.0: [1969:1083] type 00 class 0x020000
[ 1.860920] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x0003ffff 64bit]
[ 1.867123] pci 0000:01:00.0: reg 0x18: [io 0x0000-0x007f]
[ 1.874105] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.879499] PCI: bus1: Fast back to back transfers disabled
[ 1.885777] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 1.891336] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
[ 1.898325] atl1c 0000:01:00.0: can't enable device: BAR 0 [mem 0x00000000-0x0003ffff 64bit] not claimed
[ 1.904509] atl1c 0000:01:00.0: cannot enable PCI device
[ 1.914232] atl1c: probe of 0000:01:00.0 failed with error -22
[ 1.919630] pci 0000:00:00.0: BAR 8: assigned [mem 0x08000000-0x080fffff]
[ 1.925172] pci 0000:00:00.0: BAR 7: assigned [io 0xfe00000-0xfe00fff]
[ 1.932044] pci 0000:01:00.0: BAR 0: assigned [mem 0x08000000-0x0803ffff 64bit]
[ 1.938488] pci 0000:01:00.0: BAR 2: assigned [io 0xfe00000-0xfe0007f]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
| -rw-r--r-- | drivers/pci/host/pci-qcom.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-qcom.c b/drivers/pci/host/pci-qcom.c index 63086bbcc5fc..67d3a497a13a 100644 --- a/drivers/pci/host/pci-qcom.c +++ b/drivers/pci/host/pci-qcom.c @@ -957,7 +957,7 @@ static int qcom_pcie_init(void) { return platform_driver_register(&qcom_pcie_driver); } -subsys_initcall(qcom_pcie_init); +subsys_initcall_sync(qcom_pcie_init); /* RC do not represent the right class; set it to PCI_CLASS_BRIDGE_PCI */ static void msm_pcie_fixup_early(struct pci_dev *dev) |