diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2014-07-08 14:17:27 +0100 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2014-10-08 21:04:56 +0400 |
| commit | 11fffde0fe0ff53ed958818b54536096edefc402 (patch) | |
| tree | 64c6505dcaffc1a53f8e4eb229ff08e420d95c09 | |
| parent | 52e5f361e1692d4cbc9fd60e1517115cfa046e8c (diff) | |
pci: qcom: Add support to external phy reference clk.
This patch adds support to configuration which use external phy reference clk,
this option is now available via dt using "qcom,external-phy-refclk" property.
Without this option the driver will always configure the phy to use
internal clk which will not work for SOCs like APQ8064 which uses
external phy reference clock on IFC6410 board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
| -rw-r--r-- | drivers/pci/host/pci-qcom.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-qcom.c b/drivers/pci/host/pci-qcom.c index 5b49bfde3351..38d14c0040d2 100644 --- a/drivers/pci/host/pci-qcom.c +++ b/drivers/pci/host/pci-qcom.c @@ -110,6 +110,7 @@ struct qcom_pcie { void __iomem *cfg_base; struct device *dev; int reset_gpio; + bool ext_phy_ref_clk; struct clk *iface_clk; struct clk *bus_clk; struct clk *phy_clk; @@ -458,6 +459,9 @@ static int qcom_pcie_parse_dt(struct qcom_pcie *qcom_pcie, struct of_pci_range_parser parser; int ret, i; + qcom_pcie->ext_phy_ref_clk = of_property_read_bool(np, + "qcom,external-phy-refclk"); + elbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); qcom_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base); if (IS_ERR(qcom_pcie->elbi_base)) { @@ -667,7 +671,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) /* enable reference clock */ msm_pcie_write_mask(qcom_pcie->parf_base + PCIE20_PARF_PHY_REFCLK, - BIT(12), BIT(16)); + qcom_pcie->ext_phy_ref_clk ? 0 : BIT(12), + BIT(16)); /* ensure that access is enabled before proceeding */ wmb(); |