diff options
| author | Lina Iyer <lina.iyer@linaro.org> | 2014-09-04 16:35:32 -0600 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2014-10-08 21:04:53 +0400 |
| commit | d38cd2de08b7e32c99e319eafc384c4de6773ba4 (patch) | |
| tree | 81d789bb4a0767dabc4cba497111d1ef30893bd4 | |
| parent | 0f58262af27c996e195bcfc5612715d7949e9e6f (diff) | |
arm: dts: qcom: Add idle states device nodes for 8974
Add allowable C-States for each cpu using the cpu-idle-states node.
ARM spec dictates WFI as the default idle state at 0. Support standalone
power collapse (power down that does not affect any SoC idle states) for
each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 875bbdcbb5dc..b2d01e4ca0e3 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -24,6 +24,7 @@ clocks = <&kraitcc 0>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU1: cpu@1 { @@ -36,6 +37,7 @@ clocks = <&kraitcc 1>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU2: cpu@2 { @@ -48,6 +50,7 @@ clocks = <&kraitcc 2>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU3: cpu@3 { @@ -60,6 +63,7 @@ clocks = <&kraitcc 3>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; L2: l2-cache { @@ -67,6 +71,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_WFI: cpu-idle-state-0 { + compatible = "qcom,idle-state-wfi", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: cpu-idle-state-1 { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { |