diff options
| author | Andy Gross <agross@codeaurora.org> | 2015-08-05 22:52:44 -0500 |
|---|---|---|
| committer | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2015-09-03 15:15:48 +0100 |
| commit | 61ffd876b6ec0049234830c9e0fad7ad3da8acab (patch) | |
| tree | 761e13f8e3b67e0d111a41af6573077f8802fa64 | |
| parent | 54b86fbd4700a6f5b91a13cd5469becfbc882b96 (diff) | |
firmware: qcom: scm: Fixup arm64 asmtracking-integration-linux-qcomlt-ll-20150912.0tracking-integration-linux-qcomlt-ll-20150911.0tracking-integration-linux-qcomlt-ll-20150909.0
This fixes an issue with x6 usage in scm calls.
Signed-off-by: Andy Gross <agross@codeaurora.org>
| -rw-r--r-- | drivers/firmware/qcom_scm-64.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 08525886cf10..8f7a36674511 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -106,6 +106,7 @@ static DEFINE_MUTEX(qcom_scm_lock); #define R3_STR "x3" #define R4_STR "x4" #define R5_STR "x5" +#define R6_STR "x6" int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, @@ -117,6 +118,7 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, register u64 r3 asm("r3") = x3; register u64 r4 asm("r4") = x4; register u64 r5 asm("r5") = x5; + register u64 r6 asm("r6") = 0; do { asm volatile( @@ -130,14 +132,15 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, __asmeq("%7", R3_STR) __asmeq("%8", R4_STR) __asmeq("%9", R5_STR) + __asmeq("%10", R6_STR) #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), - "r" (r5) - : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", + "r" (r5), "r" (r6) + : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == QCOM_SCM_INTERRUPTED); @@ -160,6 +163,7 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, register u32 r3 asm("r3") = w3; register u32 r4 asm("r4") = w4; register u32 r5 asm("r5") = w5; + register u32 r6 asm("r6") = 0; do { asm volatile( @@ -173,14 +177,15 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, __asmeq("%7", R3_STR) __asmeq("%8", R4_STR) __asmeq("%9", R5_STR) + __asmeq("%10", R6_STR) #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), - "r" (r5) - : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", + "r" (r5), "r" (r6) + : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == QCOM_SCM_INTERRUPTED); |