diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-07-29 10:17:53 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-11-26 09:43:23 +0100 |
| commit | 4f4f85fa0b96a35429ebb4bc278d70ae0f72113c (patch) | |
| tree | 566618d20763f01c8a8b66fa1fe5f621373c4123 /drivers/clk/tegra/clk.h | |
| parent | 7f06dd61248a75668bbb39b6fcca6ff407745df8 (diff) | |
clk: tegra: Implement memory-controller clock
The memory controller clock runs either at half or the same frequency as
the EMC clock.
Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 16ec8d6bb87f..4e458aa8d45c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -86,6 +86,8 @@ struct clk *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); +struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, + void __iomem *reg, spinlock_t *lock); /* * Tegra PLL: |