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author | Andrey Konovalov <andrey.konovalov@linaro.org> | 2015-10-08 21:58:05 +0300 |
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committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2015-10-08 21:58:05 +0300 |
commit | af31ff8a1496c68089c3a2ff50d45c64ec765d34 (patch) | |
tree | 5671465bb6ba3a17b66ce04eb7fab4220c70a73b /drivers/iommu/qcom/Kconfig | |
parent | 535f95d0a6164c60f3c34a0864d653e016decde1 (diff) | |
parent | 52bddd7cb59adbc9ce56ebd03ad63936cf7cd1e5 (diff) |
Automatically merging tracking-integration-linux-qcomlt into merge-linux-linaroll-20151008.0ll_20151008.0
Conflicting files:
arch/arm64/configs/defconfig
Diffstat (limited to 'drivers/iommu/qcom/Kconfig')
-rw-r--r-- | drivers/iommu/qcom/Kconfig | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/iommu/qcom/Kconfig b/drivers/iommu/qcom/Kconfig new file mode 100644 index 000000000000..a0e41bb305af --- /dev/null +++ b/drivers/iommu/qcom/Kconfig @@ -0,0 +1,43 @@ +# Qualcomm IOMMU support + +# QCOM IOMMUv1 support +config QCOM_IOMMU_V1 + bool "Qualcomm IOMMUv1 Support" + depends on ARCH_QCOM + select IOMMU_API + select ARM_DMA_USE_IOMMU if ARM + select ARM64_DMA_USE_IOMMU if ARM64 + help + Support for the IOMMUs (v1) found on certain Qualcomm SOCs. + These IOMMUs allow virtualization of the address space used by most + cores within the multimedia subsystem. + + If unsure, say N here. + +config MMU500_ACTIVE_PREFETCH_BUG_WITH_SECTION_MAPPING + bool "Don't align virtual address at 1MB boundary" + depends on QCOM_IOMMU_V1 + help + Say Y here if the MMU500 revision has a bug in active prefetch + which can cause TLB corruptions due to 1MB alignment of a buffer. + Here is the sequence which will surface this BUG. + 1) Create a 2-level mapping in v7S format for 1MB buffer. Start of + the buffer should be at even MB boundary. + 2) Create a section mapping for 1MB buffer adjacent to previous + mapping in step 1. + 3) Access last page from 2 level mapping followed by an access into + section mapped area. + 4) Step 3 will result into TLB corruption and this corruption can + lead to any misbehavior (like Permission fault) for sub-sequent + transactions. + + If unsure, say Y here if IOMMU mapping will not exhaust the VA space. + +config IOMMU_PGTABLES_L2 + bool "Allow SMMU page tables in the L2 cache (Experimental)" + depends on QCOM_IOMMU_V1 && MMU && SMP && CPU_DCACHE_DISABLE=n + help + Improves TLB miss latency at the expense of potential L2 pollution. + However, with large multimedia buffers, the TLB should mostly contain + section mappings and TLB misses should be quite infrequent. + Most people can probably say Y here. |