From 5b7b17f0fb4bf962f89f680e8bb9647d3ef89881 Mon Sep 17 00:00:00 2001 From: Fei Wang Date: Thu, 5 Feb 2015 23:55:05 +0800 Subject: misc: hi6220: Add driver to config some device host chips resided on hi6220 SoC This driver is used to configure the hi6220 SoC to control some device hosts(e.g. UART), reset the host or disable the reset. Signed-off-by: Bintian Wang Conflicts: arch/arm64/Kconfig --- arch/arm64/Kconfig.platforms | 1 + drivers/misc/Kconfig | 8 ++++++ drivers/misc/Makefile | 1 + drivers/misc/hi6220-sysconfig.c | 63 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 drivers/misc/hi6220-sysconfig.c diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6d730fbf00df..bb4b1d043407 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -36,6 +36,7 @@ config ARCH_FSL_LS2085A config ARCH_HISI bool "Hisilicon SoC Family" select ARM_TIMER_SP804 + select HI6220_SYSCFG help This enables support for Hisilicon ARMv8 SoC family diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ccccc2943f2f..ed742d9acc54 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -525,6 +525,14 @@ config VEXPRESS_SYSCFG bus. System Configuration interface is one of the possible means of generating transactions on this bus. +config HI6220_SYSCFG + bool "Hisilicon HI6220 System Configuration driver" + depends on ARCH_HISI + default y + help + Hisilicon HI6220 uses some registers to configure some chip hosts to + work or not, e.g. disable the UART hosts reset and let's them work. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 537d7f3b78da..eeeefbf5e149 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_GENWQE) += genwqe/ obj-$(CONFIG_ECHO) += echo/ obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o obj-$(CONFIG_CXL_BASE) += cxl/ +obj-$(CONFIG_HI6220_SYSCFG) += hi6220-sysconfig.o diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c new file mode 100644 index 000000000000..ef5e017fdfb6 --- /dev/null +++ b/drivers/misc/hi6220-sysconfig.c @@ -0,0 +1,63 @@ +/* + * For Hisilicon Hi6220 SoC, the reset of some hosts (e.g. UART) should be disabled + * before using them, this driver will handle the host chip reset disable. + * + * Copyright (C) 2015 Hisilicon Ltd. + * Author: Bintian Wang + * + */ + +#include +#include + +#define reset_offset 0x334 +#define pclk_offset 0x230 + +static int __init hi6220_sysconf(void) +{ + static void __iomem *base = NULL; + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + if (!node) + return -ENOENT; + + base = of_iomap(node, 0); + if (base == NULL) { + printk(KERN_ERR "hi6220: sysctrl reg iomap failed!\n"); + return -ENOMEM; + } + + /*Disable UART1 reset and set pclk*/ + writel(BIT(5), base + reset_offset); + writel(BIT(5), base + pclk_offset); + + /*Disable UART2 reset and set pclk*/ + writel(BIT(6), base + reset_offset); + writel(BIT(6), base + pclk_offset); + + /*Disable UART3 reset and set pclk*/ + writel(BIT(7), base + reset_offset); + writel(BIT(7), base + pclk_offset); + + /*Disable UART4 reset and set pclk*/ + writel(BIT(8), base + reset_offset); + writel(BIT(8), base + pclk_offset); + + iounmap(base); + + return 0; +} +postcore_initcall(hi6220_sysconf); + +#ifdef CONFIG_ARM64 +#ifdef CONFIG_SPARSE_IRQ +#define NR_IRQS_LEGACY_HI6220 16 + +int __init arch_probe_nr_irqs(void) +{ + return NR_IRQS_LEGACY_HI6220; +} + +#endif +#endif -- cgit v1.2.3 From 82b97194f5e8ae8cc499cb58cc145cbfe29f0fff Mon Sep 17 00:00:00 2001 From: Bintian Wang Date: Tue, 20 Jan 2015 15:33:12 +0800 Subject: misc: disable the reset of microSD and SDIO controller Modify file hi6220-sysconfig.c to diable the reset of microSD and SDIO controller Signed-off-by: Bintian Wang --- drivers/misc/hi6220-sysconfig.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c index ef5e017fdfb6..103691850ca8 100644 --- a/drivers/misc/hi6220-sysconfig.c +++ b/drivers/misc/hi6220-sysconfig.c @@ -44,6 +44,9 @@ static int __init hi6220_sysconf(void) writel(BIT(8), base + reset_offset); writel(BIT(8), base + pclk_offset); + /*unreset microSD*/ + writel(readl(base+0x304) | 0x6, base + 0x304); + iounmap(base); return 0; -- cgit v1.2.3 From bc6563cbd3e2a9c1feeab5aa2ca62d9a11cec2dd Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 30 Jan 2015 11:20:41 +0800 Subject: misc: hi6220: enable PMIC clock output CK32B CK32B is a 32K clock output from PMIC Hi6553. This clock is used by TI WL1835MOD on HiKey board. Signed-off-by: Bintian Wang Signed-off-by: Guodong Xu --- drivers/misc/hi6220-sysconfig.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c index 103691850ca8..db82b8a6ca43 100644 --- a/drivers/misc/hi6220-sysconfig.c +++ b/drivers/misc/hi6220-sysconfig.c @@ -7,18 +7,21 @@ * */ +#include #include #include #define reset_offset 0x334 #define pclk_offset 0x230 +#define PMUSSI_REG_EX(pmu_base, reg_addr) (((reg_addr) << 2) + (char *)pmu_base) static int __init hi6220_sysconf(void) { - static void __iomem *base = NULL; - struct device_node *node; + static void __iomem *base = NULL, *base1 = NULL; + struct device_node *node, *node1; + unsigned char ret; - node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + node = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220-sysctrl"); if (!node) return -ENOENT; @@ -28,6 +31,16 @@ static int __init hi6220_sysconf(void) return -ENOMEM; } + node1 = of_find_compatible_node(NULL, NULL, "hisilicon,hi655x-pmic-driver"); + if (!node1) + return -ENOENT; + + base1 = of_iomap(node1, 0); + if (base1 == NULL) { + printk(KERN_ERR "hi6220: pmic reg iomap failed!\n"); + return -ENOMEM; + } + /*Disable UART1 reset and set pclk*/ writel(BIT(5), base + reset_offset); writel(BIT(5), base + pclk_offset); @@ -47,7 +60,13 @@ static int __init hi6220_sysconf(void) /*unreset microSD*/ writel(readl(base+0x304) | 0x6, base + 0x304); + /*enable clk for BT/WIFI*/ + ret = *(volatile unsigned char*)PMUSSI_REG_EX(base1, 0x1c); + ret |= 0x40; + *(volatile unsigned char*)PMUSSI_REG_EX(base1, 0x1c) = ret; + iounmap(base); + iounmap(base1); return 0; } -- cgit v1.2.3 From 73373d86f15fd12abe0f5e055f54489eda0ede80 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 29 Dec 2014 10:46:21 +0800 Subject: wlcore: make reg_ch_conf_last and _pending 64bit aligned In struct wl1271, make fields reg_ch_conf_last and reg_ch_conf_pending 64bit aligned. Without this, on 64bit ARM, wlcore_set_pending_regdomain_ch() will fail at the point it calls set_bit(ch_bit_idx, (long*)wl->reg_ch_conf_pending); Here is the error message while doing iw wlan0 scan or connect: [ 760.644782] wlcore: WL1271_ACX_INTR_DATA [ 760.648734] Unhandled fault: alignment fault (0x96000021) at 0xffffffc01bdc1b54 [ 760.656048] Internal error: : 96000021 [#1] PREEMPT SMP [ 760.661267] Modules linked in: arc4 wl18xx wlcore mac80211 cfg80211 wlcore_sdio ti_conf_wl18xx btwilink st_drv bluetooth rfkill [ 760.672824] CPU: 0 PID: 1514 Comm: irq/198-wl18xx Tainted: G W 3.10.52-wl-00204-gf704232-dirty #8 [ 760.682558] task: ffffffc01d956040 ti: ffffffc01bea4000 task.ti: ffffffc01bea4000 [ 760.690043] PC is at set_bit+0x14/0x30 [ 760.693806] LR is at wlcore_set_pending_regdomain_ch+0x38/0x44 [wlcore] Signed-off-by: Guodong Xu --- drivers/net/wireless/ti/wlcore/wlcore.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ti/wlcore/wlcore.h b/drivers/net/wireless/ti/wlcore/wlcore.h index a1b6040e6491..2690f4dab246 100644 --- a/drivers/net/wireless/ti/wlcore/wlcore.h +++ b/drivers/net/wireless/ti/wlcore/wlcore.h @@ -318,9 +318,9 @@ struct wl1271 { bool watchdog_recovery; /* Reg domain last configuration */ - u32 reg_ch_conf_last[2]; + u32 reg_ch_conf_last[2] __aligned(8); /* Reg domain pending configuration */ - u32 reg_ch_conf_pending[2]; + u32 reg_ch_conf_pending[2] __aligned(8); /* Pointer that holds DMA-friendly block for the mailbox */ void *mbox; -- cgit v1.2.3 From e7db6c9e633b4c43e6374ff91075290d5e034650 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 17 Aug 2015 17:39:44 +0800 Subject: dts: hikey: add nodes for dwmmc2 and wlcore Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 4241d6c2afcf..62a46ab54aab 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -263,6 +263,47 @@ pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; }; + dwmmc_2: dwmmc2@f723f000 { + compatible = "hisilicon,hi6220-dw-mshc"; + status = "okay"; + num-slots = <0x1>; + reg = <0x0 0xf723f000 0x0 0x1000>; + interrupts = <0x0 0x4a 0x4>; + clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; + clock-names = "ciu", "biu"; + bus-width = <0x4>; + broken-cd; + ti,non-removable; + non-removable; + /* WL_EN */ + vmmc-supply = <&wlan_en_reg>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; + pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + }; + + wlan_en_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* WLAN_EN GPIO */ + gpio = <&gpio0 5 0>; + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; -- cgit v1.2.3 From b9819e528fba2ddd793f4fd9ff59304dd7ece2ad Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 1 Sep 2015 10:21:02 +0800 Subject: defconfig: enable configs for TI WL1835 Signed-off-by: Guodong Xu --- arch/arm64/configs/defconfig | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9fe4ec9acdb3..e6dac77be183 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -69,7 +69,20 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BPF_JIT=y -# CONFIG_WIRELESS is not set +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_DEBUG_MENU=y +CONFIG_RFKILL=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_RFKILL_GPIO=y CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y # CONFIG_TEGRA_AHB is not set @@ -96,7 +109,9 @@ CONFIG_NET_XGENE=y CONFIG_SKY2=y CONFIG_SMC91X=y CONFIG_SMSC911X=y -# CONFIG_WLAN is not set +CONFIG_WL_TI=y +CONFIG_WL18XX=y +CONFIG_WLCORE_SDIO=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_SERIO_SERPORT is not set @@ -156,7 +171,6 @@ CONFIG_MMC_DW_K3=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y -- cgit v1.2.3