From d76dc28a21eaa2663ae140db00b285c435eb9457 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Thu, 19 Dec 2013 19:02:12 +0530 Subject: clk: exynos5420: Enable Gate for sclk_usbphy3* sclk_usbphy3* are the operational clocks used by USB 3.0 PHY on exynos5420 platform, but the same are not handled by the phy-samsung-usb3 driver. So enable the gates for these sclk_usbphy3* for now to make USB 3.0 ports present on smdk5420 working. Signed-off-by: Vivek Gautam Signed-off-by: Tushar Behera --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index ab4f2f7d88ef..79254587988f 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -539,9 +539,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", - GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), + GATE_TOP_SCLK_FSYS, 7, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", - GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), + GATE_TOP_SCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", -- cgit v1.2.3