From 29ef1037aefdac993c5b84ba4270b36deb261a38 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 9 Dec 2014 10:15:24 +0000 Subject: ARM: qcom_defconfig: Add QCOM specific drivers This patch adds common kconfig options required for qcom chips to work. Signed-off-by: Srinivas Kandagatla --- arch/arm/configs/qcom_defconfig | 154 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 147 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index ff7985ba226e..77972a6ca8ad 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -1,8 +1,10 @@ CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS_ALL=y @@ -21,19 +23,36 @@ CONFIG_ARCH_QCOM=y CONFIG_ARCH_MSM8X60=y CONFIG_ARCH_MSM8960=y CONFIG_ARCH_MSM8974=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_STUB=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIEPORTBUS=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CLEANCACHE=y +CONFIG_CMA=y +CONFIG_SECCOMP=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_QCOM_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_QCOM_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -48,25 +67,44 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set -CONFIG_CFG80211=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_M25P80=y CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y +CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SCH=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y +CONFIG_ATL1C=y CONFIG_KS8851=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y @@ -76,6 +114,9 @@ CONFIG_SLIP_MODE_SLIP6=y CONFIG_USB_USBNET=y # CONFIG_USB_NET_AX8817X is not set # CONFIG_USB_NET_ZAURUS is not set +CONFIG_ATH_CARDS=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set @@ -88,7 +129,6 @@ CONFIG_SERIO_LIBPS2=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_HW_RANDOM=y -CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_QUP=y CONFIG_SPI=y @@ -99,18 +139,87 @@ CONFIG_PINCTRL_APQ8084=y CONFIG_PINCTRL_IPQ8064=y CONFIG_PINCTRL_MSM8960=y CONFIG_PINCTRL_MSM8X74=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_QCOM_SSBI_PMIC=y CONFIG_GPIOLIB=y -CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y CONFIG_THERMAL=y CONFIG_MFD_QCOM_RPM=y +CONFIG_CPU_THERMAL=y +CONFIG_QCOM_TSENS=y +CONFIG_WATCHDOG=y +CONFIG_QCOM_WDT=y +CONFIG_MFD_PM8921_CORE=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_SYSCON=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_QCOM_RPM=y CONFIG_MEDIA_SUPPORT=y -CONFIG_FB=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_GSPCA=y +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +CONFIG_USB_ZR364XX=m +CONFIG_DRM=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y @@ -119,15 +228,32 @@ CONFIG_SND_DYNAMIC_MINORS=y # CONFIG_SND_USB is not set CONFIG_SND_SOC=y CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_APPLE=y +CONFIG_HID_LOGITECH=m +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG_FSM=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_SERIAL=y +CONFIG_USB_MSM_OTG=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -135,8 +261,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PM8XXX=y CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_ADM=y CONFIG_STAGING=y CONFIG_COMMON_CLK_QCOM=y CONFIG_APQ_MMCC_8084=y @@ -145,23 +273,35 @@ CONFIG_MSM_GCC_8660=y CONFIG_MSM_LCC_8960=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y +CONFIG_QCOM_HFPLL=y +CONFIG_KPSS_XCC=y +CONFIG_KRAITCC=y +CONFIG_MSM_RPMCC_8064=y CONFIG_MSM_IOMMU=y CONFIG_QCOM_GSBI=y CONFIG_QCOM_PM=y CONFIG_PHY_QCOM_APQ8064_SATA=y CONFIG_PHY_QCOM_IPQ806X_SATA=y +CONFIG_NVMEM=y +CONFIG_QCOM_QFPROM=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=y CONFIG_VFAT_FS=y -CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y CONFIG_CIFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y @@ -173,5 +313,5 @@ CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_LOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y -- cgit v1.2.3 From a25341d5f509674f5e365304305a4572d1af7396 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 18 Mar 2015 18:40:30 +0000 Subject: arm:multi_v7_defconfig: Add QCOM specific Kconfigs Signed-off-by: Srinivas Kandagatla --- arch/arm/configs/multi_v7_defconfig | 59 +++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 03deb7fb35e8..46e4087c3546 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -124,8 +124,15 @@ CONFIG_KEXEC=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT_DETAILS=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_QCOM_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_ZYNQ_CPUIDLE=y +CONFIG_ARM_QCOM_CPUIDLE=y CONFIG_NEON=y CONFIG_KERNEL_MODE_NEON=y CONFIG_ARM_ZYNQ_CPUIDLE=y @@ -153,10 +160,20 @@ CONFIG_CAN_DEV=y CONFIG_CAN_AT91=m CONFIG_CAN_XILINXCAN=y CONFIG_CAN_MCP251X=y -CONFIG_BT=m +CONFIG_BT=y CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_ATH3K=y CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_RFKILL=y CONFIG_RFKILL_INPUT=y @@ -202,6 +219,7 @@ CONFIG_SATA_RCAR=y CONFIG_NETDEVICES=y CONFIG_HIX5HD2_GMAC=y CONFIG_SUN4I_EMAC=y +CONFIG_ATL1C=y CONFIG_MACB=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_IGB=y @@ -224,6 +242,10 @@ CONFIG_USB_PEGASUS=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y +CONFIG_ATH_CARDS=m +CONFIG_ATH_DEBUG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m CONFIG_BRCMFMAC=m CONFIG_RT2X00=m CONFIG_RT2800USB=m @@ -301,6 +323,7 @@ CONFIG_I2C_DIGICOLOR=m CONFIG_I2C_GPIO=m CONFIG_I2C_EXYNOS5=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_QUP=y CONFIG_I2C_RIIC=y CONFIG_I2C_S3C2410=y CONFIG_I2C_SH_MOBILE=y @@ -330,9 +353,16 @@ CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_PALMAS=y +CONFIG_PINCTRL_APQ8064=y CONFIG_PINCTRL_APQ8084=y +CONFIG_PINCTRL_IPQ8064=y +CONFIG_PINCTRL_MSM8960=y +CONFIG_PINCTRL_MSM8X74=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_QCOM_SSBI_PMIC=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_DAVINCI=y @@ -371,6 +401,7 @@ CONFIG_DAVINCI_WATCHDOG=m CONFIG_EXYNOS_THERMAL=m CONFIG_ST_THERMAL_SYSCFG=y CONFIG_ST_THERMAL_MEMMAP=y +CONFIG_QCOM_TSENS=y CONFIG_WATCHDOG=y CONFIG_XILINX_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y @@ -391,6 +422,8 @@ CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX8907=y +CONFIG_MFD_PM8921_CORE=y +CONFIG_MFD_QCOM_RPM=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_STMPE=y CONFIG_MFD_PALMAS=y @@ -415,6 +448,7 @@ CONFIG_REGULATOR_MAX77802=m CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PBIAS=y CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_RPM=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS51632=y @@ -464,6 +498,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=m CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_AS3711=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_SOUND=m @@ -494,6 +529,7 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_MVEBU=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y CONFIG_USB_EHCI_EXYNOS=y CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_EHCI_HCD_STI=y @@ -514,12 +550,13 @@ CONFIG_KEYSTONE_USB_PHY=y CONFIG_OMAP_USB3=y CONFIG_USB_GPIO_VBUS=y CONFIG_USB_ISP1301=y +CONFIG_USB_MSM_OTG=y CONFIG_USB_MXS_PHY=y CONFIG_USB_RCAR_PHY=m CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -536,6 +573,7 @@ CONFIG_MMC_SDHCI_ST=y CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_MVSDIO=y CONFIG_MMC_SDHI=y CONFIG_MMC_DW=y @@ -582,6 +620,7 @@ CONFIG_RTC_DRV_DIGICOLOR=m CONFIG_RTC_DRV_S5M=m CONFIG_RTC_DRV_S3C=m CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_PM8XXX=y CONFIG_RTC_DRV_AT91RM9200=m CONFIG_RTC_DRV_AT91SAM9=m CONFIG_RTC_DRV_VT8500=y @@ -605,6 +644,8 @@ CONFIG_IMX_SDMA=y CONFIG_IMX_DMA=y CONFIG_MXS_DMA=y CONFIG_DMA_OMAP=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_ADM=y CONFIG_XILINX_VDMA=y CONFIG_DMA_SUN6I=y CONFIG_STAGING=y @@ -627,6 +668,12 @@ CONFIG_APQ_MMCC_8084=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y +CONFIG_QCOM_RPMCC=y +CONFIG_QCOM_HFPLL=y +CONFIG_KPSS_XCC=y +CONFIG_KRAITCC=y +CONFIG_MSM_RPMCC_8064=y +CONFIG_MSM_IOMMU=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_PM_DEVFREQ=y @@ -651,6 +698,7 @@ CONFIG_PHY_HIX5HD2_SATA=y CONFIG_PWM_STI=m CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_QCOM_APQ8064_SATA=y CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_RCAR_GEN2=m @@ -659,6 +707,8 @@ CONFIG_PHY_STIH407_USB=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN9I_USB=y CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_NVMEM=y +CONFIG_QCOM_QFPROM=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y @@ -682,7 +732,6 @@ CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y CONFIG_LOCKUP_DETECTOR=y CONFIG_CRYPTO_DEV_TEGRA_AES=y -CONFIG_CPUFREQ_DT=y CONFIG_KEYSTONE_IRQ=y CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_ARM_CRYPTO=y @@ -699,3 +748,7 @@ CONFIG_CRYPTO_GHASH_ARM_CE=m CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m +CONFIG_FUNCTION_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_TRACEPOINT_BENCHMARK=y -- cgit v1.2.3 From 638f9ab7c0f9eb1a32d585c5ce5fd4e2c20a56c5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 16 May 2014 11:53:23 -0500 Subject: PCI: qcom: Add support for pcie controllers on IPQ8064 fixed checkpatch warnings too. Signed-off-by: Kumar Gala Signed-off-by: Srinivas Kandagatla --- arch/arm/mach-qcom/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 2256cd1e25d1..afa30dd9521d 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -4,6 +4,8 @@ menuconfig ARCH_QCOM select ARM_GIC select ARM_AMBA select PINCTRL + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI select QCOM_SCM if SMP help Support for Qualcomm's devicetree based systems. -- cgit v1.2.3 From 2a192620c2df86c5081422a9e15dd92f216df677 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 28 Jul 2015 13:53:42 +0100 Subject: ARM: dts: ifc6410: Add pwrseq support for WLAN This patch adds pwrseq for WLAN which resets the WLAN just before the SDIO bus is up. Signed-off-by: Srinivas Kandagatla Conflicts: arch/arm/boot/dts/qcom-apq8064-ifc6410.dts --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index f3100da082b2..7a6d72b8f408 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -1,5 +1,6 @@ #include "qcom-apq8064-v2.0.dtsi" #include +#include / { model = "Qualcomm APQ8064/IFC6410"; @@ -14,6 +15,17 @@ stdout-path = "serial0:115200n8"; }; + pwrseq { + compatible = "simple-bus"; + + sdcc4_pwrseq: sdcc4_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; + }; + }; + soc { pinctrl@800000 { card_detect: card_detect { @@ -210,6 +222,21 @@ status = "okay"; }; + qcom,ssbi@500000 { + pmic@0 { + gpio@150 { + wlan_default_gpios: wlan-gpios { + pios { + pins = "gpio43"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + }; + }; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { @@ -231,6 +258,7 @@ status = "okay"; vmmc-supply = <&ext_3p3v>; vqmmc-supply = <&pm8921_lvs1>; + mmc-pwrseq = <&sdcc4_pwrseq>; }; }; }; -- cgit v1.2.3 From 304ca810aa1bbb8f78ce3c0022f73a1b80acd086 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 28 Jul 2015 13:53:50 +0100 Subject: ARM: dts: qs600: add pwrseq support to WLAN Add pwrseq support to sdcc4 which would enable a proper reset of WLAN without ugly hacks in the board support file. Signed-off-by: Srinivas Kandagatla Conflicts: arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts --- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index 47c0282bdfca..9e3ac6786d0e 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -1,4 +1,6 @@ #include "qcom-apq8064-v2.0.dtsi" +#include +#include / { model = "CompuLab CM-QS600"; @@ -12,6 +14,20 @@ stdout-path = "serial0:115200n8"; }; + pwrseq { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + sdcc4_pwrseq: sdcc4_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; + }; + }; + soc { pinctrl@800000 { i2c1_pins: i2c1 { @@ -163,6 +179,21 @@ regulator-always-on; }; + qcom,ssbi@500000 { + pmic@0 { + gpio@150 { + wlan_default_gpios: wlan-gpios { + pios { + pins = "gpio43"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + }; + }; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { @@ -181,6 +212,7 @@ status = "okay"; vmmc-supply = <&v3p3_fixed>; vqmmc-supply = <&v3p3_fixed>; + mmc-pwrseq = <&sdcc4_pwrseq>; }; }; }; -- cgit v1.2.3 From 4f7a66deb7d783f8e1a25b5d64b2481d779147f1 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 28 Jul 2015 13:54:00 +0100 Subject: ARM: dts: apq8064-ifc6410: add notify led support. This patch adds notify led support on IFC6410, whose trigger can be configured from userspace. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 7a6d72b8f408..cab9dcffe7d9 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -222,6 +222,18 @@ status = "okay"; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <¬ify_led>; + + led@1 { + label = "apq8064:green:user1"; + gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + qcom,ssbi@500000 { pmic@0 { gpio@150 { @@ -233,6 +245,15 @@ power-source = ; }; }; + + notify_led: nled { + pios { + pins = "gpio18"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; }; }; }; -- cgit v1.2.3 From 9f739a1331d614a20455ad3ec8cab67f3b3e4811 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 17 Aug 2015 17:05:15 +0100 Subject: ARM: dts: qs600: remove unnecessary i2c pinctrl nodes in board file. This patch removes unnecessary i2c pinctrl nodes in board file, these are already defined in the soc specific file qcom-apq8064.dtsi. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index 9e3ac6786d0e..6d299c605801 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -29,15 +29,6 @@ }; soc { - pinctrl@800000 { - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - }; - rpm@108000 { regulators { vin_lvs1_3_6-supply = <&pm8921_s4>; -- cgit v1.2.3 From 3140bcf208cbedb2c07ebd05b6d627e7a0c65bdc Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 17 Aug 2015 17:14:12 +0100 Subject: ARM: dts: qs600: Add SD card detect support. This patch adds SD card detect support. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index 6d299c605801..b44a6f17dd52 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -29,6 +29,16 @@ }; soc { + pinctrl@800000 { + card_detect: card_detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; + }; + rpm@108000 { regulators { vin_lvs1_3_6-supply = <&pm8921_s4>; @@ -197,6 +207,9 @@ sdcc3: sdcc@12180000 { status = "okay"; vmmc-supply = <&v3p3_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: sdcc@121c0000 { -- cgit v1.2.3 From 85b0475526eb083f4eb4a591a39fedfcfbb763d2 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 14 Sep 2015 11:34:24 +0100 Subject: ARM: dts: apq8064: add pm8921 rtc This patch adds rtc node for pmic8921. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index d2e94d647c27..fbb33b94aa6c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -361,6 +361,14 @@ <136 1>, <137 1>, <138 1>, <139 1>; }; + rtc@11d { + compatible = "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 1>; + reg = <0x11d>; + allow-set-time; + }; + }; }; -- cgit v1.2.3 From d2e0a06435234cfea3ebbe7be9852c2cbb4fd094 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Wed, 13 May 2015 15:41:47 -0700 Subject: devicetree: Add hardware rng entry to qcom-apq8064.dtsi Add devicetree data to add support for hw_rng support to the apq8064 dts. Tested on the Nexus7 (2013). Cc: Kumar Gala Cc: Stephen Boyd Cc: Srinivas Kandagatla Cc: devicetree@vger.kernel.org Reviewed-by: Stephen Boyd Signed-off-by: John Stultz --- arch/arm/boot/dts/qcom-apq8064.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index fbb33b94aa6c..ae07d6172b29 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -311,6 +311,13 @@ }; }; + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x00500000 0x1000>; -- cgit v1.2.3 From 46990bcd83cdbf78922a89934f43ad9afa78e294 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 18 Aug 2014 07:41:09 +0100 Subject: ARM: dts: apq8064: Add pmic gpio node This patch adds pmic gpio node to the device tree, this node is necessary for devices like wlan to control reset gpio. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index ae07d6172b29..887dae4e3704 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; @@ -333,7 +334,6 @@ #size-cells = <0>; pm8921_gpio: gpio@150 { - compatible = "qcom,pm8921-gpio"; reg = <0x150>; interrupts = <192 1>, <193 1>, <194 1>, -- cgit v1.2.3 From ce36d8474ca82690352a356ba0013d34dff022ff Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 28 Jul 2015 13:54:09 +0100 Subject: ARM: dts: apq8064: Add MDP support This patch adds MDP node to APQ8064 dt. Signed-off-by: Rob Clark [Srinivas Kandagatla] : updated with new style rpm regulators Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 87 +++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 887dae4e3704..06dba4bf8b61 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1,6 +1,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include #include #include #include @@ -107,6 +108,20 @@ }; }; + hdmi_pinctrl: hdmi-pinctrl { + mux1 { + pins = "gpio69", "gpio70", "gpio71"; + function = "hdmi"; + bias-pull-up; + drive-strength = <2>; + }; + mux2 { + pins = "gpio72"; + function = "hdmi"; + bias-pull-down; + drive-strength = <16>; + }; + }; ps_hold: ps_hold { mux { pins = "gpio78"; @@ -633,5 +648,77 @@ compatible = "qcom,tcsr-apq8064", "syscon"; reg = <0x1a400000 0x100>; }; + + hdmi: qcom,hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x1000>; + interrupts = ; + clock-names = + "core_clk", + "master_iface_clk", + "slave_iface_clk"; + clocks = + <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + }; + + gpu: qcom,adreno-3xx@4300000 { + compatible = "qcom,adreno-3xx"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + qcom,chipid = <0x03020002>; + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <450000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + + mdp: qcom,mdp@5100000 { + compatible = "qcom,mdp"; + reg = <0x05100000 0xf0000>; + interrupts = ; + connectors = <&hdmi>; + gpus = <&gpu>; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "src_clk", + "hdmi_clk", + "mdp_clk", + "mdp_axi_clk"; + clocks = + <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc TV_SRC>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>, + <&mmcc MDP_AXI_CLK>; + }; }; }; -- cgit v1.2.3 From a8a99420173ae45555be0615c49d69442c3938ff Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 28 Jul 2015 13:54:18 +0100 Subject: ARM: dts: ifc6410: enable MDP support This patch enables MDP support on IFC6410. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index cab9dcffe7d9..28a893028e23 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -126,6 +126,16 @@ regulator-boot-on; }; + hdmi: qcom,hdmi-tx@4a00000 { + status = "okay"; + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&ext_3p3v>; + }; + + mdp: qcom,mdp@5100000 { + status = "okay"; + }; + gsbi3: gsbi@16200000 { status = "okay"; qcom,mode = ; -- cgit v1.2.3 From 961df47af300a972fb211bb53d1ee8e4592a8adc Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 28 Jul 2015 13:54:27 +0100 Subject: ARM: dts: qs600: enable MDP support This patch enables MDP support on QS600 platform. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index b44a6f17dd52..e7a7932bef76 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -106,6 +106,16 @@ }; }; + hdmi: qcom,hdmi-tx@4a00000 { + status = "okay"; + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&v3p3_fixed>; + }; + + mdp: qcom,mdp@5100000 { + status = "okay"; + }; + gsbi@12440000 { status = "okay"; qcom,mode = ; -- cgit v1.2.3 From d56d33f581689008b64145942320d7150444eed9 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 28 Jul 2015 13:54:36 +0100 Subject: ARM: dts: ifc6410: add inforce LVDS panel support This patch adds LVDS panel for IFC6410. Signed-off-by: Rob Clark [Rob Clark: WIP patch] Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 78 ++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 28a893028e23..0092430af692 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -78,6 +78,12 @@ qcom,switch-mode-frequency = <3200000>; }; + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + pm8921_l3: l3 { regulator-min-microvolt = <3050000>; regulator-max-microvolt = <3300000>; @@ -111,6 +117,10 @@ pm8921_lvs1: lvs1 { bias-pull-down; }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; }; }; @@ -134,6 +144,51 @@ mdp: qcom,mdp@5100000 { status = "okay"; + lvds-vccs-3p3v-supply = <&ext_3p3v>; + lvds-pll-vdda-supply = <&pm8921_l2>; + lvds-vdda-supply = <&pm8921_lvs7>; + + port { + lvds_out: endpoint { + remote-endpoint = <&auo_in>; + }; + }; + }; + + panel_3p3v: panel_3p3v { + compatible = "regulator-fixed"; + pinctrl-0 = <&disp_en_gpios>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "panel_en_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + backlight: backlight{ + pinctrl-0 = <&pwm_bl_gpios>; + pinctrl-names = "default"; + compatible = "gpio-backlight"; + gpios = <&pm8921_gpio 26 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel: auo,b101xtn01 { + status = "okay"; + compatible = "auo,b101xtn01"; + + ddc-i2c-bus = <&i2c3>; + backlight = <&backlight>; + power-supply = <&panel_3p3v>; + port { + auo_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; }; gsbi3: gsbi@16200000 { @@ -247,6 +302,29 @@ qcom,ssbi@500000 { pmic@0 { gpio@150 { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios>; + + pwm_bl_gpios: pwm-bl-gpios { + pios { + pins = "gpio26"; + bias-disable; + function = "normal"; + qcom,drive-strength = ; + power-source = ; + }; + }; + + disp_en_gpios: disp-en-gpios { + pios { + pins = "gpio36"; + bias-disable; + function = "normal"; + qcom,drive-strength = ; + power-source = ; + }; + }; + wlan_default_gpios: wlan-gpios { pios { pins = "gpio43"; -- cgit v1.2.3 From bbb878718d7de0d1c3d87e8a9beb0d6f2fbb7d0c Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 9 Jul 2014 18:08:32 +0100 Subject: ARM: DT: apq8064: add pci support This patch adds PCIE support to APQ8064, tested on IFC6410 board. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 22 ++++++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 41 +++++++++++++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 0092430af692..ffe2061948e8 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -118,6 +118,10 @@ bias-pull-down; }; + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + pm8921_lvs7: lvs7 { bias-pull-down; }; @@ -286,6 +290,24 @@ usb4: usb@12530000 { status = "okay"; }; + + /* on board fixed 3.3v supply */ + v3p3_pcieclk: v3p3-pcieclk { + compatible = "regulator-fixed"; + regulator-name = "PCIE V3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci@1b500000 { + status = "ok"; + pcie-clk-supply = <&v3p3_pcieclk>; + avdd-supply = <&pm8921_s3>; + vdd-supply = <&pm8921_lvs6>; + qcom,external-phy-refclk; + reset-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 06dba4bf8b61..d25617205a31 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -8,6 +8,7 @@ #include #include #include + / { model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; @@ -439,7 +440,45 @@ }; }; - usb1_phy: phy@12500000 { + /* PCIE */ + + pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000>, <0x1b502000 0x100>, <0x1b600000 0x80>; + reg-names = "base", "elbi", "parf"; + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + interrupts = <0 35 0x0 + 0 36 0x0 + 0 37 0x0 + 0 38 0x0 + 0 39 0x0 + 0 238 0x0>; + interrupt-names = "irq1", "irq2", "irq3", "irq4", "iqr5", "msi"; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy"; + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_REF_CLK>; + clock-names = "core", "iface", "phy"; + + ranges = <0x00000000 0 0 0x0ff00000 0 0x00100000 /* configuration space */ + 0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + + }; + + + + usb1_phy:phy@12500000 { compatible = "qcom,usb-otg-ci"; reg = <0x12500000 0x400>; interrupts = ; -- cgit v1.2.3 From a72f44b5a608cf7013ab56405372c61be45f7c52 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 9 Jul 2014 22:07:15 -0400 Subject: ARM: dts: APQ8064: Add iommu Signed-off-by: Srinivas Kandagatla Srinivas Kandagatla [updated with latest generic IOMMU changes from Sricharan] --- arch/arm/boot/dts/qcom-apq8064.dtsi | 73 +++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index d25617205a31..b990aebeff1b 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -725,6 +725,12 @@ <&mmcc GFX3D_AXI_CLK>, <&mmcc MMSS_IMEM_AHB_CLK>; qcom,chipid = <0x03020002>; + + iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + qcom,gpu-pwrlevels { compatible = "qcom,gpu-pwrlevels"; qcom,gpu-pwrlevel@0 { @@ -758,6 +764,73 @@ <&mmcc HDMI_TV_CLK>, <&mmcc MDP_TV_CLK>, <&mmcc MDP_AXI_CLK>; + + iommus = <&mdp_port0 0 2 + &mdp_port1 0 2>; + }; + + mdp_port0: qcom,iommu@7500000 { + compatible = "qcom,iommu-v0"; + #iommu-cells = <2>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07500000 0x100000>; + interrupts = + , + ; + ncb = <2>; + }; + + mdp_port1: qcom,iommu@7600000 { + compatible = "qcom,iommu"; + #iommu-cells = <2>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07600000 0x100000>; + interrupts = + , + ; + ncb = <2>; + }; + + gfx3d: qcom,iommu@7c00000 { + compatible = "qcom,iommu-v0"; + #iommu-cells = <16>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07c00000 0x100000>; + interrupts = + , + ; + ncb = <3>; + }; + + gfx3d1: qcom,iommu@7d00000 { + compatible = "qcom,iommu-v0"; + #iommu-cells = <16>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07d00000 0x100000>; + interrupts = + , + ; + ncb = <3>; }; }; }; -- cgit v1.2.3 From 7d7d9d7b51058f98f5337e356512a9c60973b30a Mon Sep 17 00:00:00 2001 From: Nicolas Dechesne Date: Wed, 26 Nov 2014 13:42:18 +0100 Subject: ARM: DT: apq8064: add pci support in CM QS600 This patch adds PCIE support to APQ8064, tested with Ethernet on Compulab QS600 board. Signed-off-by: Nicolas Dechesne --- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index e7a7932bef76..1ba01ee17934 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -103,6 +103,11 @@ regulator-max-microvolt = <1900000>; bias-pull-down; }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + }; }; @@ -205,6 +210,15 @@ }; }; + pci@1b500000 { + status = "ok"; + pcie-clk-supply = <&v3p3_fixed>; + avdd-supply = <&pm8921_s3>; + vdd-supply = <&pm8921_lvs6>; + qcom,external-phy-refclk; + reset-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { -- cgit v1.2.3 From 1c77ce6cc8084899b5aeafa360914caff0558ae7 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 8 Jul 2015 15:17:16 +0530 Subject: arm: dts: apq8064: Add thermal zones, tsens and eeprom nodes Add thermal zones, tsens and eeprom nodes Signed-off-by: Rajendra Nayak --- arch/arm/boot/dts/qcom-apq8064.dtsi | 108 ++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b990aebeff1b..11239e265900 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -78,6 +78,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert0: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert1: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + cpu_alert2: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + + trips { + cpu_alert3: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; @@ -395,11 +477,37 @@ }; }; + qfprom: qfprom@00700000 { + compatible = "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + tsens_calib: calib { + reg = <0x404 0x10>; + }; + tsens_backup: backup_calib { + reg = <0x414 0x10>; + }; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tsens: thermal-sensor@900000 { + compatible = "qcom,msm8960-tsens"; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + qcom,tsens-slopes = <1176 1176 1154 1176 1111 + 1132 1132 1199 1132 1199 1132>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { -- cgit v1.2.3 From dfedfb57b8d00229065edd1e0c59a17fa87f885d Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 5 Sep 2014 15:47:36 -0700 Subject: ARM: dts: qcom: Add necessary DT data for Krait cpufreq Add the necessary DT nodes and data so we can probe the cpufreq driver on MSM devices with Krait CPUs. Signed-off-by: Stephen Boyd --- arch/arm/boot/dts/qcom-apq8064.dtsi | 224 ++++++++++++++++++++++++++ arch/arm/boot/dts/qcom-msm8960.dtsi | 49 ++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 313 +++++++++++++++++++++++++++++++++++- 3 files changed, 581 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 11239e265900..648e53273b4c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -27,6 +27,9 @@ qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; }; cpu@1 { @@ -38,6 +41,9 @@ qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; }; cpu@2 { @@ -49,6 +55,9 @@ qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 2>; + clock-names = "cpu"; + clock-latency = <100000>; }; cpu@3 { @@ -60,6 +69,9 @@ qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 3>; + clock-names = "cpu"; + clock-latency = <100000>; }; L2: l2-cache { @@ -165,6 +177,214 @@ interrupts = <1 10 0x304>; }; + qcom,pvs { + qcom,pvs-format-a; + qcom,speed0-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 975000 >, + < 594000000 1000000 >, + < 702000000 1025000 >, + < 810000000 1075000 >, + < 918000000 1100000 >; + + qcom,speed0-pvs1-bin-v0 = + < 384000000 900000 >, + < 486000000 925000 >, + < 594000000 950000 >, + < 702000000 975000 >, + < 810000000 1025000 >, + < 918000000 1050000 >; + + qcom,speed0-pvs3-bin-v0 = + < 384000000 850000 >, + < 486000000 875000 >, + < 594000000 900000 >, + < 702000000 925000 >, + < 810000000 975000 >, + < 918000000 1000000 >; + + qcom,speed0-pvs4-bin-v0 = + < 384000000 850000 >, + < 486000000 875000 >, + < 594000000 900000 >, + < 702000000 925000 >, + < 810000000 962500 >, + < 918000000 975000 >; + + qcom,speed1-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 1000000 >, + < 918000000 1025000 >; + + qcom,speed1-pvs1-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 975000 >, + < 918000000 1000000 >; + + qcom,speed1-pvs2-bin-v0 = + < 384000000 925000 >, + < 486000000 925000 >, + < 594000000 925000 >, + < 702000000 925000 >, + < 810000000 937500 >, + < 918000000 950000 >; + + qcom,speed1-pvs3-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 900000 >, + < 918000000 925000 >; + + qcom,speed1-pvs4-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed1-pvs5-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed1-pvs6-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed2-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 950000 >, + < 810000000 962500 >, + < 918000000 975000 >; + + qcom,speed2-pvs1-bin-v0 = + < 384000000 925000 >, + < 486000000 925000 >, + < 594000000 925000 >, + < 702000000 925000 >, + < 810000000 937500 >, + < 918000000 950000 >; + + qcom,speed2-pvs2-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 912500 >, + < 918000000 925000 >; + + qcom,speed2-pvs3-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 900000 >, + < 918000000 912500 >; + + qcom,speed2-pvs4-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed2-pvs5-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed2-pvs6-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed14-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 1000000 >, + < 918000000 1025000 >; + + qcom,speed14-pvs1-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 975000 >, + < 918000000 1000000 >; + + qcom,speed14-pvs2-bin-v0 = + < 384000000 925000 >, + < 486000000 925000 >, + < 594000000 925000 >, + < 702000000 925000 >, + < 810000000 937500 >, + < 918000000 950000 >; + + qcom,speed14-pvs3-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 900000 >, + < 918000000 925000 >; + + qcom,speed14-pvs4-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed14-pvs5-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed14-pvs6-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + #clock-cells = <1>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -256,21 +476,25 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; }; acc2: clock-controller@20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu2_aux"; }; acc3: clock-controller@20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu3_aux"; }; saw0: power-controller@2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 134cd91d68ec..14a8b96ae9b6 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -25,6 +25,10 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; + }; cpu@1 { @@ -35,6 +39,10 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; + }; L2: l2-cache { @@ -49,6 +57,39 @@ qcom,no-pc-write; }; + qcom,pvs { + qcom,pvs-format-a; + /* Hz uV */ + qcom,speed0-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 975000 >, + < 594000000 1000000 >, + < 702000000 1025000 >, + < 810000000 1075000 >, + < 918000000 1100000 >; + + qcom,speed0-pvs1-bin-v0 = + < 384000000 900000 >, + < 486000000 925000 >, + < 594000000 950000 >, + < 702000000 975000 >, + < 810000000 1025000 >, + < 918000000 1050000 >; + + qcom,speed0-pvs3-bin-v0 = + < 384000000 850000 >, + < 486000000 875000 >, + < 594000000 900000 >, + < 702000000 925000 >, + < 810000000 975000 >, + < 918000000 1000000 >; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + #clock-cells = <1>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -126,11 +167,19 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; saw0: regulator@2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ab8e57250468..3292bcee9717 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -25,7 +25,7 @@ #size-cells = <0>; interrupts = <1 9 0xf04>; - cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -34,9 +34,12 @@ qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -45,9 +48,12 @@ qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -56,9 +62,12 @@ qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 2>; + clock-names = "cpu"; + clock-latency = <100000>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -67,6 +76,9 @@ qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc 3>; + clock-names = "cpu"; + clock-latency = <100000>; }; L2: l2-cache { @@ -100,6 +112,267 @@ clock-frequency = <19200000>; }; + qcom,pvs { + qcom,pvs-format-b; + /* Hz uV ua */ + qcom,speed0-pvs0-bin-v0 = + < 300000000 815000 73 >, + < 345600000 825000 85 >, + < 422400000 835000 104 >, + < 499200000 845000 124 >, + < 576000000 855000 144 >, + < 652800000 865000 165 >, + < 729600000 875000 186 >, + < 806400000 890000 208 >, + < 883200000 900000 229 >, + < 960000000 915000 252 >; + + qcom,speed0-pvs1-bin-v0 = + < 300000000 800000 73 >, + < 345600000 810000 85 >, + < 422400000 820000 104 >, + < 499200000 830000 124 >, + < 576000000 840000 144 >, + < 652800000 850000 165 >, + < 729600000 860000 186 >, + < 806400000 875000 208 >, + < 883200000 885000 229 >, + < 960000000 895000 252 >; + + qcom,speed0-pvs2-bin-v0 = + < 300000000 785000 73 >, + < 345600000 795000 85 >, + < 422400000 805000 104 >, + < 499200000 815000 124 >, + < 576000000 825000 144 >, + < 652800000 835000 165 >, + < 729600000 845000 186 >, + < 806400000 855000 208 >, + < 883200000 865000 229 >, + < 960000000 875000 252 >; + + qcom,speed0-pvs3-bin-v0 = + < 300000000 775000 73 >, + < 345600000 780000 85 >, + < 422400000 790000 104 >, + < 499200000 800000 124 >, + < 576000000 810000 144 >, + < 652800000 820000 165 >, + < 729600000 830000 186 >, + < 806400000 840000 208 >, + < 883200000 850000 229 >, + < 960000000 860000 252 >; + + qcom,speed0-pvs4-bin-v0 = + < 300000000 775000 73 >, + < 345600000 775000 85 >, + < 422400000 780000 104 >, + < 499200000 790000 124 >, + < 576000000 800000 144 >, + < 652800000 810000 165 >, + < 729600000 820000 186 >, + < 806400000 830000 208 >, + < 883200000 840000 229 >, + < 960000000 850000 252 >; + + qcom,speed0-pvs5-bin-v0 = + < 300000000 750000 73 >, + < 345600000 760000 85 >, + < 422400000 770000 104 >, + < 499200000 780000 124 >, + < 576000000 790000 144 >, + < 652800000 800000 165 >, + < 729600000 810000 186 >, + < 806400000 820000 208 >, + < 883200000 830000 229 >, + < 960000000 840000 252 >; + + qcom,speed0-pvs6-bin-v0 = + < 300000000 750000 73 >, + < 345600000 750000 85 >, + < 422400000 760000 104 >, + < 499200000 770000 124 >, + < 576000000 780000 144 >, + < 652800000 790000 165 >, + < 729600000 800000 186 >, + < 806400000 810000 208 >, + < 883200000 820000 229 >, + < 960000000 830000 252 >; + + qcom,speed2-pvs0-bin-v0 = + < 300000000 800000 72 >, + < 345600000 800000 83 >, + < 422400000 805000 102 >, + < 499200000 815000 121 >, + < 576000000 825000 141 >, + < 652800000 835000 161 >, + < 729600000 845000 181 >, + < 806400000 855000 202 >, + < 883200000 865000 223 >, + < 960000000 875000 245 >; + + qcom,speed2-pvs1-bin-v0 = + < 300000000 800000 72 >, + < 345600000 800000 83 >, + < 422400000 800000 102 >, + < 499200000 800000 121 >, + < 576000000 810000 141 >, + < 652800000 820000 161 >, + < 729600000 830000 181 >, + < 806400000 840000 202 >, + < 883200000 850000 223 >, + < 960000000 860000 245 >; + + qcom,speed2-pvs2-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 102 >, + < 499200000 785000 121 >, + < 576000000 795000 141 >, + < 652800000 805000 161 >, + < 729600000 815000 181 >, + < 806400000 825000 202 >, + < 883200000 835000 223 >, + < 960000000 845000 245 >; + + qcom,speed2-pvs3-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 102 >, + < 499200000 775000 121 >, + < 576000000 780000 141 >, + < 652800000 790000 161 >, + < 729600000 800000 181 >, + < 806400000 810000 202 >, + < 883200000 820000 223 >, + < 960000000 830000 245 >; + + qcom,speed2-pvs4-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 102 >, + < 499200000 775000 121 >, + < 576000000 775000 141 >, + < 652800000 780000 161 >, + < 729600000 790000 181 >, + < 806400000 800000 202 >, + < 883200000 810000 223 >, + < 960000000 820000 245 >; + + qcom,speed2-pvs5-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 102 >, + < 499200000 750000 121 >, + < 576000000 760000 141 >, + < 652800000 770000 161 >, + < 729600000 780000 181 >, + < 806400000 790000 202 >, + < 883200000 800000 223 >, + < 960000000 810000 245 >; + + qcom,speed2-pvs6-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 102 >, + < 499200000 750000 121 >, + < 576000000 750000 141 >, + < 652800000 760000 161 >, + < 729600000 770000 181 >, + < 806400000 780000 202 >, + < 883200000 790000 223 >, + < 960000000 800000 245 >; + + qcom,speed1-pvs0-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 101 >, + < 499200000 780000 120 >, + < 576000000 790000 139 >, + < 652800000 800000 159 >, + < 729600000 810000 180 >, + < 806400000 820000 200 >, + < 883200000 830000 221 >, + < 960000000 840000 242 >; + + qcom,speed1-pvs1-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 101 >, + < 499200000 775000 120 >, + < 576000000 775000 139 >, + < 652800000 785000 159 >, + < 729600000 795000 180 >, + < 806400000 805000 200 >, + < 883200000 815000 221 >, + < 960000000 825000 242 >; + + qcom,speed1-pvs2-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 101 >, + < 499200000 750000 120 >, + < 576000000 760000 139 >, + < 652800000 770000 159 >, + < 729600000 780000 180 >, + < 806400000 790000 200 >, + < 883200000 800000 221 >, + < 960000000 810000 242 >; + + qcom,speed1-pvs3-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 101 >, + < 499200000 750000 120 >, + < 576000000 750000 139 >, + < 652800000 755000 159 >, + < 729600000 765000 180 >, + < 806400000 775000 200 >, + < 883200000 785000 221 >, + < 960000000 795000 242 >; + + qcom,speed1-pvs4-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 101 >, + < 499200000 750000 120 >, + < 576000000 750000 139 >, + < 652800000 750000 159 >, + < 729600000 755000 180 >, + < 806400000 765000 200 >, + < 883200000 775000 221 >, + < 960000000 785000 242 >; + + qcom,speed1-pvs5-bin-v0 = + < 300000000 725000 72 >, + < 345600000 725000 83 >, + < 422400000 725000 101 >, + < 499200000 725000 120 >, + < 576000000 725000 139 >, + < 652800000 735000 159 >, + < 729600000 745000 180 >, + < 806400000 755000 200 >, + < 883200000 765000 221 >, + < 960000000 775000 242 >; + + qcom,speed1-pvs6-bin-v0 = + < 300000000 725000 72 >, + < 345600000 725000 83 >, + < 422400000 725000 101 >, + < 499200000 725000 120 >, + < 576000000 725000 139 >, + < 652800000 725000 159 >, + < 729600000 735000 180 >, + < 806400000 745000 200 >, + < 883200000 755000 221 >, + < 960000000 765000 242 >; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v2"; + #clock-cells = <1>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -193,7 +466,37 @@ reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; - saw_l2: power-controller@f9012000 { + clock-controller@f9016000 { + compatible = "qcom,hfpll"; + reg = <0xf9016000 0x30>; + clock-output-names = "hfpll_l2"; + }; + + clock-controller@f908a000 { + compatible = "qcom,hfpll"; + reg = <0xf908a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll0"; + }; + + clock-controller@f909a000 { + compatible = "qcom,hfpll"; + reg = <0xf909a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll1"; + }; + + clock-controller@f90aa000 { + compatible = "qcom,hfpll"; + reg = <0xf90aa000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll2"; + }; + + clock-controller@f90ba000 { + compatible = "qcom,hfpll"; + reg = <0xf90ba000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll3"; + }; + + saw_l2: regulator@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; -- cgit v1.2.3 From d27e877dd499f277cc7014faea71ddbb7aad0edf Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Wed, 19 Nov 2014 15:39:04 +0530 Subject: ARM: qcom: add description of KPSS WDT for APQ8064 Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the APQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK, which will do for now. Signed-off-by: Josh Cartwright --- arch/arm/boot/dts/qcom-apq8064.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 648e53273b4c..df1457a50141 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -385,6 +385,14 @@ #clock-cells = <1>; }; + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -473,6 +481,13 @@ cpu-offset = <0x80000>; }; + watchdog@208a038 { + compatible = "qcom,kpss-wdt-apq8064"; + reg = <0x0208a038 0x40>; + clocks = <&sleep_clk>; + timeout-sec = <10>; + }; + acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; -- cgit v1.2.3 From 167f1488da9e268441abb09ba0f6939e74c84414 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Mon, 1 Dec 2014 14:13:22 +0530 Subject: ARM: DT: apq8064: Add Support for ext_3p3v regulator in pci node Ethernet needs ext_3p3v regulator to function properly. This regulator being shared among modules, Ethernet fails when other modules which share this regulator are not enabled. Ethernet is connected on pcie bus and ext_3p3v regulator can be configured through pcie. This change adds support for ext_3p3v regulator in pci DT and make ethernet independent of others and functional. Signed-off-by: Pramod Gurav --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index ffe2061948e8..adc9a343451f 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -305,6 +305,7 @@ pcie-clk-supply = <&v3p3_pcieclk>; avdd-supply = <&pm8921_s3>; vdd-supply = <&pm8921_lvs6>; + ext-3p3v-supply = <&ext_3p3v>; qcom,external-phy-refclk; reset-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; -- cgit v1.2.3 From 104c08435720e97e884904d3bcc7a0c9facd893a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 19 Jan 2015 11:14:36 +0000 Subject: dts: qcom-apq8064: add rpm clock node. This patch adds rpm clock and handoff nodes. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index df1457a50141..80f8f898447d 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -772,12 +773,19 @@ compatible = "qcom,rpm-apq8064"; reg = <0x108000 0x1000>; qcom,ipc = <&l2cc 0x8 2>; + #address-cells = <1>; + #size-cells = <0>; interrupts = , , ; interrupt-names = "ack", "err", "wakeup"; + rpmcc: rpm-clock-controller { + compatible = "qcom,apq8064-rpm-clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; regulators { compatible = "qcom,rpm-pm8921-regulators"; @@ -787,6 +795,7 @@ }; }; + /* PCIE */ pci@1b500000 { -- cgit v1.2.3 From 94a032249fd0052594226d86dad88dc73922b516 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Fri, 28 Aug 2015 11:42:05 +0300 Subject: ARM: dts: apq8064: Assign a power supply to each CPU Assign to each CPU its power supply that will be used for voltage scaling. Signed-off-by: Georgi Djakov --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 ++++++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 8 ++++---- 2 files changed, 20 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index adc9a343451f..3841a7fb7356 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -395,3 +395,19 @@ }; }; }; + +&CPU0 { + cpu-supply = <&saw0>; +}; + +&CPU1 { + cpu-supply = <&saw1>; +}; + +&CPU2 { + cpu-supply = <&saw2>; +}; + +&CPU3 { + cpu-supply = <&saw3>; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 80f8f898447d..e421881b812d 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -19,7 +19,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + CPU0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -33,7 +33,7 @@ clock-latency = <100000>; }; - cpu@1 { + CPU1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -47,7 +47,7 @@ clock-latency = <100000>; }; - cpu@2 { + CPU2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -61,7 +61,7 @@ clock-latency = <100000>; }; - cpu@3 { + CPU3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; -- cgit v1.2.3 From 16321941ad907b352849c5467371b3df7bec7e93 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Fri, 28 Aug 2015 11:43:33 +0300 Subject: ARM: dts: apq8064: Add OPP data for frequencies above 1ghz Now we can scale voltages, so add all frequencies. Signed-off-by: Georgi Djakov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 251 ++++++++++++++++++++++++++++++++---- 1 file changed, 226 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index e421881b812d..52bf178b79d1 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -186,7 +186,17 @@ < 594000000 1000000 >, < 702000000 1025000 >, < 810000000 1075000 >, - < 918000000 1100000 >; + < 918000000 1100000 >, + < 1026000000 1125000 >, + < 1080000000 1175000 >, + < 1134000000 1175000 >, + < 1188000000 1200000 >, + < 1242000000 1200000 >, + < 1296000000 1225000 >, + < 1350000000 1225000 >, + < 1404000000 1237500 >, + < 1458000000 1237500 >, + < 1512000000 1250000 >; qcom,speed0-pvs1-bin-v0 = < 384000000 900000 >, @@ -194,7 +204,17 @@ < 594000000 950000 >, < 702000000 975000 >, < 810000000 1025000 >, - < 918000000 1050000 >; + < 918000000 1050000 >, + < 1026000000 1075000 >, + < 1080000000 1125000 >, + < 1134000000 1125000 >, + < 1188000000 1150000 >, + < 1242000000 1150000 >, + < 1296000000 1175000 >, + < 1350000000 1175000 >, + < 1404000000 1187500 >, + < 1458000000 1187500 >, + < 1512000000 1200000 >; qcom,speed0-pvs3-bin-v0 = < 384000000 850000 >, @@ -202,7 +222,17 @@ < 594000000 900000 >, < 702000000 925000 >, < 810000000 975000 >, - < 918000000 1000000 >; + < 918000000 1000000 >, + < 1026000000 1025000 >, + < 1080000000 1075000 >, + < 1134000000 1075000 >, + < 1188000000 1100000 >, + < 1242000000 1100000 >, + < 1296000000 1125000 >, + < 1350000000 1125000 >, + < 1404000000 1137500 >, + < 1458000000 1137500 >, + < 1512000000 1150000 >; qcom,speed0-pvs4-bin-v0 = < 384000000 850000 >, @@ -210,7 +240,17 @@ < 594000000 900000 >, < 702000000 925000 >, < 810000000 962500 >, - < 918000000 975000 >; + < 918000000 975000 >, + < 1026000000 1000000 >, + < 1080000000 1050000 >, + < 1134000000 1050000 >, + < 1188000000 1075000 >, + < 1242000000 1075000 >, + < 1296000000 1100000 >, + < 1350000000 1100000 >, + < 1404000000 1112500 >, + < 1458000000 1112500 >, + < 1512000000 1125000 >; qcom,speed1-pvs0-bin-v0 = < 384000000 950000 >, @@ -218,7 +258,15 @@ < 594000000 950000 >, < 702000000 962500 >, < 810000000 1000000 >, - < 918000000 1025000 >; + < 918000000 1025000 >, + < 1026000000 1037500 >, + < 1134000000 1075000 >, + < 1242000000 1087500 >, + < 1350000000 1125000 >, + < 1458000000 1150000 >, + < 1566000000 1175000 >, + < 1674000000 1225000 >, + < 1728000000 1250000 >; qcom,speed1-pvs1-bin-v0 = < 384000000 950000 >, @@ -226,7 +274,15 @@ < 594000000 950000 >, < 702000000 962500 >, < 810000000 975000 >, - < 918000000 1000000 >; + < 918000000 1000000 >, + < 1026000000 1012500 >, + < 1134000000 1037500 >, + < 1242000000 1050000 >, + < 1350000000 1087500 >, + < 1458000000 1112500 >, + < 1566000000 1150000 >, + < 1674000000 1187500 >, + < 1728000000 1200000 >; qcom,speed1-pvs2-bin-v0 = < 384000000 925000 >, @@ -234,7 +290,15 @@ < 594000000 925000 >, < 702000000 925000 >, < 810000000 937500 >, - < 918000000 950000 >; + < 918000000 950000 >, + < 1026000000 975000 >, + < 1134000000 1000000 >, + < 1242000000 1012500 >, + < 1350000000 1037500 >, + < 1458000000 1075000 >, + < 1566000000 1100000 >, + < 1674000000 1137500 >, + < 1728000000 1162500 >; qcom,speed1-pvs3-bin-v0 = < 384000000 900000 >, @@ -242,7 +306,15 @@ < 594000000 900000 >, < 702000000 900000 >, < 810000000 900000 >, - < 918000000 925000 >; + < 918000000 925000 >, + < 1026000000 950000 >, + < 1134000000 975000 >, + < 1242000000 987500 >, + < 1350000000 1000000 >, + < 1458000000 1037500 >, + < 1566000000 1062500 >, + < 1674000000 1100000 >, + < 1728000000 1125000 >; qcom,speed1-pvs4-bin-v0 = < 384000000 875000 >, @@ -250,7 +322,15 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 950000 >, + < 1242000000 962500 >, + < 1350000000 975000 >, + < 1458000000 1000000 >, + < 1566000000 1037500 >, + < 1674000000 1075000 >, + < 1728000000 1100000 >; qcom,speed1-pvs5-bin-v0 = < 384000000 875000 >, @@ -258,7 +338,15 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 937500 >, + < 1242000000 950000 >, + < 1350000000 962500 >, + < 1458000000 987500 >, + < 1566000000 1012500 >, + < 1674000000 1050000 >, + < 1728000000 1075000 >; qcom,speed1-pvs6-bin-v0 = < 384000000 875000 >, @@ -266,7 +354,15 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 937500 >, + < 1242000000 950000 >, + < 1350000000 962500 >, + < 1458000000 975000 >, + < 1566000000 1000000 >, + < 1674000000 1025000 >, + < 1728000000 1050000 >; qcom,speed2-pvs0-bin-v0 = < 384000000 950000 >, @@ -274,7 +370,16 @@ < 594000000 950000 >, < 702000000 950000 >, < 810000000 962500 >, - < 918000000 975000 >; + < 918000000 975000 >, + < 1026000000 1000000 >, + < 1134000000 1025000 >, + < 1242000000 1037500 >, + < 1350000000 1062500 >, + < 1458000000 1100000 >, + < 1566000000 1125000 >, + < 1674000000 1175000 >, + < 1782000000 1225000 >, + < 1890000000 1287500 >; qcom,speed2-pvs1-bin-v0 = < 384000000 925000 >, @@ -282,7 +387,16 @@ < 594000000 925000 >, < 702000000 925000 >, < 810000000 937500 >, - < 918000000 950000 >; + < 918000000 950000 >, + < 1026000000 975000 >, + < 1134000000 1000000 >, + < 1242000000 1012500 >, + < 1350000000 1037500 >, + < 1458000000 1075000 >, + < 1566000000 1100000 >, + < 1674000000 1137500 >, + < 1782000000 1187500 >, + < 1890000000 1250000 >; qcom,speed2-pvs2-bin-v0 = < 384000000 900000 >, @@ -290,7 +404,16 @@ < 594000000 900000 >, < 702000000 900000 >, < 810000000 912500 >, - < 918000000 925000 >; + < 918000000 925000 >, + < 1026000000 950000 >, + < 1134000000 975000 >, + < 1242000000 987500 >, + < 1350000000 1012500 >, + < 1458000000 1050000 >, + < 1566000000 1075000 >, + < 1674000000 1112500 >, + < 1782000000 1162500 >, + < 1890000000 1212500 >; qcom,speed2-pvs3-bin-v0 = < 384000000 900000 >, @@ -298,7 +421,16 @@ < 594000000 900000 >, < 702000000 900000 >, < 810000000 900000 >, - < 918000000 912500 >; + < 918000000 912500 >, + < 1026000000 937500 >, + < 1134000000 962500 >, + < 1242000000 975000 >, + < 1350000000 1000000 >, + < 1458000000 1025000 >, + < 1566000000 1050000 >, + < 1674000000 1087500 >, + < 1782000000 1137500 >, + < 1890000000 1175000 >; qcom,speed2-pvs4-bin-v0 = < 384000000 875000 >, @@ -306,7 +438,16 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 950000 >, + < 1242000000 962500 >, + < 1350000000 975000 >, + < 1458000000 1000000 >, + < 1566000000 1037500 >, + < 1674000000 1075000 >, + < 1782000000 1112500 >, + < 1890000000 1150000 >; qcom,speed2-pvs5-bin-v0 = < 384000000 875000 >, @@ -314,7 +455,16 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 937500 >, + < 1242000000 950000 >, + < 1350000000 962500 >, + < 1458000000 987500 >, + < 1566000000 1012500 >, + < 1674000000 1050000 >, + < 1782000000 1087500 >, + < 1890000000 1125000 >; qcom,speed2-pvs6-bin-v0 = < 384000000 875000 >, @@ -322,7 +472,16 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 937500 >, + < 1242000000 950000 >, + < 1350000000 962500 >, + < 1458000000 975000 >, + < 1566000000 1000000 >, + < 1674000000 1025000 >, + < 1782000000 1062500 >, + < 1890000000 1100000 >; qcom,speed14-pvs0-bin-v0 = < 384000000 950000 >, @@ -330,7 +489,13 @@ < 594000000 950000 >, < 702000000 962500 >, < 810000000 1000000 >, - < 918000000 1025000 >; + < 918000000 1025000 >, + < 1026000000 1037500 >, + < 1134000000 1075000 >, + < 1242000000 1087500 >, + < 1350000000 1125000 >, + < 1458000000 1150000 >, + < 1512000000 1162500 >; qcom,speed14-pvs1-bin-v0 = < 384000000 950000 >, @@ -338,7 +503,13 @@ < 594000000 950000 >, < 702000000 962500 >, < 810000000 975000 >, - < 918000000 1000000 >; + < 918000000 1000000 >, + < 1026000000 1012500 >, + < 1134000000 1037500 >, + < 1242000000 1050000 >, + < 1350000000 1087500 >, + < 1458000000 1112500 >, + < 1512000000 1125000 >; qcom,speed14-pvs2-bin-v0 = < 384000000 925000 >, @@ -346,7 +517,13 @@ < 594000000 925000 >, < 702000000 925000 >, < 810000000 937500 >, - < 918000000 950000 >; + < 918000000 950000 >, + < 1026000000 975000 >, + < 1134000000 1000000 >, + < 1242000000 1012500 >, + < 1350000000 1037500 >, + < 1458000000 1075000 >, + < 1512000000 1087500 >; qcom,speed14-pvs3-bin-v0 = < 384000000 900000 >, @@ -354,7 +531,13 @@ < 594000000 900000 >, < 702000000 900000 >, < 810000000 900000 >, - < 918000000 925000 >; + < 918000000 925000 >, + < 1026000000 950000 >, + < 1134000000 975000 >, + < 1242000000 987500 >, + < 1350000000 1000000 >, + < 1458000000 1037500 >, + < 1512000000 1050000 >; qcom,speed14-pvs4-bin-v0 = < 384000000 875000 >, @@ -362,7 +545,13 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 950000 >, + < 1242000000 962500 >, + < 1350000000 975000 >, + < 1458000000 1000000 >, + < 1512000000 1012500 >; qcom,speed14-pvs5-bin-v0 = < 384000000 875000 >, @@ -370,7 +559,13 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 937500 >, + < 1242000000 950000 >, + < 1350000000 962500 >, + < 1458000000 987500 >, + < 1512000000 1000000 >; qcom,speed14-pvs6-bin-v0 = < 384000000 875000 >, @@ -378,7 +573,13 @@ < 594000000 875000 >, < 702000000 875000 >, < 810000000 887500 >, - < 918000000 900000 >; + < 918000000 900000 >, + < 1026000000 925000 >, + < 1134000000 937500 >, + < 1242000000 950000 >, + < 1350000000 962500 >, + < 1458000000 975000 >, + < 1512000000 987500 >; }; kraitcc: clock-controller { -- cgit v1.2.3 From 4d9cfd93b416cfc513bac48e533b0b85fd0faa48 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 26 Aug 2015 18:19:47 +0300 Subject: ARM: dts: apq8064: Add thermal cooling maps Signed-off-by: Georgi Djakov Conflicts: arch/arm/boot/dts/qcom-apq8064.dtsi --- arch/arm/boot/dts/qcom-apq8064.dtsi | 41 +++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 52bf178b79d1..604ab321c9d5 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { model = "Qualcomm APQ8064"; @@ -31,6 +32,9 @@ clocks = <&kraitcc 0>; clock-names = "cpu"; clock-latency = <100000>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -45,6 +49,9 @@ clocks = <&kraitcc 1>; clock-names = "cpu"; clock-latency = <100000>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -59,6 +66,9 @@ clocks = <&kraitcc 2>; clock-names = "cpu"; clock-latency = <100000>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -73,6 +83,9 @@ clocks = <&kraitcc 3>; clock-names = "cpu"; clock-latency = <100000>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; }; L2: l2-cache { @@ -110,6 +123,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal1 { @@ -130,6 +150,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal2 { @@ -150,6 +177,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal3 { @@ -170,6 +204,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; -- cgit v1.2.3 From 29dca0a2f4208c79c3769f07d1018260199b48cb Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 26 Aug 2015 11:09:14 +0300 Subject: ARM: dts: apq8064: Add voltage ranges of the SAW2 regulators Signed-off-by: Georgi Djakov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 604ab321c9d5..e3186fbbe2ed 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -759,24 +759,40 @@ compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; + regulator-name = "krait0"; + regulator-always-on; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1250000>; }; saw1: power-controller@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; + regulator-name = "krait1"; + regulator-always-on; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1250000>; }; saw2: power-controller@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; + regulator-name = "krait2"; + regulator-always-on; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1250000>; }; saw3: power-controller@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; + regulator-name = "krait3"; + regulator-always-on; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1250000>; }; gsbi1: gsbi@12440000 { -- cgit v1.2.3 From 8da4fefecd12328a8d89e34db4a1982dc1cf5acc Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Mon, 7 Sep 2015 12:39:44 +0300 Subject: ARM: dts: apq8064: Add reference to the L2 clock Signed-off-by: Georgi Djakov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index e3186fbbe2ed..c19e408f6cee 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -29,8 +29,8 @@ qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; - clocks = <&kraitcc 0>; - clock-names = "cpu"; + clocks = <&kraitcc 0>, <&kraitcc 4>; + clock-names = "cpu", "l2"; clock-latency = <100000>; cooling-min-level = <0>; cooling-max-level = <7>; @@ -46,8 +46,8 @@ qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; - clocks = <&kraitcc 1>; - clock-names = "cpu"; + clocks = <&kraitcc 1>, <&kraitcc 4>; + clock-names = "cpu", "l2"; clock-latency = <100000>; cooling-min-level = <0>; cooling-max-level = <7>; @@ -63,8 +63,8 @@ qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; - clocks = <&kraitcc 2>; - clock-names = "cpu"; + clocks = <&kraitcc 2>, <&kraitcc 4>; + clock-names = "cpu", "l2"; clock-latency = <100000>; cooling-min-level = <0>; cooling-max-level = <7>; @@ -80,8 +80,8 @@ qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; - clocks = <&kraitcc 3>; - clock-names = "cpu"; + clocks = <&kraitcc 3>, <&kraitcc 4>; + clock-names = "cpu", "l2"; clock-latency = <100000>; cooling-min-level = <0>; cooling-max-level = <7>; -- cgit v1.2.3 From ab34870d8a876735410695ff605404f47bfb196d Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 9 Sep 2015 10:06:12 +0300 Subject: ARM: dts: apq8064: Add a DT node for the L2 data Signed-off-by: Georgi Djakov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index c19e408f6cee..52e997b9afe7 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -93,6 +93,10 @@ cache-level = <2>; }; + qcom,l2 { + qcom,l2-rates = <384000000 972000000 1188000000>; + }; + idle-states { CPU_SPC: spc { compatible = "qcom,idle-state-spc", -- cgit v1.2.3 From e7e8d433b11f98037fbeabc32ec991cb5882b2e6 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 3 Sep 2015 18:12:13 +0300 Subject: ARM: dts: qcom: apq8064-ifc6410 Use hardware flow control for GSBI6 GSBI6 UART module is connected to BT chip, which uses hardware flow control lines. Enable them on SoC side. Signed-off-by: Ivan T. Ivanov --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 3841a7fb7356..a014b171f9f2 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -225,7 +225,7 @@ gsbi@16500000 { status = "ok"; - qcom,mode = ; + qcom,mode = ; serial@16540000 { status = "ok"; -- cgit v1.2.3 From 97a285e274525cbd1e21b73b736dbfc51469e1fc Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Fri, 31 Jul 2015 16:43:38 +0300 Subject: ARM: dts: apq8064: Add ADM configuration node Add Application Data Mover (DMA) device node. Connect GSBI6 UARTDM RX and TX channels to it. Signed-off-by: Ivan T. Ivanov --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 4 ++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index a014b171f9f2..10804413ef50 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -243,6 +243,10 @@ }; }; + adm: dma@18320000 { + status = "okay"; + }; + sata_phy0: phy@1b400000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 52e997b9afe7..1aaa19e8c0ef 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -877,6 +877,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + syscon-tcsr = <&tcsr>; gsbi6_serial: serial@16540000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; @@ -885,6 +886,13 @@ interrupts = <0 156 0x0>; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; + + qcom,rx-crci = <11>; + qcom,tx-crci = <6>; + + dmas = <&adm 6>, <&adm 7>; + dma-names = "rx", "tx"; + status = "disabled"; }; }; @@ -1301,6 +1309,26 @@ }; }; + adm: dma@18320000 { + compatible = "qcom,adm"; + reg = <0x18320000 0xE0000>; + interrupts = ; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <1>; + + status = "disabled"; + }; + tcsr: syscon@1a400000 { compatible = "qcom,tcsr-apq8064", "syscon"; reg = <0x1a400000 0x100>; -- cgit v1.2.3 From 35240a5814826d9eac5a0ae92a91901a8fe92faa Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 16 Sep 2015 13:27:18 +0100 Subject: fixup! ARM: dts: qcom: Add MSM8960 RPM and RPM regulator nodes --- arch/arm/boot/dts/qcom-msm8960.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 14a8b96ae9b6..1111debb1376 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -146,11 +146,6 @@ #reset-cells = <1>; }; - l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; - }; - rpm@108000 { compatible = "qcom,rpm-msm8960"; reg = <0x108000 0x1000>; -- cgit v1.2.3 From 00c8435d86b2760cdc640a189e5520ec430a6481 Mon Sep 17 00:00:00 2001 From: eInfochips Team Date: Wed, 16 Sep 2015 10:19:43 +0200 Subject: arm: dts: Added eInfochips ERAGON600 board support Signed-off-by: Nicolas Dechesne --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8064-eI_ERAGON600.dts | 427 ++++++++++++++++++++++++ 2 files changed, 428 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8064-eI_ERAGON600.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 233159d2eaab..29b66959e45c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -486,6 +486,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-eI_ERAGON600.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8074-dragonboard.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8064-eI_ERAGON600.dts b/arch/arm/boot/dts/qcom-apq8064-eI_ERAGON600.dts new file mode 100644 index 000000000000..40cf6c8eee07 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-eI_ERAGON600.dts @@ -0,0 +1,427 @@ +#include "qcom-apq8064-v2.0.dtsi" +#include +#include + +/ { + model = "Qualcomm APQ8064/ERAGON600"; + compatible = "qcom,apq8064-eragon600", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + }; + + soc { + pinctrl@800000 { + card_detect: card_detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; + }; + + rpm@108000 { + regulators { + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + qcom,force-mode = <3>; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + }; + }; + + ext_3p3v: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ext_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + hdmi: qcom,hdmi-tx@4a00000 { + status = "okay"; + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&ext_3p3v>; + }; + + mdp: qcom,mdp@5100000 { + status = "okay"; + lvds-vccs-3p3v-supply = <&ext_3p3v>; + lvds-pll-vdda-supply = <&pm8921_l2>; + lvds-vdda-supply = <&pm8921_lvs7>; + + port { + lvds_out: endpoint { + remote-endpoint = <&data_image_in>; + }; + }; + }; + + panel_3p3v: panel_3p3v { + pinctrl-0 = <&pwm_en_gpios>; + pinctrl-names = "default"; + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "panel_en_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + backlight: backlight{ + pinctrl-0 = <&pwm_bl_gpios>; + pinctrl-names = "default"; + compatible = "gpio-backlight"; + gpios = <&pm8921_gpio 26 GPIO_ACTIVE_HIGH>; + default-on; + }; + + levelshifter: levelshifter{ + pinctrl-0 = <&pwm_bl_gpios>; + pinctrl-names = "default"; + compatible = "gpio-backlight"; + gpios = <&tlmm_pinmux 85 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + default-on; + }; + + panel: data_image,scf0700C48ggu21 { + status = "okay"; + compatible = "data_image,scf0700C48ggu21"; + + ddc-i2c-bus = <&i2c3>; + backlight = <&backlight>; + power-supply = <&panel_3p3v>; + port { + data_image_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + gsbi3: gsbi@16200000 { + status = "okay"; + qcom,mode = ; + i2c3: i2c@16280000 { + status = "okay"; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + }; + }; + + gsbi@12440000 { + status = "okay"; + qcom,mode = ; + + i2c@12460000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + }; + }; + }; + + gsbi@16500000 { + status = "ok"; + qcom,mode = ; + + serial@16540000 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart_pins>; + }; + }; + + gsbi@16600000 { + status = "ok"; + qcom,mode = ; + serial@16640000 { + status = "ok"; + }; + }; + + adm: dma@18320000 { + status = "okay"; + }; + + sata_phy0: phy@1b400000 { + status = "okay"; + }; + + sata0: sata@29000000 { + status = "okay"; + target-supply = <&pm8921_s4>; + }; + + /* OTG */ + usb1_phy: phy@12500000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + + usb3_phy: phy@12520000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + usb4_phy: phy@12530000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + gadget1: gadget@12500000 { + status = "okay"; + }; + + /* OTG */ + usb1: usb@12500000 { + status = "okay"; + }; + + usb3: usb@12520000 { + status = "okay"; + }; + + usb4: usb@12530000 { + status = "okay"; + }; + + /* on board fixed 3.3v supply */ + v3p3_pcieclk: v3p3-pcieclk { + compatible = "regulator-fixed"; + regulator-name = "PCIE V3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci@1b500000 { + status = "ok"; + pcie-clk-supply = <&v3p3_pcieclk>; + avdd-supply = <&pm8921_s3>; + vdd-supply = <&pm8921_lvs6>; + ext-3p3v-supply = <&ext_3p3v>; + qcom,external-phy-refclk; + reset-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <¬ify_led>; + + led@1 { + label = "apq8064:green:user1"; + gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + qcom,ssbi@500000 { + pmicintc: pmic@0 { + pm8921_gpio: gpio@150 { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios &bt_gpios>; + + pwm_bl_gpios: pwm-bl-gpios { + pios { + pins = "gpio26"; + bias-disable; + function = "normal"; + qcom,drive-strength = <1>; + power-source = ; + }; + }; + + pwm_en_gpios: pwm-en-gpios { + pios { + pins = "gpio36"; + bias-disable; + function = "normal"; + qcom,drive-strength = <1>; + power-source = ; + }; + }; + + wlan_default_gpios: wlan-gpios { + pios { + pins = "gpio43"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + + bt_gpios: bt-gpio { + pios { + pins = "gpio44"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + + notify_led: nled { + pios { + pins = "gpio18"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + }; + }; + }; + sdcc4_pwrseq:pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>, + <&pm8921_gpio 44 GPIO_ACTIVE_LOW>; + }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + vmmc-supply = <&pm8921_l6>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + }; + /* WLAN */ + sdcc4: sdcc@121c0000 { + status = "okay"; + vmmc-supply = <&ext_3p3v>; + vqmmc-supply = <&pm8921_lvs1>; + mmc-pwrseq = <&sdcc4_pwrseq>; + }; + }; + }; +}; + +&CPU0 { + cpu-supply = <&saw0>; +}; + +&CPU1 { + cpu-supply = <&saw1>; +}; + +&CPU2 { + cpu-supply = <&saw2>; +}; + +&CPU3 { + cpu-supply = <&saw3>; +}; -- cgit v1.2.3 From 282eabf2abe8c2e0e60cd3453a564e31006231aa Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 17 Sep 2015 10:02:18 +0100 Subject: ARM: dts: ifc6410: HACK add bt reset gpios to pwrseq This patch adds BT gpios to reset sequence in SDCC4 pwrseq. Ideally BT UART bus should get hold of pwrseq and do the reset, but for now as a hack we let the BT reset done just with SDIO bus. Things will change once the pwrseq is converted in to a proper platform driver and other buses can use it. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 10804413ef50..19b16218e3c8 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -20,9 +20,10 @@ sdcc4_pwrseq: sdcc4_pwrseq { pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; + pinctrl-0 = <&wlan_default_gpios &bt_gpios>; compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; + reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>, + <&pm8921_gpio 44 GPIO_ACTIVE_LOW>; }; }; @@ -361,6 +362,15 @@ }; }; + bt_gpios: bt-gpio { + pios { + pins = "gpio44"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; + notify_led: nled { pios { pins = "gpio18"; -- cgit v1.2.3 From c7514442b11192ebdd577f5da6e24676e76161f8 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 14 Apr 2015 18:42:14 +0530 Subject: arm: dts: qcom: Add #power-domain-cells property msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them. Signed-off-by: Rajendra Nayak --- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 0554fbd72c40..fcffecae3e67 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -221,6 +221,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ab8e57250468..ab8473bbef38 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -228,6 +228,7 @@ compatible = "qcom,gcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; }; @@ -240,6 +241,7 @@ compatible = "qcom,mmcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; }; -- cgit v1.2.3 From f3d9620c0ac470d57f1846a8fa6ded719531347c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 8 Jul 2015 15:17:15 +0530 Subject: arm: dts: msm8974: Add thermal zones, tsens and eeprom nodes Add thermal zones, tsens and eeprom nodes Signed-off-by: Rajendra Nayak --- arch/arm/boot/dts/qcom-msm8974.dtsi | 105 ++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ab8473bbef38..fe2c5a601d8e 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -86,6 +86,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; @@ -114,6 +196,29 @@ <0xf9002000 0x1000>; }; + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + tsens: thermal-sensor@fc4a8000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a8000 0x2000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + qcom,tsens-slopes = <3200 3200 3200 3200 3200 3200 + 3200 3200 3200 3200 3200>; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From a02103411ae575c61cd5ea5b6b6183f7a69d358e Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 8 Jul 2015 15:17:17 +0530 Subject: arm: dts: apq8084: Add thermal zones, tsens and eeprom nodes Add thermal zones, tsens and eeprom nodes Signed-off-by: Rajendra Nayak --- arch/arm/boot/dts/qcom-apq8084.dtsi | 105 ++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fcffecae3e67..477173c55d0b 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -75,6 +75,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; @@ -103,6 +185,29 @@ <0xf9002000 0x1000>; }; + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + tsens: thermal-sensor@fc4a8000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a8000 0x2000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + qcom,tsens-slopes = <3200 3200 3200 3200 3200 3200 + 3200 3200 3200 3200 3200>; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From bad7af9a507527f4fa96fd39c0fa91f2ff451932 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 15 May 2015 02:00:02 +0300 Subject: arm: dma-mapping: Don't override dma_ops in arch_setup_dma_ops() The arch_setup_dma_ops() function is in charge of setting dma_ops with a call to set_dma_ops(). set_dma_ops() is also called from - highbank and mvebu bus notifiers - dmabounce (to be replaced with swiotlb) - arm_iommu_attach_device (arm_iommu_attach_device is itself called from IOMMU and bus master device drivers) To allow the arch_setup_dma_ops() call to be moved from device add time to device probe time we must ensure that dma_ops already setup by any of the above callers will not be overriden. Aftering replacing dmabounce with swiotlb, converting IOMMU drivers to of_xlate and taking care of highbank and mvebu, the workaround should be removed. Signed-off-by: Laurent Pinchart --- arch/arm/mm/dma-mapping.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 1a7815e5421b..7e2b75f8b046 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2126,6 +2126,15 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, struct dma_map_ops *dma_ops; dev->archdata.dma_coherent = coherent; + + /* + * Don't override the dma_ops if they have already been set. Ideally + * this should be the only location where dma_ops are set, remove this + * check when all other callers of set_dma_ops will have disappeared. + */ + if (dev->archdata.dma_ops) + return; + if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) dma_ops = arm_get_iommu_dma_map_ops(coherent); else -- cgit v1.2.3 From 902293cc625e88cb9c6931bda0e47d951db71a4a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Mar 2015 23:45:20 -0700 Subject: ARM: Add Krait L2 register accessor functions Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland Cc: Russell King Cc: Courtney Cavin Signed-off-by: Stephen Boyd --- arch/arm/common/Kconfig | 3 ++ arch/arm/common/Makefile | 1 + arch/arm/common/krait-l2-accessors.c | 58 +++++++++++++++++++++++++++++++ arch/arm/include/asm/krait-l2-accessors.h | 20 +++++++++++ 4 files changed, 82 insertions(+) create mode 100644 arch/arm/common/krait-l2-accessors.c create mode 100644 arch/arm/include/asm/krait-l2-accessors.h (limited to 'arch/arm') diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index c3a4e9ceba34..9da52dc6260b 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -9,6 +9,9 @@ config DMABOUNCE bool select ZONE_DMA +config KRAIT_L2_ACCESSORS + bool + config SHARP_LOCOMO bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 6ee5959a813b..6764ed0ba87d 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -7,6 +7,7 @@ obj-y += firmware.o obj-$(CONFIG_ICST) += icst.o obj-$(CONFIG_SA1111) += sa1111.o obj-$(CONFIG_DMABOUNCE) += dmabounce.o +obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o diff --git a/arch/arm/common/krait-l2-accessors.c b/arch/arm/common/krait-l2-accessors.c new file mode 100644 index 000000000000..5d514bbc88a6 --- /dev/null +++ b/arch/arm/common/krait-l2-accessors.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include +#include + +static DEFINE_RAW_SPINLOCK(krait_l2_lock); + +void krait_set_l2_indirect_reg(u32 addr, u32 val) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&krait_l2_lock, flags); + /* + * Select the L2 window by poking l2cpselr, then write to the window + * via l2cpdr. + */ + asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); + isb(); + asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val)); + isb(); + + raw_spin_unlock_irqrestore(&krait_l2_lock, flags); +} +EXPORT_SYMBOL(krait_set_l2_indirect_reg); + +u32 krait_get_l2_indirect_reg(u32 addr) +{ + u32 val; + unsigned long flags; + + raw_spin_lock_irqsave(&krait_l2_lock, flags); + /* + * Select the L2 window by poking l2cpselr, then read from the window + * via l2cpdr. + */ + asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); + isb(); + asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val)); + + raw_spin_unlock_irqrestore(&krait_l2_lock, flags); + + return val; +} +EXPORT_SYMBOL(krait_get_l2_indirect_reg); diff --git a/arch/arm/include/asm/krait-l2-accessors.h b/arch/arm/include/asm/krait-l2-accessors.h new file mode 100644 index 000000000000..48fe5527bc01 --- /dev/null +++ b/arch/arm/include/asm/krait-l2-accessors.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H +#define __ASMARM_KRAIT_L2_ACCESSORS_H + +extern void krait_set_l2_indirect_reg(u32 addr, u32 val); +extern u32 krait_get_l2_indirect_reg(u32 addr); + +#endif -- cgit v1.2.3