diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-06-08 17:34:44 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-08 17:34:44 +0100 |
| commit | c906d2a8493bedcb5478a466f13a579551900c17 (patch) | |
| tree | 5d947a508785a0b46479dc3b9fc4711b5bbe2daf /plat/rockchip/rk3368/include | |
| parent | 0437c421cdafcf84e92a7a47ea814b2f772f2c7c (diff) | |
| parent | 84597b57f98233989ef44ee0ccdf67b8ecea97b3 (diff) | |
Merge pull request #967 from rockchip-linux/rockchip-cleanup-20170606
RK3399: Shrink M0 SRAM code to fit in PMUSRAM
Diffstat (limited to 'plat/rockchip/rk3368/include')
| -rw-r--r-- | plat/rockchip/rk3368/include/plat.ld.S | 37 | ||||
| -rw-r--r-- | plat/rockchip/rk3368/include/platform_def.h | 3 |
2 files changed, 40 insertions, 0 deletions
diff --git a/plat/rockchip/rk3368/include/plat.ld.S b/plat/rockchip/rk3368/include/plat.ld.S new file mode 100644 index 000000000..b3559b20f --- /dev/null +++ b/plat/rockchip/rk3368/include/plat.ld.S @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __ROCKCHIP_PLAT_LD_S__ +#define __ROCKCHIP_PLAT_LD_S__ + +MEMORY { + PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE +} + +SECTIONS +{ + . = PMUSRAM_BASE; + + /* + * pmu_cpuson_entrypoint request address + * align 64K when resume, so put it in the + * start of pmusram + */ + .text_pmusram : { + ASSERT(. == ALIGN(64 * 1024), + ".pmusram.entry request 64K aligned."); + *(.pmusram.entry) + __bl31_pmusram_text_start = .; + *(.pmusram.text) + *(.pmusram.rodata) + __bl31_pmusram_text_end = .; + __bl31_pmusram_data_start = .; + *(.pmusram.data) + __bl31_pmusram_data_end = .; + + } >PMUSRAM +} + +#endif /* __ROCKCHIP_PLAT_LD_S__ */ diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 053f6fe39..07b91e268 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -122,4 +122,7 @@ #define PLAT_RK_PRIMARY_CPU 0x0 +#define PSRAM_DO_DDR_RESUME 0 +#define PSRAM_CHECK_WAKEUP_CPU 0 + #endif /* __PLATFORM_DEF_H__ */ |