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2017-06-16Merge pull request #953 from vwadekar/tegra-misra-fixes-v1davidcunado-arm
Tegra misra fixes v1
2017-06-16Merge pull request #984 from masahir0y/uniphierdavidcunado-arm
uniphier memory-overrun bug fix
2017-06-16Merge pull request #986 from jagadeeshujja/jagujj/fix-get-power-statedavidcunado-arm
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
2017-06-15Merge pull request #980 from dp-arm/dp/make-fixdavidcunado-arm
tools: Use exported quiet flag from top-level Makefile
2017-06-15Merge pull request #981 from soby-mathew/sm/cov_scmidavidcunado-arm
Fix coverity error in CSS SCMI driver
2017-06-15Merge pull request #985 from hzhuang1/remove_mailboxdavidcunado-arm
hikey960: remove mailbox driver
2017-06-15CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is setjagadeesh ujja
The ARM_PLAT_MT bit enables the support for MT bit in MPIDR format. This means that the level 0 affinity represents the thread and CPU / Cluster levels are at affinity level 1 and 2 respectively. This was not catered for in the scpi 'css_scp_get_power_state, API. Since the SCPI driver can only cater for single threaded CPUs, this patch fixes the problem by catering for this shift by effectively ignoring the Thread (level 0) affinity level. Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>
2017-06-15hikey960: remove mailbox driverHaojian Zhuang
Since this mailbox driver is abandoned, remove it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-15uniphier: fix memory over-run bugMasahiro Yamada
Check the array index before the write. This issue was found by a static analysis tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-14Tegra186: mce: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: delay_timer: fix MISRA defectsAnthony Zhou
Main fixes: * Include header file for function declarations [Rule 8.4] * Move global object into function [Rule 8.9] Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: gic: fix MISRA defectsVarun Wadekar
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Fixed assert/if statements conditions to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Convert macros form headers to unsigned ints Change-Id: I8051cc16499cece2039c9751bd347645f40f0901 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: fiq_glue: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Convert object type to match the type of function parameters [Rule 10.3] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: pmc: fix defects flagged during MISRA analysisAnthony Zhou
Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: memctrl: check GPU reset state from common placeVarun Wadekar
This patch moves the GPU reset state check, during VideoMem resize, to the common SiP handler, to reduce code duplication. Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: memctrl_v2: fix software logic to check "flush complete"Varun Wadekar
This patch fixes the logic to check if the command written to the MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module. Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: add explicit casts for integer macrosVarun Wadekar
This patch adds explicit casts (U(x)) to integers in the tegra_def.h headers, to make them compatible with whatever operation they're used in [MISRA-C Rule 10.1] Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14include: add U()/ULL() macros for constantsVarun Wadekar
This patch uses the U() and ULL() macros for constants, to fix some of the signed-ness defects flagged by the MISRA scanner. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Add U() macro to share constants between C and other sourcesVarun Wadekar
This patch adds the U(_x) macros to utils_def.h to allow constants to be shared between C and other sources. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Merge pull request #979 from soby-mathew/sm/aarch32_macro_fixdavidcunado-arm
Fix stdlib defines for AArch32
2017-06-13Merge pull request #974 from masahir0y/uniphierdavidcunado-arm
UniPhier Initial Support
2017-06-13Merge pull request #982 from hzhuang1/fix_hikey960davidcunado-arm
Fix hikey960
2017-06-13hikey960: fix the calculation in boardidHaojian Zhuang
Since the type of ADC value is always unsigned int, don't need to check the value with negative value. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-13ufs: fix the and operatorHaojian Zhuang
Should use AND (&), not &&. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-13uniphier: add TSP supportMasahiro Yamada
Add TSP to test BL32 without relying on external projects. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-13uniphier: support Socionext UniPhier platformMasahiro Yamada
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-12tools: Use exported quiet flag from top-level Makefiledp-arm
When V is set from the command line, the value is passed to the tools' Makefiles as well. Change-Id: I91a1f66de5c1ae6f36b6c9f0a9bd550d4a30f092 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-09Fix coverity error in CSS SCMI driverSoby Mathew
Change-Id: Ia7d731f429e452e4bc9f9a553d7105b6394c621c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-09Fix stdlib defines for AArch32Soby Mathew
Some of the macro defines in the header files of `include/lib/stdlib/machine/` folder are not correct for AArch32. This patch fixes the same. Change-Id: I8bfaf638a7986fd902648d2074537bd26c313cb3 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-09Merge pull request #972 from achingupta/ag/freebsd-dt-changedavidcunado-arm
Device tree changes to boot FreeBSD on FVPs
2017-06-09Merge pull request #971 from Xilinx/tegradavidcunado-arm
tegra: Fix build errors
2017-06-09Merge pull request #973 from danh-arm/dh/add-maintainersdavidcunado-arm
Docs: Clarify copyright requirements
2017-06-09Merge pull request #968 from antonio-nino-diaz-arm/an/snprintf-altdavidcunado-arm
mbedtls: Don't use tf_snprintf if option not defined
2017-06-08Merge pull request #967 from rockchip-linux/rockchip-cleanup-20170606davidcunado-arm
RK3399: Shrink M0 SRAM code to fit in PMUSRAM
2017-06-08tegra: Fix build errorsSoren Brinkmann
The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO level print statement. INFO is defined based on LOG_LEVEL. Hence, builds would fail when - DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined - DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used Fixing this by guarding impl with the same condition that guards INFO. Fixes ARM-software/tf-issues#490 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2017-06-08Docs: Clarify copyright requirementsDan Handley
Clarify copyright requirements in contributing.md. Also clarify maintainership structure by adding a new maintainers.md. This imports individual maintainer details from the GitHub wiki. Fixes ARM-software/tf-issues#488 Change-Id: I7135d3f77ea45533f667de7e1dcdf65697486a91 Signed-off-by: Dan Handley <dan.handley@arm.com>
2017-06-08Merge pull request #970 from vingu-linaro/enable-pmf-rt-instr-hikeydanh-arm
Enable pmf rt instr hikey
2017-06-08Merge pull request #959 from hzhuang1/hikey960_v1danh-arm
Hikey960 v1
2017-06-08rockchip: check wakeup cpu when resumeLin Huang
unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need to check wakeup cpu when resume. Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-06-08rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspendLin Huang
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that. Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-08rockchip/rk3399: Move DRAM restore to PMUSRAMDerek Basehore
This moves the DRAM restore code to PMUSRAM. This is so that the voltage domain that contains the SRAM that it was stored in before may be turned off during system suspend. Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: convert to for-loops to save code spaceDerek Basehore
This converts two functions to use for-loops. This saves a bit of space to help moving DRAM resume code to PMUSRAM. Change-Id: Ie6ca490cf50c2ec83335cf1845b337c3e8a47496 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: Remove unneeded if statementDerek Basehore
The removed if statement would make the same check that the for loop it is in does to break out of the for loop, so it doesn't make any sense to keep it there. Change-Id: I819c29f9182e6de1fc47e418aed15ad38e8f9fa9 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: Remove unneeded register setsDerek Basehore
This removes the mmio_... function calls to set the multicast bit for the PHY registers when overriding the write leveling values. These are not needed since multicast is set by default when calling the function, and it's also better not to leave the side effect of disabling multicast when exiting the function. Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: remove unneeded DDR restore functionDerek Basehore
This removes the phy_dll_bypass_set function as it is unneeded. The values that function sets are saved during suspend, so the proper values will be restored on resume. Change-Id: I17542206c56e639ce8cb6375233145167441d4e2 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: Save space for DRAM suspend dataDerek Basehore
This removes the space allocation for the unused PHY register space. For instance in PHY registers 0-127, only 0-90 are used, so don't save the 91-127 registers. This saves about 1.6KB of space. Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip: add pmusram sectionLin Huang
the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-08rockchip/rk3399: fix DRAM gate training issueLin Huang
The differential signal of DQS need keep low level before gate training. It need enable RPULL and disable PHY side ODT to ensure it when do gate training. But it can not access the PHY registers to do it when perform DFS.So the workaroud as below: It is ensure that the PHY's read gate is landing somewhere in the incoming DQS's pulses before it starts searching for pre-amble window. It need get the rddqs_delay_ps to calculate the start point of gate training for DFS. Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe Signed-off-by: Lin Huang <hl@rock-chips.com>
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