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| author | Manish Pandey <manish.pandey2@arm.com> | 2018-05-30 17:49:52 +0100 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2018-05-30 17:49:52 +0100 |
| commit | e5ba23f3fb4d80d0a00e7c06e5d1974222c7a84f (patch) | |
| tree | 79dae4944d5c151c04e4b3befc2f6c6c3a680bcc | |
| parent | 510d936a8a540c9cbac9514226e4fbf60b77f7b0 (diff) | |
bootwrapper: correcting cpu GIC base for Cortex-A5/A9.
CPU GIC base for Cortex-A9 and Cortex-A5 are different than
other cpu's so introduced a compilation flag CORTEX_A9_A5
to select correct GICC base.
To build for Cortex-A9 or A5
"make CORTEX_A9_A5=yes semi"
Change-Id: I1844ee7da9454ab18b860ab16e6850d77b6dfa0b
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| -rw-r--r-- | boot.S | 6 | ||||
| -rw-r--r-- | config-default.mk | 4 |
2 files changed, 9 insertions, 1 deletions
@@ -52,7 +52,11 @@ start: bne 2b @ Set GIC priority mask bit [7] = 1 - ldr r0, =0x2c002000 @ CPU GIC base +#ifdef CORTEX_A9_A5 + ldr r0, =0x2c000100 @ CPU GIC base +#else + ldr r0, =0x2c002000 @ CPU GIC base +#endif mov r1, #0x80 str r1, [r0, #0x4] @ GIC ICCPMR diff --git a/config-default.mk b/config-default.mk index 6c73934..fade53d 100644 --- a/config-default.mk +++ b/config-default.mk @@ -87,6 +87,10 @@ CPPFLAGS += -DSMP CPPFLAGS += -march=armv7-a -marm #CPPFLAGS += -DTHUMB2_KERNEL CPPFLAGS += -DVEXPRESS +CORTEX_A9_A5 ?= no +ifeq ($(CORTEX_A9_A5),yes) +CPPFLAGS +=-DCORTEX_A9_A5 +endif # Default kernel command line, using initrd: ifeq ($(USE_INITRD),yes) |