summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorArd Biesheuvel <ard.biesheuvel@linaro.org>2016-04-19 16:16:37 +0200
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2016-05-10 14:44:27 +0200
commit80e5a33da1fcbe54cbcc178f1880e80e297d5fd4 (patch)
tree5b4f9ede9312b0eaee3f57811147e6bcba5e125e
parente55f8c73b6255b353c021ab59017a364dd527a86 (diff)
ArmPkg/ArmDmaLib: consistently use 'gCacheAlignment - 1' as alignment mask
We manage to use both an AND operation with 'gCacheAlignment - 1' and a modulo operation with 'gCacheAlignment' in the same compound if statement. Since gCacheAlignment is a global of which the compiler cannot guarantee that it is a power of two, simply use the AND version in both cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
-rw-r--r--ArmPkg/Library/ArmDmaLib/ArmDmaLib.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
index 1e6b288b10..66f3469eb1 100644
--- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
+++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
@@ -93,7 +93,7 @@ DmaMap (
*Mapping = Map;
if ((((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) ||
- ((*NumberOfBytes % gCacheAlignment) != 0)) {
+ ((*NumberOfBytes & (gCacheAlignment - 1)) != 0)) {
// Get the cacheability of the region
Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);