diff options
| author | Vishnu Banavath <vishnu.banavath@arm.com> | 2019-10-09 14:43:18 +0100 |
|---|---|---|
| committer | Tushar Khandelwal <tushar.khandelwal@arm.com> | 2020-01-24 15:37:14 +0000 |
| commit | 211f64282cde60e87eb030500cb8ebbd03eba328 (patch) | |
| tree | 32a1820e501148416e6b67a866917347384ccf1b | |
| parent | 1823b4070df6fb9fd214d75f08e79ba815a95a33 (diff) | |
pl011: set uart clock to 32MHzCORSTONE-700-2020.02.10
Set UART clock 32MHz to aling with FPGA
Change-Id: I10c394028ecbcda47659dfa2bf602eb4a67f1b5c
| -rw-r--r-- | product/corstone-700/firmware/config_log.c | 2 | ||||
| -rw-r--r-- | product/corstone-700/module/pl011/include/mod_pl011.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/product/corstone-700/firmware/config_log.c b/product/corstone-700/firmware/config_log.c index e9e4b47..4f34f1c 100644 --- a/product/corstone-700/firmware/config_log.c +++ b/product/corstone-700/firmware/config_log.c @@ -25,7 +25,7 @@ static const struct fwk_element pl011_element_desc_table[] = { .data = &((struct mod_pl011_device_config) { .reg_base = ES_PL011_UART_BASE, .baud_rate_bps = 115200, - .clock_rate_hz = SYSTEM_CLOCK, + .clock_rate_hz = 32 * UART_CLK_MHZ, .clock_id = FWK_ID_NONE_INIT, }), }, diff --git a/product/corstone-700/module/pl011/include/mod_pl011.h b/product/corstone-700/module/pl011/include/mod_pl011.h index 4ae23f1..71a6dde 100644 --- a/product/corstone-700/module/pl011/include/mod_pl011.h +++ b/product/corstone-700/module/pl011/include/mod_pl011.h @@ -27,6 +27,8 @@ * @{ */ +#define UART_CLK_MHZ (1000UL * 1000UL) + /*! * \brief PL011 device configuration data. */ |