diff options
| author | Jon Medhurst <tixy@linaro.org> | 2016-03-23 11:10:53 +0000 |
|---|---|---|
| committer | Jon Medhurst <tixy@linaro.org> | 2017-04-03 11:58:49 +0100 |
| commit | aee3d5c9efdab24641c7bb2a84c20a4aacc22d67 (patch) | |
| tree | 5b1bc605e524d7e5ca96c8c920ee9e528aaf5679 | |
| parent | 083e6ec23591191955d94bb6e26f837fd1247abc (diff) | |
arm64: dts: Add HDLCD to Base FVP
but mark it disabled, so CLCD is used by default.
To use HDLCD, s/&hdlcd/&clcd/ to mark CLCD disabled instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base.dtsi | 49 |
2 files changed, 53 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts index 682e64128c1b..eb9d35a61243 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts @@ -221,3 +221,8 @@ #include "fvp-base.dtsi" }; + +&hdlcd { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/arm/fvp-base.dtsi b/arch/arm64/boot/dts/arm/fvp-base.dtsi index ea3f170ad6fa..3ffbb83955e1 100644 --- a/arch/arm64/boot/dts/arm/fvp-base.dtsi +++ b/arch/arm64/boot/dts/arm/fvp-base.dtsi @@ -205,7 +205,7 @@ clock-names = "apb_pclk"; }; - clcd@1c1f0000 { + clcd: clcd@1c1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x0 0x1c1f0000 0x0 0x1000>; interrupt-names = "combined"; @@ -260,6 +260,53 @@ }; }; + fake_hdlcd_clk: fake-hdlcd-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <63500000>; + clock-output-names = "pxlclk"; + }; + + + hdlcd: hdlcd@7ff60000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff60000 0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&fake_hdlcd_clk>; + clock-names = "pxlclk"; + + port { + hdlcd_out: endpoint { + remote-endpoint = <&bp_hdlcd_display>; + }; + }; + }; + + vencoder { + compatible = "drm,virtual-encoder"; + + port { + bp_hdlcd_display: endpoint { + remote-endpoint = <&hdlcd_out>; + }; + }; + + display-timings { + panel-timing { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; + + }; + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x80000000>, |