diff options
Diffstat (limited to 'drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz')
5 files changed, 547 insertions, 0 deletions
diff --git a/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/Kbuild b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/Kbuild new file mode 100755 index 000000000000..32c707030b0f --- /dev/null +++ b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/Kbuild @@ -0,0 +1,17 @@ +# +# (C) COPYRIGHT 2012 ARM Limited. All rights reserved. +# +# This program is free software and is provided to you under the terms of the +# GNU General Public License version 2 as published by the Free Software +# Foundation, and any use by you of this program is subject to the terms +# of such GNU licence. +# +# A copy of the licence is included with the program, and can also be obtained +# from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, +# Boston, MA 02110-1301, USA. +# +# + + +obj-y += mali_kbase_config_vexpress.o +obj-y += mali_kbase_cpu_vexpress.o diff --git a/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_config_platform.h b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_config_platform.h new file mode 100755 index 000000000000..ad576a533ef8 --- /dev/null +++ b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_config_platform.h @@ -0,0 +1,33 @@ +/* + * + * (C) COPYRIGHT ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained + * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + * + */ + + + +/** + * Maximum frequency GPU will be clocked at. Given in kHz. + * This must be specified as there is no default value. + * + * Attached value: number in kHz + * Default value: NA + */ +#define GPU_FREQ_KHZ_MAX 40000 +/** + * Minimum frequency GPU will be clocked at. Given in kHz. + * This must be specified as there is no default value. + * + * Attached value: number in kHz + * Default value: NA + */ +#define GPU_FREQ_KHZ_MIN 40000 diff --git a/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_config_vexpress.c b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_config_vexpress.c new file mode 100755 index 000000000000..c0ec1dd57f04 --- /dev/null +++ b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_config_vexpress.c @@ -0,0 +1,293 @@ +/* + * + * (C) COPYRIGHT ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained + * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + * + */ + + + +#include <linux/ioport.h> +#include <mali_kbase.h> +#include <mali_kbase_defs.h> +#include <mali_kbase_config.h> + +#include "mali_kbase_cpu_vexpress.h" + +/* Versatile Express (VE) configuration defaults shared between config_attributes[] + * and config_attributes_hw_issue_8408[]. Settings are not shared for + * JS_HARD_STOP_TICKS_SS and JS_RESET_TICKS_SS. + */ +#define KBASE_VE_JS_SCHEDULING_TICK_NS_DEBUG 15000000u /* 15ms, an agressive tick for testing purposes. This will reduce performance significantly */ +#define KBASE_VE_JS_SOFT_STOP_TICKS_DEBUG 1 /* between 15ms and 30ms before soft-stop a job */ +#define KBASE_VE_JS_SOFT_STOP_TICKS_CL_DEBUG 1 /* between 15ms and 30ms before soft-stop a CL job */ +#define KBASE_VE_JS_HARD_STOP_TICKS_SS_DEBUG 333 /* 5s before hard-stop */ +#define KBASE_VE_JS_HARD_STOP_TICKS_SS_8401_DEBUG 2000 /* 30s before hard-stop, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) - for issue 8401 */ +#define KBASE_VE_JS_HARD_STOP_TICKS_CL_DEBUG 166 /* 2.5s before hard-stop */ +#define KBASE_VE_JS_HARD_STOP_TICKS_NSS_DEBUG 100000 /* 1500s (25mins) before NSS hard-stop */ +#define KBASE_VE_JS_RESET_TICKS_SS_DEBUG 500 /* 45s before resetting GPU, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) */ +#define KBASE_VE_JS_RESET_TICKS_SS_8401_DEBUG 3000 /* 7.5s before resetting GPU - for issue 8401 */ +#define KBASE_VE_JS_RESET_TICKS_CL_DEBUG 500 /* 45s before resetting GPU */ +#define KBASE_VE_JS_RESET_TICKS_NSS_DEBUG 100166 /* 1502s before resetting GPU */ + +#define KBASE_VE_JS_SCHEDULING_TICK_NS 1250000000u /* 1.25s */ +#define KBASE_VE_JS_SOFT_STOP_TICKS 2 /* 2.5s before soft-stop a job */ +#define KBASE_VE_JS_SOFT_STOP_TICKS_CL 1 /* 1.25s before soft-stop a CL job */ +#define KBASE_VE_JS_HARD_STOP_TICKS_SS 4 /* 5s before hard-stop */ +#define KBASE_VE_JS_HARD_STOP_TICKS_SS_8401 24 /* 30s before hard-stop, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) - for issue 8401 */ +#define KBASE_VE_JS_HARD_STOP_TICKS_CL 2 /* 2.5s before hard-stop */ +#define KBASE_VE_JS_HARD_STOP_TICKS_NSS 1200 /* 1500s before NSS hard-stop */ +#define KBASE_VE_JS_RESET_TICKS_SS 6 /* 7.5s before resetting GPU */ +#define KBASE_VE_JS_RESET_TICKS_SS_8401 36 /* 45s before resetting GPU, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) - for issue 8401 */ +#define KBASE_VE_JS_RESET_TICKS_CL 3 /* 3.75s before resetting GPU */ +#define KBASE_VE_JS_RESET_TICKS_NSS 1201 /* 1502s before resetting GPU */ + +#define KBASE_VE_JS_RESET_TIMEOUT_MS 3000 /* 3s before cancelling stuck jobs */ +#define KBASE_VE_JS_CTX_TIMESLICE_NS 1000000 /* 1ms - an agressive timeslice for testing purposes (causes lots of scheduling out for >4 ctxs) */ +#define KBASE_VE_POWER_MANAGEMENT_CALLBACKS ((uintptr_t)&pm_callbacks) +#define KBASE_VE_CPU_SPEED_FUNC ((uintptr_t)&kbase_get_vexpress_cpu_clock_speed) + +#define HARD_RESET_AT_POWER_OFF 0 + +#ifndef CONFIG_OF +static kbase_io_resources io_resources = { + .job_irq_number = 68, + .mmu_irq_number = 69, + .gpu_irq_number = 70, + .io_memory_region = { + .start = 0xFC010000, + .end = 0xFC010000 + (4096 * 4) - 1 + } + +}; +#endif /* CONFIG_OF */ + +static int pm_callback_power_on(struct kbase_device *kbdev) +{ + /* Nothing is needed on VExpress, but we may have destroyed GPU state (if the below HARD_RESET code is active) */ + return 1; +} + +static void pm_callback_power_off(struct kbase_device *kbdev) +{ +#if HARD_RESET_AT_POWER_OFF + /* Cause a GPU hard reset to test whether we have actually idled the GPU + * and that we properly reconfigure the GPU on power up. + * Usually this would be dangerous, but if the GPU is working correctly it should + * be completely safe as the GPU should not be active at this point. + * However this is disabled normally because it will most likely interfere with + * bus logging etc. + */ + KBASE_TRACE_ADD(kbdev, CORE_GPU_HARD_RESET, NULL, NULL, 0u, 0); + kbase_os_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_HARD_RESET); +#endif +} + +static struct kbase_pm_callback_conf pm_callbacks = { + .power_on_callback = pm_callback_power_on, + .power_off_callback = pm_callback_power_off, + .power_suspend_callback = NULL, + .power_resume_callback = NULL +}; + +/* Please keep table config_attributes in sync with config_attributes_hw_issue_8408 */ +static struct kbase_attribute config_attributes[] = { +#ifdef CONFIG_MALI_DEBUG +/* Use more aggressive scheduling timeouts in debug builds for testing purposes */ + { + KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS, + KBASE_VE_JS_SCHEDULING_TICK_NS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS, + KBASE_VE_JS_SOFT_STOP_TICKS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS_CL, + KBASE_VE_JS_SOFT_STOP_TICKS_CL_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS, + KBASE_VE_JS_HARD_STOP_TICKS_SS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_CL, + KBASE_VE_JS_HARD_STOP_TICKS_CL_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS, + KBASE_VE_JS_HARD_STOP_TICKS_NSS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS, + KBASE_VE_JS_RESET_TICKS_SS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_CL, + KBASE_VE_JS_RESET_TICKS_CL_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS, + KBASE_VE_JS_RESET_TICKS_NSS_DEBUG}, +#else /* CONFIG_MALI_DEBUG */ +/* In release builds same as the defaults but scaled for 5MHz FPGA */ + { + KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS, + KBASE_VE_JS_SCHEDULING_TICK_NS}, + + { + KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS, + KBASE_VE_JS_SOFT_STOP_TICKS}, + + { + KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS_CL, + KBASE_VE_JS_SOFT_STOP_TICKS_CL}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS, + KBASE_VE_JS_HARD_STOP_TICKS_SS}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_CL, + KBASE_VE_JS_HARD_STOP_TICKS_CL}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS, + KBASE_VE_JS_HARD_STOP_TICKS_NSS}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS, + KBASE_VE_JS_RESET_TICKS_SS}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_CL, + KBASE_VE_JS_RESET_TICKS_CL}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS, + KBASE_VE_JS_RESET_TICKS_NSS}, +#endif /* CONFIG_MALI_DEBUG */ + { + KBASE_CONFIG_ATTR_JS_RESET_TIMEOUT_MS, + KBASE_VE_JS_RESET_TIMEOUT_MS}, + + { + KBASE_CONFIG_ATTR_JS_CTX_TIMESLICE_NS, + KBASE_VE_JS_CTX_TIMESLICE_NS}, + + { + KBASE_CONFIG_ATTR_POWER_MANAGEMENT_CALLBACKS, + KBASE_VE_POWER_MANAGEMENT_CALLBACKS}, + + { + KBASE_CONFIG_ATTR_CPU_SPEED_FUNC, + KBASE_VE_CPU_SPEED_FUNC}, + + { + KBASE_CONFIG_ATTR_END, + 0} +}; + +/* as config_attributes array above except with different settings for + * JS_HARD_STOP_TICKS_SS, JS_RESET_TICKS_SS that + * are needed for BASE_HW_ISSUE_8408. + */ +struct kbase_attribute config_attributes_hw_issue_8408[] = { +#ifdef CONFIG_MALI_DEBUG +/* Use more aggressive scheduling timeouts in debug builds for testing purposes */ + { + KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS, + KBASE_VE_JS_SCHEDULING_TICK_NS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS, + KBASE_VE_JS_SOFT_STOP_TICKS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS, + KBASE_VE_JS_HARD_STOP_TICKS_SS_8401_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS, + KBASE_VE_JS_HARD_STOP_TICKS_NSS_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS, + KBASE_VE_JS_RESET_TICKS_SS_8401_DEBUG}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS, + KBASE_VE_JS_RESET_TICKS_NSS_DEBUG}, +#else /* CONFIG_MALI_DEBUG */ +/* In release builds same as the defaults but scaled for 5MHz FPGA */ + { + KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS, + KBASE_VE_JS_SCHEDULING_TICK_NS}, + + { + KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS, + KBASE_VE_JS_SOFT_STOP_TICKS}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS, + KBASE_VE_JS_HARD_STOP_TICKS_SS_8401}, + + { + KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS, + KBASE_VE_JS_HARD_STOP_TICKS_NSS}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS, + KBASE_VE_JS_RESET_TICKS_SS_8401}, + + { + KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS, + KBASE_VE_JS_RESET_TICKS_NSS}, +#endif /* CONFIG_MALI_DEBUG */ + { + KBASE_CONFIG_ATTR_JS_RESET_TIMEOUT_MS, + KBASE_VE_JS_RESET_TIMEOUT_MS}, + + { + KBASE_CONFIG_ATTR_JS_CTX_TIMESLICE_NS, + KBASE_VE_JS_CTX_TIMESLICE_NS}, + + { + KBASE_CONFIG_ATTR_POWER_MANAGEMENT_CALLBACKS, + KBASE_VE_POWER_MANAGEMENT_CALLBACKS}, + + { + KBASE_CONFIG_ATTR_CPU_SPEED_FUNC, + KBASE_VE_CPU_SPEED_FUNC}, + + { + KBASE_CONFIG_ATTR_END, + 0} +}; + +static struct kbase_platform_config virtex7_platform_config = { + .attributes = config_attributes, +#ifndef CONFIG_OF + .io_resources = &io_resources +#endif +}; + +struct kbase_platform_config *kbase_get_platform_config(void) +{ + return &virtex7_platform_config; +} + +int kbase_platform_early_init(void) +{ + /* Nothing needed at this stage */ + return 0; +} + diff --git a/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_cpu_vexpress.c b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_cpu_vexpress.c new file mode 100755 index 000000000000..f0036a345453 --- /dev/null +++ b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_cpu_vexpress.c @@ -0,0 +1,178 @@ +/* + * + * (C) COPYRIGHT ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained + * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + * + */ + + + +#include <linux/io.h> +#include <mali_kbase.h> +#include "mali_kbase_cpu_vexpress.h" + +#define HZ_IN_MHZ (1000000) + +#define CORETILE_EXPRESS_A9X4_SCC_START (0x100E2000) +#define MOTHERBOARD_SYS_CFG_START (0x10000000) +#define SYS_CFGDATA_OFFSET (0x000000A0) +#define SYS_CFGCTRL_OFFSET (0x000000A4) +#define SYS_CFGSTAT_OFFSET (0x000000A8) + +#define SYS_CFGCTRL_START_BIT_VALUE (1 << 31) +#define READ_REG_BIT_VALUE (0 << 30) +#define DCC_DEFAULT_BIT_VALUE (0 << 26) +#define SYS_CFG_OSC_FUNC_BIT_VALUE (1 << 20) +#define SITE_DEFAULT_BIT_VALUE (1 << 16) +#define BOARD_STACK_POS_DEFAULT_BIT_VALUE (0 << 12) +#define DEVICE_DEFAULT_BIT_VALUE (2 << 0) +#define SYS_CFG_COMPLETE_BIT_VALUE (1 << 0) +#define SYS_CFG_ERROR_BIT_VALUE (1 << 1) + +#define FEED_REG_BIT_MASK (0x0F) +#define FCLK_PA_DIVIDE_BIT_SHIFT (0x03) +#define FCLK_PB_DIVIDE_BIT_SHIFT (0x07) +#define FCLK_PC_DIVIDE_BIT_SHIFT (0x0B) +#define AXICLK_PA_DIVIDE_BIT_SHIFT (0x0F) +#define AXICLK_PB_DIVIDE_BIT_SHIFT (0x13) + +#define IS_SINGLE_BIT_SET(val, pos) (val&(1<<pos)) + +#define CPU_CLOCK_SPEED_UNDEFINED 0 + +static u32 cpu_clock_speed = CPU_CLOCK_SPEED_UNDEFINED; + +static DEFINE_RAW_SPINLOCK(syscfg_lock); +/** + * kbase_get_vendor_specific_cpu_clock_speed + * @brief Retrieves the CPU clock speed. + * The implementation is platform specific. + * @param[out] cpu_clock - the value of CPU clock speed in MHz + * @return 0 on success, 1 otherwise +*/ +int kbase_get_vexpress_cpu_clock_speed(u32 *cpu_clock) +{ + + + if (CPU_CLOCK_SPEED_UNDEFINED != cpu_clock_speed) + { + *cpu_clock = cpu_clock_speed; + return 0; + } + else + { + int result = 0; + u32 reg_val = 0; + u32 osc2_value = 0; + u32 pa_divide = 0; + u32 pb_divide = 0; + u32 pc_divide = 0; + void *volatile pSysCfgReg = 0; + void *volatile pSCCReg = 0; + + /* Init the value case something goes wrong */ + *cpu_clock = 0; + + /* Map CPU register into virtual memory */ + pSysCfgReg = ioremap(MOTHERBOARD_SYS_CFG_START, 0x1000); + if (pSysCfgReg == NULL) { + result = 1; + + goto pSysCfgReg_map_failed; + } + + pSCCReg = ioremap(CORETILE_EXPRESS_A9X4_SCC_START, 0x1000); + if (pSCCReg == NULL) { + result = 1; + + goto pSCCReg_map_failed; + } + + raw_spin_lock(&syscfg_lock); + + /*Read SYS regs - OSC2 */ + reg_val = readl(pSysCfgReg + SYS_CFGCTRL_OFFSET); + + /*Verify if there is no other undergoing request */ + if (!(reg_val & SYS_CFGCTRL_START_BIT_VALUE)) { + /*Reset the CGFGSTAT reg */ + writel(0, (pSysCfgReg + SYS_CFGSTAT_OFFSET)); + + writel(SYS_CFGCTRL_START_BIT_VALUE | READ_REG_BIT_VALUE | DCC_DEFAULT_BIT_VALUE | SYS_CFG_OSC_FUNC_BIT_VALUE | SITE_DEFAULT_BIT_VALUE | BOARD_STACK_POS_DEFAULT_BIT_VALUE | DEVICE_DEFAULT_BIT_VALUE, (pSysCfgReg + SYS_CFGCTRL_OFFSET)); + /* Wait for the transaction to complete */ + while (!(readl(pSysCfgReg + SYS_CFGSTAT_OFFSET) & SYS_CFG_COMPLETE_BIT_VALUE)) + ; + /* Read SYS_CFGSTAT Register to get the status of submitted transaction */ + reg_val = readl(pSysCfgReg + SYS_CFGSTAT_OFFSET); + + /*------------------------------------------------------------------------------------------*/ + /* Check for possible errors */ + if (reg_val & SYS_CFG_ERROR_BIT_VALUE) { + /* Error while setting register */ + result = 1; + } else { + osc2_value = readl(pSysCfgReg + SYS_CFGDATA_OFFSET); + /* Read the SCC CFGRW0 register */ + reg_val = readl(pSCCReg); + + /* + Select the appropriate feed: + CFGRW0[0] - CLKOB + CFGRW0[1] - CLKOC + CFGRW0[2] - FACLK (CLK)B FROM AXICLK PLL) + */ + /* Calculate the FCLK */ + if (IS_SINGLE_BIT_SET(reg_val, 0)) { /*CFGRW0[0] - CLKOB */ + /* CFGRW0[6:3] */ + pa_divide = ((reg_val & (FEED_REG_BIT_MASK << FCLK_PA_DIVIDE_BIT_SHIFT)) >> FCLK_PA_DIVIDE_BIT_SHIFT); + /* CFGRW0[10:7] */ + pb_divide = ((reg_val & (FEED_REG_BIT_MASK << FCLK_PB_DIVIDE_BIT_SHIFT)) >> FCLK_PB_DIVIDE_BIT_SHIFT); + *cpu_clock = osc2_value * (pa_divide + 1) / (pb_divide + 1); + } else { + if (IS_SINGLE_BIT_SET(reg_val, 1)) { /*CFGRW0[1] - CLKOC */ + /* CFGRW0[6:3] */ + pa_divide = ((reg_val & (FEED_REG_BIT_MASK << FCLK_PA_DIVIDE_BIT_SHIFT)) >> FCLK_PA_DIVIDE_BIT_SHIFT); + /* CFGRW0[14:11] */ + pc_divide = ((reg_val & (FEED_REG_BIT_MASK << FCLK_PC_DIVIDE_BIT_SHIFT)) >> FCLK_PC_DIVIDE_BIT_SHIFT); + *cpu_clock = osc2_value * (pa_divide + 1) / (pc_divide + 1); + } else if (IS_SINGLE_BIT_SET(reg_val, 2)) { /*CFGRW0[2] - FACLK */ + /* CFGRW0[18:15] */ + pa_divide = ((reg_val & (FEED_REG_BIT_MASK << AXICLK_PA_DIVIDE_BIT_SHIFT)) >> AXICLK_PA_DIVIDE_BIT_SHIFT); + /* CFGRW0[22:19] */ + pb_divide = ((reg_val & (FEED_REG_BIT_MASK << AXICLK_PB_DIVIDE_BIT_SHIFT)) >> AXICLK_PB_DIVIDE_BIT_SHIFT); + *cpu_clock = osc2_value * (pa_divide + 1) / (pb_divide + 1); + } else { + result = 1; + } + } + } + } else { + result = 1; + } + raw_spin_unlock(&syscfg_lock); + /* Convert result expressed in Hz to Mhz units. */ + *cpu_clock /= HZ_IN_MHZ; + if (!result) + { + cpu_clock_speed = *cpu_clock; + } + + /* Unmap memory */ + iounmap(pSCCReg); + + pSCCReg_map_failed: + iounmap(pSysCfgReg); + + pSysCfgReg_map_failed: + + return result; + } +} diff --git a/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_cpu_vexpress.h b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_cpu_vexpress.h new file mode 100755 index 000000000000..3f6c68ece392 --- /dev/null +++ b/drivers/gpu/arm/midgard/platform/vexpress_virtex7_40mhz/mali_kbase_cpu_vexpress.h @@ -0,0 +1,26 @@ +/* + * + * (C) COPYRIGHT ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained + * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + * + */ + + + +#ifndef _KBASE_CPU_VEXPRESS_H_ +#define _KBASE_CPU_VEXPRESS_H_ + +/** + * Versatile Express implementation of @ref kbase_cpuprops_clock_speed_function. + */ +int kbase_get_vexpress_cpu_clock_speed(u32 *cpu_clock); + +#endif /* _KBASE_CPU_VEXPRESS_H_ */ |