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This fix rounds the clock rate properly by using quotient and not
remainder in the calculation. This issue was found while testing HDMI
in the Juno platform.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
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This reverts commit b99e1f2a1a3f4158bed9b9e9e97ac46678d8c2ac.
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This reverts commit 29acc42e8e10a4721757af9ed8aec569d30ce39b.
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This reverts commit 3aceaa34d7723c2556555b05ad04a89ce2d66374.
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Signed-off-by: Koen Kooi <koen.kooi@linaro.org>
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Signed-off-by: Arvind Chauhan <arvind.chauhan@arm.com>
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Signed-off-by: Arvind Chauhan <arvind.chauhan@arm.com>
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Signed-off-by: Arvind Chauhan <arvind.chauhan@arm.com>
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Signed-off-by: Arvind Chauhan <arvind.chauhan@arm.com>
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Enable same SCMI configs that Sudeep added in his v4.18/scmi_mhu_dt_changes
branch:
b3f9cbf8 2017-06-19 arm64: defconfig: add all SCMI related configs [Sudeep Holla]
Some others configs are added that Sudeep didn't need to add because they
were already in defconfig.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
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With SMCI firmware and a 4.12 kernel, Juno in AArch32 mode needs
PM_GENERIC_DOMAINS selected to be able to boot, otherwise it hangs after
this line:
[ 0.928854] Serial: AMBA PL011 UART driver
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
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Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Some mailbox controllers are lack FIFOs or memory to transmit data.
They typically contains single doorbell registers to just signal the
remote. The actually data is transmitted/shared using some shared memory
which is not part of the mailbox.
Such controllers don't need to transmit any data, they just transmit
the signal. In such controllers the data pointer passed to
mbox_send_message is passed to client via it's tx_prepare callback.
Controller doesn't need any data to be passed from the client.
This patch introduce the new API send_signal to support such doorbell/
signal mode in mailbox controllers. This is useful to avoid another
layer of abstraction as typically multiple channels can be multiplexied
into single register.
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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It's sometimes useful to identify the mailbox controller with the name
as specified in the devicetree via mbox-name property especially in a
system with multiple controllers.
This patch adds support to read and record the mailbox controller name.
Cc: Alexey Klimov <alexey.klimov@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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We now have the basic infrastructure and binding to support doorbells
on ARM MHU controller.
This patch adds all the necessary mailbox operations to add support for
the doorbells. Maximum of 32 doorbells are supported on each physical
channel, however the total number of doorbells is restricted to 20
in order to save memory. It can increased if required in future.
Cc: Alexey Klimov <alexey.klimov@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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In order to support doorbells, we need a bit of reword around data
structures that are per-channel. Since the number of doorbells are
not fixed though restricted to maximum of 20, the channel assignment
and initialization is move to xlate function.
This patch also adds the platform data for the existing support of one
channel per physical channel.
Cc: Alexey Klimov <alexey.klimov@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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In preparation to introduce support for doorbells which require the
interrupt handlers to be threaded, this patch moves the existing
interrupt handler to threaded handler.
Also it moves out the registering and freeing of the handlers from
the mailbox startup and shutdown methods. This also is required to
support doorbells.
Cc: Alexey Klimov <alexey.klimov@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The ARM MHU has mechanism to assert interrupt signals to facilitate
inter-processor message based communication. It drives the signal using
a 32-bit register, with all 32-bits logically ORed together. It also
enables software to set, clear and check the status of each of the bits
of this register independently. Each bit of the register can be
associated with a type of event that can contribute to raising the
interrupt thereby allowing it to be used as independent doorbells.
Since the first version of this binding can't support doorbells,
this patch extends the existing binding to support them by allowing
"#mbox-cells" to be 2.
Cc: Alexey Klimov <alexey.klimov@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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This patch just re-orders some of the headers includes and also drop
the ones that are unnecessary.
Cc: Alexey Klimov <alexey.klimov@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r1 to r2.
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[arranged nodes in ascending order with respect to register addresses]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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In contrast with the non-multi-threading DTS, this enumerates MPIDR
values shifted by one affinity level to the left. The newly added DTS
reflects CPUs with a single thread in them.
Since both DTS files are the same apart from MPIDR contents, the common
bits have been moved to a separate file that's then included from the
top-level DTS files. The multi-threading version only updates the MPIDR
contents.
cherry-picked from:
https://github.com/ARM-software/arm-trusted-firmware/pull/1046/commits/1bdbdc3b3f3068797a1539eacff727592762d5b9
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
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FVP Base models aren't really that compatible with Versatile Express and
the only thing in Linux that tests for that string is the platform code
which registers smp ops in 32-bit kernels. As we use PSCI for CPU
bringup remove this compatible string and let 32-bit kernels work wore
reliably.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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For generic device-tree based cpuidle as used by systems with PSCI.
Specifically needed by Base FVPs running with 32-bit kernels.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This FVP can be run with CPUs set to 32-bit mode, so add links to
the arm64 device-trees so be can easily build 32-bit kernels for that
scenario.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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ARMv8 targets such as ARM's FVP Cortex-A32 model can run the 32-bit
ARMv7 kernel. And these targets often contain GICv3.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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So we use PSCI for those purposes instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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ARM Platform Release's are intended to work with ARM Trusted Firmware
which implements PSCI.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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but mark it disabled, so CLCD is used by default.
To use HDLCD, s/&hdlcd/&clcd/ to mark CLCD disabled instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Fixed Virtual Platform (FVP) Base models are simulations of systems
that resemble Versatile Express or Juno hardware.
This adds a device-tree for the model variant that has two clusters of
Architecture Envelope Model (AEM) v8-A CPUs. The peripheral devices that
are common to all variants of Base models have been placed in a separate
file (fvp-base.dtsi) to facilitate creating device-trees for other
models.
It is desirable to use simulations for code testing purposes and so it
is beneficial to include nodes for things that are timing and power
consumption related, even when these don't otherwise have relevance or
accuracy. Where these have been included here (e.g. idle-states) entries
have been copied from real hardware platforms such as Juno.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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List the required properties used to describe ARM's FVP models.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The silicon doesn't seem to be able to cope with max frequency on the big core.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Juno isn't really that compatible with Versatile Express and the only
thing in Linux that tests for that string is the platform code which
registers smp ops in 32-bit kernels. These won't work on Juno as it uses
PSCI, so remove this compatible string and let 32-bit kernels work
properly.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Juno can be run with CPUs set to 32-bit mode, so add links to the arm64
device-trees so be can easily build 32-bit kernels for that scenario.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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These can be run by passing kernel commandline parameters, e.g.
arm_scpi_test.stress_time=60 arm_scpi_test.run=3
or from a shell after boot like:
echo 60 > /sys/module/arm_scpi_test/parameters/stress_time
echo 3 > /sys/module/arm_scpi_test/parameters/run
The 'run' parameter gives the number of the test case to run, or -1
to indicate all tests. Setting run to zero will stop currently running
tests.
'stress_time' is the number of seconds each stress test is run for
and if omitted a default for each test will be used.
Test progress is output with pr_info, pr_err etc, so will appear in the
kernel log and on a console if the kernel log is also directed there.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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scpi_send_message is broken for a least two reasons.
1. The driver sets tx_block on the mailbox client and expects mbox_send_message
to block until the message is sent, however this isn't the case. Whether by
design or in error, mbox_send_message waits for tx_complete which will be
signalled when any message is transmitted, not the one just queued. So in the
case where two threads send messages concurrently, one thread may see the signal
from the other's message completing, whilst it's message is still in the queue.
2. The second flaw is that even if the mailbox framework was waiting for the
correct message signal the driver has set a timeout (mailbox client tx_tout)
which means the wait for that signal may be aborted whilst the message is still
in the queue for sending.
Both the above mean that when mbox_send_message returns the message may still be
pending transmission so we cannot safely do anything with its resources. The
current code however goes on to free the message with put_scpi_xfer resulting
in all sorts of bugs.
To fix this, we add code to do a proper wait for the message to complete and
if a timeout occurs BUG because we don't have any way to cancel messages in the
queue.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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For designs where EEPROMs are not connected to PCI Yukon2
chips we need to get the MAC address from the firmware.
Add a module parameter called 'mac_address' for this. It
will be used if no DT node can be found and the B2_MAC
register holds an invalid value.
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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We need this available to use as a broadcast timer on Juno r0 which has
a broken memory mapped architected timer.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Mali driver is hard coded to the name "clk_mali" and latest kernels
use the clock-output-names in preference to any phandles when looking
for clocks, so this name shold match expectations.
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When the device is shutdown, the state change can trigger a notifier
which tries to gather network statistics by calling sky2_get_stats.
Unfortunately, this attempts to read registers in hardware which may
have been powered down leading to a bus abort (see below). Partially
workaround this by checking device power state in sky2_get_stats.
Unhandled fault: synchronous external abort (0x96000210) at 0xffffff800017a918
Internal error: : 96000210 [#1] PREEMPT SMP
CPU: 0 PID: 229 Comm: kworker/0:2 Not tainted 3.18.31-00004-g60c1593-dirty #2
Hardware name: ARM Juno development board (r2) (DT)
Workqueue: events linkwatch_event
task: ffffffc97665c0c0 ti: ffffffc9766e0000 task.ti: ffffffc9766e0000
PC is at sky2_get_stats+0x74/0x40c
LR is at sky2_get_stats+0x408/0x40c
Call trace:
[<ffffffc0005eb3b4>] sky2_get_stats+0x74/0x40c
[<ffffffc0007a8978>] dev_get_stats+0x68/0xd0
[<ffffffc0007b651c>] rtnl_fill_ifinfo+0x388/0x8e0
[<ffffffc0007b9764>] rtmsg_ifinfo+0x78/0x10c
[<ffffffc0007a34b4>] netdev_state_change+0x48/0x54
[<ffffffc0007bacfc>] linkwatch_do_dev+0x50/0x88
[<ffffffc0007bb004>] __linkwatch_run_queue+0x164/0x198
[<ffffffc0007bb068>] linkwatch_event+0x30/0x3c
[<ffffffc0000b7084>] process_one_work+0x150/0x458
[<ffffffc0000b74d8>] worker_thread+0x14c/0x47c
[<ffffffc0000bd1f0>] kthread+0xe0/0xf4
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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