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/*
* ARM Ltd. Fixed Virtual Platform (FVP) Base model with dual cluster
* Architecture Envelope Model (AEM) v8-A CPUs
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "FVP_Base_AEMv8A-AEMv8A";
compatible = "arm,fvp-base,aemv8a-aemv8a", "arm,fvp-base";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &bp_serial0;
serial1 = &bp_serial1;
serial2 = &bp_serial2;
serial3 = &bp_serial3;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0_0>;
};
core1 {
cpu = <&CPU0_1>;
};
core2 {
cpu = <&CPU0_2>;
};
core3 {
cpu = <&CPU0_3>;
};
};
cluster1 {
core0 {
cpu = <&CPU1_0>;
};
core1 {
cpu = <&CPU1_1>;
};
core2 {
cpu = <&CPU1_2>;
};
core3 {
cpu = <&CPU1_3>;
};
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
CPU0_0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU0_1: cpu@1 {
compatible = "arm,armv8";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU0_2: cpu@2 {
compatible = "arm,armv8";
reg = <0x0 0x2>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU0_3: cpu@3 {
compatible = "arm,armv8";
reg = <0x0 0x3>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU1_0: cpu@100 {
compatible = "arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU1_1: cpu@101 {
compatible = "arm,armv8";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU1_2: cpu@102 {
compatible = "arm,armv8";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU1_3: cpu@103 {
compatible = "arm,armv8";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0_0>,
<&CPU0_1>,
<&CPU0_2>,
<&CPU0_3>,
<&CPU1_0>,
<&CPU1_1>,
<&CPU1_2>,
<&CPU1_3>;
};
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x100000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
pci: pci@40000000 {
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
compatible = "pci-host-ecam-generic";
device_type = "pci";
bus-range = <0x0 0x1>;
reg = <0x0 0x40000000 0x0 0x10000000>;
ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0xa8 0x4>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0xa9 0x4>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0xaa 0x4>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0xab 0x4>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
msi-parent = <&its>;
msi-map = <0x0 &its 0x0 0x10000>;
iommu-map = <0x0 &smmu 0x0 0x10000>;
dma-coherent;
ats-supported;
};
smmu: smmu@2b400000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x2b400000 0x0 0x20000>;
interrupts = <0 74 1>, <0 75 1>, <0 77 1>, <0 79 1>;
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
dma-coherent;
#iommu-cells = <1>;
msi-parent = <&its 0x10000>;
};
#include "fvp-base.dtsi"
};
&hdlcd {
status = "disabled";
};
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