From a671c16c974be59fb88485b0a206ed3cf185e22b Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Mon, 20 Jun 2016 11:53:17 +0100 Subject: Documentation: bindings: Add DT bindings for ARM's FVP models. List the required properties used to describe ARM's FVP models. Signed-off-by: Jon Medhurst --- Documentation/devicetree/bindings/arm/arm-boards | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index b6e810c2781a..d28b61c93cf8 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -235,3 +235,24 @@ Example: }; }; + +ARM Fixed Virtual Platforms (FVP) +--------------------------------- +FVPs are simulated platforms produced by ARM to aid software development without +the requirement for actual hardware. They come in several families, each of +which (usually) contain variants for different configurations of simulated +hardware. These are documented in the Fixed Virtual Platforms FVP Reference +Guide (reference number ARM DUI0837H). + +Required properties (in root node): +- compatible value: + compatible = "arm,,", "arm,"; + where is one of: + - "fvp-base" for the Base FVP + - "fvp-ve" for the VE FVP + and is the part of the model's executable filename with the family + name omitted, converted to lower case, and with non-alphanumeric characters + replaced with '-'. E.g. the Base FVP that has two AEMv8 CPU clusters has an + executable file called FVP_Base_AEMv8A-AEMv8A, so the compatible value for + this would be: + compatible = "arm,fvp-base,aemv8a-aemv8a", "arm,fvp-base"; -- cgit v1.2.3 From 9e7d9359628d27a64824529992ddc9f8838e4d68 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Wed, 10 Jun 2015 11:12:42 +0100 Subject: arm64: dts: Add device-tree for ARM's AEMv8A-AEMv8A FVP Base model Fixed Virtual Platform (FVP) Base models are simulations of systems that resemble Versatile Express or Juno hardware. This adds a device-tree for the model variant that has two clusters of Architecture Envelope Model (AEM) v8-A CPUs. The peripheral devices that are common to all variants of Base models have been placed in a separate file (fvp-base.dtsi) to facilitate creating device-trees for other models. It is desirable to use simulations for code testing purposes and so it is beneficial to include nodes for things that are timing and power consumption related, even when these don't otherwise have relevance or accuracy. Where these have been included here (e.g. idle-states) entries have been copied from real hardware platforms such as Juno. Signed-off-by: Jon Medhurst --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts | 223 +++++++++++++++++ arch/arm64/boot/dts/arm/fvp-base.dtsi | 267 +++++++++++++++++++++ 3 files changed, 491 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts create mode 100644 arch/arm64/boot/dts/arm/fvp-base.dtsi diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 75cc2aa10101..7531001f6321 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-aemv8a-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb diff --git a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts new file mode 100644 index 000000000000..682e64128c1b --- /dev/null +++ b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts @@ -0,0 +1,223 @@ +/* + * ARM Ltd. Fixed Virtual Platform (FVP) Base model with dual cluster + * Architecture Envelope Model (AEM) v8-A CPUs + */ + +/dts-v1/; + +#include + +/ { + model = "FVP_Base_AEMv8A-AEMv8A"; + compatible = "arm,fvp-base,aemv8a-aemv8a", "arm,fvp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &bp_serial0; + serial1 = &bp_serial1; + serial2 = &bp_serial2; + serial3 = &bp_serial3; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0_0>; + }; + core1 { + cpu = <&CPU0_1>; + }; + core2 { + cpu = <&CPU0_2>; + }; + core3 { + cpu = <&CPU0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU1_0>; + }; + core1 { + cpu = <&CPU1_1>; + }; + core2 { + cpu = <&CPU1_2>; + }; + core3 { + cpu = <&CPU1_3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + }; + }; + + CPU0_0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU0_1: cpu@1 { + compatible = "arm,armv8"; + reg = <0x0 0x1>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU0_2: cpu@2 { + compatible = "arm,armv8"; + reg = <0x0 0x2>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU0_3: cpu@3 { + compatible = "arm,armv8"; + reg = <0x0 0x3>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_0: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_1: cpu@101 { + compatible = "arm,armv8"; + reg = <0x0 0x101>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_2: cpu@102 { + compatible = "arm,armv8"; + reg = <0x0 0x102>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_3: cpu@103 { + compatible = "arm,armv8"; + reg = <0x0 0x103>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CLUSTER0_L2: l2-cache0 { + compatible = "cache"; + }; + + CLUSTER1_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&CPU0_0>, + <&CPU0_1>, + <&CPU0_2>, + <&CPU0_3>, + <&CPU1_0>, + <&CPU1_1>, + <&CPU1_2>, + <&CPU1_3>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0x0 0x10000>, + <0x0 0x2f100000 0x0 0x100000>, + <0x0 0x2c000000 0x0 0x2000>, + <0x0 0x2c010000 0x0 0x2000>, + <0x0 0x2c02f000 0x0 0x2000>; + interrupts = ; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x2f020000 0x0 0x20000>; + }; + }; + + #include "fvp-base.dtsi" +}; diff --git a/arch/arm64/boot/dts/arm/fvp-base.dtsi b/arch/arm64/boot/dts/arm/fvp-base.dtsi new file mode 100644 index 000000000000..ea3f170ad6fa --- /dev/null +++ b/arch/arm64/boot/dts/arm/fvp-base.dtsi @@ -0,0 +1,267 @@ + bp_clock35mhz: clock35mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <35000000>; + clock-output-names = "bp:clock35mhz"; + }; + + bp_clock24mhz: clock24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; + + flash@8000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0x0 0x08000000 0x0 0x04000000>, + <0x0 0x0C000000 0x0 0x04000000>; + bank-width = <4>; + }; + + bp_video_ram: vram@18000000 { + compatible = "arm,vexpress-vram"; + reg = <0x0 0x18000000 0x0 0x00800000>; + }; + + ethernet@1a000000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1a000000 0x0 0x10000>; + interrupts = ; + }; + + bp_sysreg: sysreg@1c010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x0 0x1c010000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&bp_sysreg>; + + bp_oscclk1: oscclk1 { + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "bp:oscclk1"; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + }; + + sysctl_refclk: sysctl-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "sysctl:refclk"; + }; + + sysctl_timclk: sysctl-timclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sysctl:timclk"; + }; + + bp_sysctl: sysctl@1c020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x0 0x1c020000 0x0 0x1000>; + clocks = <&sysctl_refclk>, <&sysctl_timclk>, <&bp_clock35mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&bp_sysctl 0>, <&bp_sysctl 1>, <&bp_sysctl 3>, <&bp_sysctl 3>; + assigned-clock-parents = <&sysctl_timclk>, <&sysctl_timclk>, <&sysctl_timclk>, <&sysctl_timclk>; + }; + + aaci@1c040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x0 0x1c040000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>; + clock-names = "apb_pclk"; + }; + + bp_fixed_3v3: bp-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mmci@1c050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x0 0x1c050000 0x0 0x1000>; + interrupts = , + ; + cd-gpios = <&bp_sysreg 0 0>; + wp-gpios = <&bp_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&bp_fixed_3v3>; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@1c060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c060000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@1c070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c070000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + bp_serial0: uart@1c090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x1c090000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + bp_serial1: uart@1c0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x1c0a0000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + bp_serial2: uart@1c0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x1c0b0000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + bp_serial3: uart@1c0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x1c0c0000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@1c0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + bp_timer01: timer@1c110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0x1c110000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_sysctl 0>, <&bp_sysctl 1>, <&bp_clock35mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + bp_timer23: timer@1c120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0x1c120000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_sysctl 2>, <&bp_sysctl 3>, <&bp_clock35mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + virtio_block@1c0130000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c130000 0x0 0x200>; + interrupts = ; + }; + + rtc@1c170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x1c170000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_clock24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1c1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x0 0x1c1f0000 0x0 0x1000>; + interrupt-names = "combined"; + interrupts = ; + clocks = <&bp_oscclk1>, <&bp_clock24mhz>; + clock-names = "clcdclk", "apb_pclk"; + arm,pl11x,framebuffer = <0x18000000 0x00180000>; + memory-region = <&bp_video_ram>; + max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + + port { + bp_clcd_pads: endpoint { + remote-endpoint = <&bp_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + bp_clcd_panel: endpoint { + remote-endpoint = <&bp_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x1000>; + clock-frequency = <50000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x2a830000 0x0 0x1000>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; -- cgit v1.2.3 From dca85947e8c93304fc2767e749e74c3face239ba Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Wed, 23 Mar 2016 11:10:53 +0000 Subject: arm64: dts: Add HDLCD to Base FVP but mark it disabled, so CLCD is used by default. To use HDLCD, s/&hdlcd/&clcd/ to mark CLCD disabled instead. Signed-off-by: Jon Medhurst --- arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts | 5 +++ arch/arm64/boot/dts/arm/fvp-base.dtsi | 49 +++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts index 682e64128c1b..eb9d35a61243 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts @@ -221,3 +221,8 @@ #include "fvp-base.dtsi" }; + +&hdlcd { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/arm/fvp-base.dtsi b/arch/arm64/boot/dts/arm/fvp-base.dtsi index ea3f170ad6fa..3ffbb83955e1 100644 --- a/arch/arm64/boot/dts/arm/fvp-base.dtsi +++ b/arch/arm64/boot/dts/arm/fvp-base.dtsi @@ -205,7 +205,7 @@ clock-names = "apb_pclk"; }; - clcd@1c1f0000 { + clcd: clcd@1c1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x0 0x1c1f0000 0x0 0x1000>; interrupt-names = "combined"; @@ -260,6 +260,53 @@ }; }; + fake_hdlcd_clk: fake-hdlcd-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <63500000>; + clock-output-names = "pxlclk"; + }; + + + hdlcd: hdlcd@7ff60000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff60000 0 0x1000>; + interrupts = ; + clocks = <&fake_hdlcd_clk>; + clock-names = "pxlclk"; + + port { + hdlcd_out: endpoint { + remote-endpoint = <&bp_hdlcd_display>; + }; + }; + }; + + vencoder { + compatible = "drm,virtual-encoder"; + + port { + bp_hdlcd_display: endpoint { + remote-endpoint = <&hdlcd_out>; + }; + }; + + display-timings { + panel-timing { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; + + }; + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x80000000>, -- cgit v1.2.3 From 780f8af3f2b2d23cae4d74c6c7cc899414fb38c1 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Mon, 16 May 2016 11:20:39 +0100 Subject: arm64: dts: Use PSCI enable-method for Foundation model CPUs ARM Platform Release's are intended to work with ARM Trusted Firmware which implements PSCI. Signed-off-by: Jon Medhurst --- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 7cfa8e414e7f..c362ef71d493 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -24,6 +24,11 @@ serial3 = &v2m_serial3; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -32,32 +37,28 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; -- cgit v1.2.3 From e11b463410120a91926e7f5779437f74573a02ff Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Tue, 25 Oct 2016 17:32:23 +0100 Subject: arm64: dts: Add CPU idle state for Foundation model Signed-off-by: Jon Medhurst --- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 54 +++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index c362ef71d493..7f536637d4ce 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -33,32 +33,78 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; }; - cpu@1 { + + CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; }; - cpu@2 { + + CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; }; - cpu@3 { + + CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; }; -- cgit v1.2.3 From d6cd458cb18f0e20350d55c7674170eb767831cd Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Tue, 25 Oct 2016 18:10:35 +0100 Subject: arm64: dts: Remove shutdown and reboot from mcc on FVP Base model So we use PSCI for those purposes instead. Signed-off-by: Jon Medhurst --- arch/arm64/boot/dts/arm/fvp-base.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/arm/fvp-base.dtsi b/arch/arm64/boot/dts/arm/fvp-base.dtsi index 3ffbb83955e1..bf919fa76ff3 100644 --- a/arch/arm64/boot/dts/arm/fvp-base.dtsi +++ b/arch/arm64/boot/dts/arm/fvp-base.dtsi @@ -53,16 +53,6 @@ compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; }; sysctl_refclk: sysctl-refclk { -- cgit v1.2.3 From 4ccbdffb32121a56f2a284e109df9dd776da5228 Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Wed, 16 Nov 2016 14:43:02 +0000 Subject: ARM: vexpress: enable GICv3 ARMv8 targets such as ARM's FVP Cortex-A32 model can run the 32-bit ARMv7 kernel. And these targets often contain GICv3. Signed-off-by: Ryan Harkin Signed-off-by: Jon Medhurst --- arch/arm/mach-vexpress/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 7c728ebc0b33..ed579382d41f 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -4,6 +4,7 @@ menuconfig ARCH_VEXPRESS select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_GIC + select ARM_GIC_V3 select ARM_GLOBAL_TIMER select ARM_TIMER_SP804 select COMMON_CLK_VERSATILE -- cgit v1.2.3 From e33bf7cddd727701a41dfe6d0fdb4cb8892bdb76 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Thu, 17 Nov 2016 14:12:33 +0000 Subject: arm: dts: fvp: Add links to device-tree for FVP_Base_AEMv8A-AEMv8A This FVP can be run with CPUs set to 32-bit mode, so add links to the arm64 device-trees so be can easily build 32-bit kernels for that scenario. Signed-off-by: Jon Medhurst --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dts | 1 + arch/arm/boot/dts/fvp-base.dtsi | 1 + 3 files changed, 3 insertions(+) create mode 120000 arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dts create mode 120000 arch/arm/boot/dts/fvp-base.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 01d178a2009f..ae9bbd755255 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -912,6 +912,7 @@ dtb-$(CONFIG_ARCH_VERSATILE) += \ versatile-ab.dtb \ versatile-pb.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += \ + fvp-base-aemv8a-aemv8a.dtb \ vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ diff --git a/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dts b/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dts new file mode 120000 index 000000000000..4f545027a7b4 --- /dev/null +++ b/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dts @@ -0,0 +1 @@ +../../../arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/fvp-base.dtsi b/arch/arm/boot/dts/fvp-base.dtsi new file mode 120000 index 000000000000..9cb4e3c1cbf1 --- /dev/null +++ b/arch/arm/boot/dts/fvp-base.dtsi @@ -0,0 +1 @@ +../../../arm64/boot/dts/arm/fvp-base.dtsi \ No newline at end of file -- cgit v1.2.3 From 5216676dd86c56bd702432f9d9ec95002768e502 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Fri, 18 Nov 2016 13:47:10 +0000 Subject: configs: vexpress: Enable CONFIG_ARM_CPUIDLE For generic device-tree based cpuidle as used by systems with PSCI. Specifically needed by Base FVPs running with 32-bit kernels. Signed-off-by: Jon Medhurst --- linaro/configs/vexpress.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/linaro/configs/vexpress.conf b/linaro/configs/vexpress.conf index 8370cf15be65..562212a29b6e 100644 --- a/linaro/configs/vexpress.conf +++ b/linaro/configs/vexpress.conf @@ -7,6 +7,7 @@ CONFIG_ARM_PSCI=y CONFIG_MCPM=y CONFIG_ARCH_VEXPRESS_DCSCB=y CONFIG_ARCH_VEXPRESS_TC2_PM=y +CONFIG_ARM_CPUIDLE=y CONFIG_ARM_BIG_LITTLE_CPUIDLE=y CONFIG_BIG_LITTLE=y CONFIG_ARM_BIG_LITTLE_CPUFREQ=y -- cgit v1.2.3