clk: hisilicon: add flag hiword

timerX_mux should not use CLK_MUX_HIWORD_MASK
add hiword to distinguish
Introduced from commit 0b47626 ARM: dts: fix the clock setting of sp804 timer

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

2 files changed, 29 insertions, 2 deletions

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index bfadfc27106a..f77815b206a9 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -116,6 +116,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &pclk>;
+				hiword;
 				clock-output-names = "rclk_uart0";
 				/* reg_offset, enable_bits */
 				hisilicon,clkmux-reg = <0x100 0x80>;
@@ -125,6 +126,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &pclk>;
+				hiword;
 				clock-output-names = "rclk_uart1";
 				hisilicon,clkmux-reg = <0x100 0x100>;
 				hisilicon,clkmux-table = <0 0x100>;
@@ -133,6 +135,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &pclk>;
+				hiword;
 				clock-output-names = "rclk_uart2";
 				hisilicon,clkmux-reg = <0x100 0x200>;
 				hisilicon,clkmux-table = <0 0x200>;
@@ -141,6 +144,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &pclk>;
+				hiword;
 				clock-output-names = "rclk_uart3";
 				hisilicon,clkmux-reg = <0x100 0x400>;
 				hisilicon,clkmux-table = <0 0x400>;
@@ -149,6 +153,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &pclk>;
+				hiword;
 				clock-output-names = "rclk_uart4";
 				hisilicon,clkmux-reg = <0x100 0x800>;
 				hisilicon,clkmux-table = <0 0x800>;
@@ -158,6 +163,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_usb &pll_peri>;
+				hiword;
 				clock-output-names = "rclk_hsic";
 				hisilicon,clkmux-reg = <0x130 0x4>;
 				hisilicon,clkmux-table = <0 0x4>;
@@ -184,6 +190,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &refclk_cfgaxi>;
+				hiword;
 				clock-output-names = "rclk_spi0";
 				hisilicon,clkmux-reg = <0x100 0x1000>;
 				hisilicon,clkmux-table = <0 0x1000>;
@@ -192,6 +199,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &refclk_cfgaxi>;
+				hiword;
 				clock-output-names = "rclk_spi1";
 				hisilicon,clkmux-reg = <0x100 0x2000>;
 				hisilicon,clkmux-table = <0 0x2000>;
@@ -200,6 +208,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &refclk_cfgaxi>;
+				hiword;
 				clock-output-names = "rclk_spi2";
 				hisilicon,clkmux-reg = <0x100 0x4000>;
 				hisilicon,clkmux-table = <0 0x4000>;
@@ -279,6 +288,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_usb &pll_peri>;
+				hiword;
 				clock-output-names = "rclk_shareAXI";
 				hisilicon,clkmux-reg = <0x24 0x8000>;
 				hisilicon,clkmux-table = <0 0x8000>;
@@ -287,6 +297,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				hiword;
 				clock-output-names = "rclk_mmc1";
 				hisilicon,clkmux-reg = <0x108 0x200>;
 				hisilicon,clkmux-table = <0 0x200>;
@@ -295,6 +306,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				hiword;
 				clock-output-names = "rclk_mmc2";
 				hisilicon,clkmux-reg = <0x140 0x10>;
 				hisilicon,clkmux-table = <0 0x10>;
@@ -303,6 +315,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				hiword;
 				clock-output-names = "rclk_mmc3";
 				hisilicon,clkmux-reg = <0x140 0x200>;
 				hisilicon,clkmux-table = <0 0x200>;
@@ -311,6 +324,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				hiword;
 				clock-output-names = "rclk_sd";
 				hisilicon,clkmux-reg = <0x108 0x10>;
 				hisilicon,clkmux-table = <0 0x10>;
@@ -318,6 +332,7 @@
 			refclk_mmc1_parent: refclk@27 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&osc26m &div_mmc1>;
 				clock-output-names = "rclk_mmc1_parent";
 				hisilicon,clkmux-reg = <0x108 0x400>;
@@ -326,6 +341,7 @@
 			refclk_venc: refclk@28 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&pll_peri &pll_usb>;
 				clock-output-names = "rclk_venc";
 				hisilicon,clkmux-reg = <0x10c 0x800>;
@@ -334,6 +350,7 @@
 			refclk_g2d: refclk@29 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&pll_peri &pll_usb>;
 				clock-output-names = "rclk_g2d";
 				hisilicon,clkmux-reg = <0x10c 0x20>;
@@ -342,6 +359,7 @@
 			refclk_vdec: refclk@30 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&pll_peri &pll_usb>;
 				clock-output-names = "rclk_vdec";
 				hisilicon,clkmux-reg = <0x110 0x20>;
@@ -350,6 +368,7 @@
 			refclk_vpp: refclk@31 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&pll_peri &pll_usb>;
 				clock-output-names = "rclk_vpp";
 				hisilicon,clkmux-reg = <0x110 0x800>;
@@ -358,6 +377,7 @@
 			refclk_ldi0: refclk@32 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&pll_peri &pll_usb &pll_hdmi>;
 				clock-output-names = "rclk_ldi0";
 				hisilicon,clkmux-reg = <0x114 0x6000>;
@@ -366,6 +386,7 @@
 			refclk_ldi1: refclk@33 {
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
+				hiword;
 				clocks = <&pll_peri &pll_usb &pll_hdmi>;
 				clock-output-names = "rclk_ldi1";
 				hisilicon,clkmux-reg = <0x118 0xc000>;
@@ -639,6 +660,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc32k &pwm_divider>;
+				hiword;
 				clock-output-names = "pwm0_mux";
 				hisilicon,clkmux-reg = <0x104 0x400>;
 				hisilicon,clkmux-table = <0 0x400>;
@@ -647,6 +669,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc32k &pwm_divider>;
+				hiword;
 				clock-output-names = "pwm1_mux";
 				hisilicon,clkmux-reg = <0x104 0x800>;
 				hisilicon,clkmux-table = <0 0x800>;
diff --git a/drivers/clk/hisilicon/clk-hi3xxx.c b/drivers/clk/hisilicon/clk-hi3xxx.c
index 1e59f2c11f6b..a277992dee72 100644
--- a/drivers/clk/hisilicon/clk-hi3xxx.c
+++ b/drivers/clk/hisilicon/clk-hi3xxx.c
@@ -246,7 +246,7 @@ static void __init hi3620_clkmux_setup(struct device_node *np)
 	struct clk *clk;
 	const char *clk_name, **parent_names = NULL;
 	u32 rdata[2], mask, *table = NULL;
-	u8 num_parents, shift;
+	u8 num_parents, shift, flag = 0;
 	void __iomem *reg, *base;
 	int i, ret;
 
@@ -259,6 +259,10 @@ static void __init hi3620_clkmux_setup(struct device_node *np)
 	if (of_property_read_u32_array(np, "hisilicon,clkmux-reg",
 				       &rdata[0], 2))
 		return;
+
+	if (of_property_read_bool(np, "hiword"))
+		flag = CLK_MUX_HIWORD_MASK;
+
 	ret = hi3xxx_parse_mux(np, &num_parents, table);
 	if (ret)
 		return;
@@ -274,7 +278,7 @@ static void __init hi3620_clkmux_setup(struct device_node *np)
 	mask = rdata[1] >> shift;
 	clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
 				     CLK_SET_RATE_PARENT, reg, shift, mask,
-				     CLK_MUX_HIWORD_MASK, table,
+				     flag, table,
 				     &hs_clk.lock);
 	if (IS_ERR(clk))
 		goto err_clk;