diff options
| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2014-07-01 16:06:17 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@linaro.org> | 2014-07-01 16:06:17 +0800 |
| commit | d760dc5f6fe1f24f1dc7e2837c107b4e8465af55 (patch) | |
| tree | 0aded894cf74576462bf9721ded79d6c154c5fc8 | |
| parent | d6593c7a7531b940138c1ec44ce85c22d0a8a89c (diff) | |
kvm: arm64: remove parsing apr offset from hw_cfg
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| -rw-r--r-- | arch/arm64/kvm/hyp.S | 24 |
1 files changed, 4 insertions, 20 deletions
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 34b6c202ee64..2dbe337d74eb 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -402,9 +402,7 @@ __kvm_hyp_code_start: ldr w8, [x2, #GICH_EISR1] ldr w9, [x2, #GICH_ELRSR0] ldr w10, [x2, #GICH_ELRSR1] - ldr w11, [x3, #VGIC_CPU_HW_CFG] - mov w11, w11, lsr #HWCFG_APR_SHIFT - ldr w11, [x2, w10] + ldr w11, [x2, #GICH_APR] CPU_BE( rev w4, w4 ) CPU_BE( rev w5, w5 ) CPU_BE( rev w6, w6 ) @@ -427,13 +425,8 @@ CPU_BE( rev w11, w11 ) str wzr, [x2, #GICH_HCR] /* Save list registers */ + add x2, x2, #GICH_LR0 ldr w4, [x3, #VGIC_CPU_HW_CFG] - mov w6, w4, lsr #HWCFG_APR_SHIFT - ldr w7, =HWCFG_NR_LR_MASK - and w4, w4, w7 - /* the offset between GICH_APR and GICH_LR0 is 0x10 */ - add w6, w6, 0x10 - add x2, x2, w6 add x3, x3, #VGIC_CPU_LR 1: ldr w5, [x2], #4 CPU_BE( rev w5, w5 ) @@ -468,20 +461,11 @@ CPU_BE( rev w6, w6 ) str w4, [x2, #GICH_HCR] str w5, [x2, #GICH_VMCR] - ldr w4, [x3, #VGIC_CPU_HW_CFG] - mov w4, w4, #HWCFG_APR_SHIFT - str w6, [x2, w4] + str w6, [x2, #GICH_APR] /* Restore list registers */ + add x2, x2, #GICH_LR0 ldr w4, [x3, #VGIC_CPU_HW_CFG] - mov w6, w4, #HWCFG_APR_SHIFT - /* the offset between GICH_APR and GICH_LR0 is 0x10 */ - add w6, w6, #0x10 - /* get offset of GICH_LR0 */ - add x2, x2, w6 - /* get NR_LR from VGIC_CPU_HW_CFG */ - ldr w6, =HWCFG_NR_LR_MASK - and w4, w4, w6 add x3, x3, #VGIC_CPU_LR 1: ldr w5, [x3], #4 CPU_BE( rev w5, w5 ) |