diff options
| author | Zhou Wang <wangzhou1@hisilicon.com> | 2014-05-14 11:18:03 +0800 |
|---|---|---|
| committer | Zhou Wang <wangzhou1@hisilicon.com> | 2014-05-14 11:24:20 +0800 |
| commit | d9629ba5ff7b56b8a78b6a6b76c1c73af0261e57 (patch) | |
| tree | 6aa9789de47d6046d1b6f0e6d6d78d05bd2486a3 | |
| parent | 7d56d1975db0bc43a839c83ddf4fc0a894f361de (diff) | |
ARM: dts: hip04:add gpio piecestracking-hilt-d01-gpio-0514
Hisilicon Soc hip04 has four gpio controllers, each one has 32
gpios and can be configured to be an interrupt controller.The gpio
controllers are compatible with the snps,dw-apb-gpio driver.
This patch add the corresponding device tree nodes.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
| -rw-r--r-- | arch/arm/boot/dts/hip04.dtsi | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 080ef18c9c56..d960644b676d 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -315,5 +315,81 @@ id = <2>; phy-handle = <&phy1>; }; + + gpio@4003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4003000 0x1000>; + + gpio3: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 392 4>; + }; + }; + + gpio@4002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4002000 0x1000>; + + gpio2: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 391 4>; + }; + }; + + gpio@4001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4001000 0x1000>; + + gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 390 4>; + }; + }; + + gpio@4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4000000 0x1000>; + + gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 389 4>; + }; + }; }; }; |