diff options
author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-06-08 22:47:19 +0800 |
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committer | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-10-17 16:28:32 +0800 |
commit | 026929744054f27ead5ef3dcc7b5b41a525f03b6 (patch) | |
tree | 01a6f6043271a95c45f7e4edeabda073c5974950 /include | |
parent | 25e7bf7c19dbd730b742d799fd279c5b97cd5e0e (diff) |
clk: gate: add CLK_GATE_HIWORD_MASK
In Rockchip Cortex-A9 based chips, they don't use paradigm of
reading-changing-writing the register contents. Instead they
use a hiword mask to indicate the changed bits.
When b1 should be set as gate, it also needs to indicate the change
by setting hiword mask (b1 << 16).
The patch adds gate flag for this usage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/clk-provider.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 16da26acf6f1..227a20d5b9b2 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -218,6 +218,10 @@ void of_fixed_clk_setup(struct device_node *np); * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock + * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit + * of this register, and mask of gate bits are in higher 16-bit of this + * register. While setting the gate bits, higher 16-bit should also be + * updated to indicate changing gate bits. */ struct clk_gate { struct clk_hw hw; @@ -228,6 +232,7 @@ struct clk_gate { }; #define CLK_GATE_SET_TO_DISABLE BIT(0) +#define CLK_GATE_HIWORD_MASK BIT(1) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, |